View BU7963GUW_4808673.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MSDL (Mobile Shrink Data Link) Transceivers for Mobile Phones
Data rate 1350Mbps RGB Interface
BU7963GUW
No.10058EAT05
Description BU7963GUW is a differential serial interface connecting mobile phone LCD modules to the host CPU. Unique technology is utilized for lower power consumption and EMI. MSDL minimizes the number of wires required - an important consideration in hinge phones - resulting in greater reliability and design flexibility. Features 1) MSDL3 high-speed differential interface with a maximum transfer rate of 1350 Mbps. 2) Compatible with24-bit RGB video mode for LCD controller-to-LCD interface. 3) Pixel clock frequency range from 4 to 45MHz. 4) Depending on the data transfer rate, one, two or three differential data channels can be selected. Applications Serial Interface for LCD Display Interface of Mobile Devices Application. Absolute Maximum Ratings: Parameter Power Supply Voltage Input Voltage Output Voltage Input Current Output Current Preservation Temperature
Symbol DVDD MSVDD VIN VOUT IIN IOUT Tstg
Ratings -0.3 ~ +2.5 -0.3 ~ +2.5 -0.3 ~ MSVDD+0.3 -0.3 ~ DVDD+0.3 -0.3 ~ MSVDD+0.3 -0.3 ~ DVDD+0.3 -10 ~ +10 -70 ~ +70 -55 ~ +125
Unit V V V V V V mA mA
Remarks I/O terminals of MSVDD line I/O terminals of DVDD line I/O terminals of MSVDD line I/O terminals of DVDD line -
Operating Conditions: Parameter Supply Voltage for DVDD Supply Voltage for MSVDD Data Transmission Rate Operating Temperature Range Symbol VDVDD VMSVDD DR Topr Ratings Min 1.65 1.65 120 -30 Typ 1.80 1.80 25 Max 1.95 1.95 450 85 Unit V V Mbps/ch Conditions VDVDD = VMSVDD -
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
1/19
2010.04 - Rev.A
BU7963GUW
Package View
Technical Note
1PIN MARK
LOT NO.
5.00.1
0.9 MAX
5.00.1 S 0.10 B 8 P = 0.5x7 0.750.1
BU7963
0.08
S
A 0.750.1 63-0.2950.05 0.05
M
P = 0.5x7 0.5
S AB H G F E D C B A 2 3 4 5 6 7
1
(UNIT:mm)
Fig.1. Package View (VBGA063W050)
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
2/19
2010.04 - Rev.A
BU7963GUW
Block Diagram
DVDD
Technical Note
MSVDD High Speed I/F Parallel to Serial D0+ D0-
PD[26:0] I/F Logic CKD Odd Parity
D1+ D1-
D2+ D2Timing Generator Tx
PCLK
PCLK Control
PLL Tx
CLK+ CLK-
XSD Clock Detection Reset Generator
LS[1:0] RVS POL_PCLK PLL_BW TEST[1:0]
Control Logic
Reference
DRVR
DGND
MSGND
Fig.2. Block Diagram
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
3/19
2010.04 - Rev.A
BU7963GUW
Pin Layout 1 2 3 4 5 6 7
Technical Note
8
A
TEST0
PD19
PD17
PD16
PD14
PD13
PD10
CKD
B
PCLK
PD18
PD15
PD12
PD11
PD9
PD8
C
PD22
PD20
PLL_BW
DVDD
N.C.
RVS
PD7
PD6
D
PD23
PD21
N.C.
DGND
DGND
DVDD
PD4
PD5
E
PD25
PD24
DVDD
DGND
MSGND
N.C.
PD1
PD3
F
PD26
LS0
MSVDD
MSGND
MSVDD
N.C.
XSD
PD2
G
LS1
POL_ PCLK
D2+ (D0+)
D1+ (CLK+)
CLK+ (D1+)
D0+ (D2+)
N.C.
PD0
H
N.C.
N.C.
D2(D0-)
D1(CLK-)
CLK(D1-)
D0(D2-)
DRVR
TEST1
Fig.3. Pin Layout (Top View)
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
4/19
2010.04 - Rev.A
BU7963GUW
Pin Functions Table 1. Power Supply and Ground Power Supply / Ground : Name DVDD MSVDD DGND MSGND Width 3 2 3 2 CMOS I/O and logic core power supply. Analog core power supply. CMOS I/O and logic core ground. Analog core ground. 10-pin Functions
Technical Note
Table 2. MSDL3 High-Speed Serial Interface Name CLK+ Width 1 Level Analog 8-pin I/O O Functions CLK+ pin When RVS = `L' : CLK+ When RVS = `H' : D1+ CLK- pin When RVS = `L' : CLKWhen RVS = `H' : D1D0+ pin When RVS = `L' : D0+ When RVS = `H' : D2+ D0- pin When RVS = `L' : D0When RVS = `H' : D2D1+ pin When RVS = `L' : D1+ When RVS = `H' : CLK+ D1- pin When RVS = `L' : D1When RVS = `H' : CLKD2+ pin When RVS = `L' : D2+ When RVS = `H' : D0+ D2- pin When RVS = `L' : D2When RVS = `H' : D0Shutdown Hi-Z Equivalent Schematic D
CLK-
1
Analog
O
Hi-Z
D
D0+
1
Analog
O
Hi-Z
D
D0-
1
Analog
O
Hi-Z
D
D1+
1
Analog
O
Hi-Z
D
D1-
1
Analog
O
Hi-Z
D
D2+
1
Analog
O
Hi-Z
D
D2-
1
Analog
O
Hi-Z
D
Table 3. Analog Analog Name DRVR 1-pin Width 1 Level Analog I/O Functions 10k5% register should be connected between DRVR and MSGND. Shutdown Equivalent Schematic D
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
5/19
2010.04 - Rev.A
BU7963GUW
Table 4. Parallel Data Interface Parallel Data Interface Name PCLK Width 1 29-pin Level CMOS I/O I PCLK interface. Functions
Technical Note
Shutdown Input
Equivalent Schematic A
PD[26:0]
27
CMOS
I
Parallel data interface. Output of PCLK detection result. `L': clock stop. `H': clock detect.
Input
A
CKD
1
CMOS
O
`L'
C
Table 5. Control Control Name XSD 8-pin Width 1 Level CMOS I/O I Shutdown pin. `L': shutdown. `H': normal operation. Selection of the number of data channel and the data format. Refer to "Selection of the number of MSDL3 channels". Set the same number of data channel between the TX device and the RX device. Selection of MSDL3 pins assignment. `L': Default matrix. `H': Flipped matrix. Selection of PLL bandwidth. Selection of input clock polarity. `L': sample parallel data at falling. `H': sample parallel data at rising. Test mode pin. `L': normal mode. `H': test mode. Must be `L.' Functions Shutdown Input Equivalent Schematic A
LS0
1 CMOS I
Input
A
LS1
1
RVS
1
CMOS
I
Input
A
PLL_BW
1
CMOS
I
Input
A
POL_PCLK
1
CMOS
I
Input
A
TEST0
1 Pull down I
B Input B
TEST1
1
DVDD
DVDD
DVDD
MSVDD
A
B
C Fig.4. Equivalent Schematics
D
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
6/19
2010.04 - Rev.A
BU7963GUW
Technical Note
Operation Control MSDL3 Channel Count Selection Pin LS is used to control the high-speed data channel count and data format. The LS pin settings (i.e., high-speed data channel count, data format) should be the same between the transmitting and receiving devices (the BU7963GUW and BU7964GUW, respectively). Table 6 shows the PCLK input frequency ranges and transmission data rate ranges for the LS pin settings. Table 6. The Range of The Transmission Data rate LS1 `L' `L' `H' `H' LS0 `L' `H' `L' `H'
The Number of Data Channel The Range of PCLK Input Frequency [MHz] The Range of The Data Transmission Rate [Mbits/sec]
1-channel 2-channel 3-channel
4.0-15.0 8.0-30.0 12.0-45.0 Inhibit setting.
120-450 240-900 360-1350
MSDL3 Pin Assignment RVS determines the assignment of MSDL3 pins, CLK+ / CLK-, D0+ / D0-, D1+ / D1- and D2+ / D2-. Only the MSDL3 high-speed signaling pins are affected by RVS, while pin assignment of other functions does not change. User can select the assignment from `straight' (default) and `flipped' assignment in order to minimize channel-to-channel skew in PWB design. Table 7 shows the MSDL3 pin assignment, and Fig.5 shows the `straight' and `flipped' Table 7. MSDL3 Pin Assignment MSDL3 Pin Assignment `Straight' (default matrix) `Flipped'
RVS `L' `H'
Top View RVS='L' Default MSDL3 terminal assignment G H 1 2
D2+ D1+ CLK+ D0+
D2-
D1-
CLK-
D0-
3
4
5
6
7
8
(a) `Straight' Pin Assignment
Top View RVS='H' Flipped MSDL3 terminal assignment G H 1 2
D0+ CLK+ D1+ D2+
D0-
CLK-
D1-
D2-
3
4
5
6
7
8
(b) `Flipped' Pin Assignment Fig.5. MSDL3 Pin Assignment
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
7/19
2010.04 - Rev.A
BU7963GUW
Technical Note
PCLK Polarity Selection BU7963GUW controls PCLK input polarity by POL_PCLK setting. Table 8 shows PCLK input polarity. Table 8. PCLK Polarity Selection Parallel Data Capturing Polarity Capture parallel data at falling edge. Capture parallel data at rising edge.
POL_PCLK `L' `H' (default)
PLL Bandwidth Selection BU7963GUW controls the range of the CLK+ / CLK- input frequency (= PCLK output frequency) by the setting of the data format (LS1, and LS0) of the high-speed data channel and the bandwidth setting of PLL_BW. Table 9. PLL_BW Setting CLK+ / CLK- Frequency Range [MHz] (PCLK Input Frequency) PLL_BW Min Max `L' `H' `L' `H' `L' `H' 4 7 8 14 12 21 8 15 16 30 24 45
LS1 `L' `L' `L' `L' `H' `H'
LS0 `L' `L' `H' `H' `L' `L'
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
8/19
2010.04 - Rev.A
BU7963GUW
Power Modes BU7963GUW has three power modes.
Technical Note
1) Shutdown Mode BU7963GUW goes to Shutdown Mode when XSD = `L'. All logic circuits are initialized in the Shutdown Mode. All high-speed signaling channels are disabled, and the outputs keep Hi-Z status. 2) Standby Mode BU7963GUW goes to Standby Mode when XSD = `H' and PCLK is not provided. All high-speed signaling channel outputs keep Hi-Z status. BU7963GUW is monitoring whether PCLK input is running or not and the link switches to Active Mode when PCLK running is detected. 3) Active Mode BU7963GUW goes to Active Mode when XSD = `H' and PCLK is running. All high-speed signaling channels are enabled. Table 10. Power Modes
Power Mode Shutdown Standby Active Input XSD `L' `H' `H' PCLK Static (`L' or `H') Static (`L' or `H') Clock input is active Operation Functions MSDL3 Terminals Initialized Disabled (Hi-Z) PCLK detection Disabled (Hi-Z) PCLK detection Normal operation Enabled (P2S conv)
4) Power Modes Transition Fig.6 shows the transition of power modes. XSD = "L"
Shutdown
XSD = "H"
Standby
PCLK input stopped
PCLK input detected
Active
Fig.6. Power Modes Transition
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
9/19
2010.04 - Rev.A
BU7963GUW
High-Speed Data Channel Protocols Fig.7, Fig.8 and Fig.9 show high-speed data channel protocols.
Technical Note
D0channel CLK channel
CP
PD26
PD25 PD24
PD23
PD22 PD21 PD20
PD19
PD18 PD17
PD16 PD15
PD14 PD13 PD12
Frame start/end PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 res res CP PD26 PD25
Fig.7. MSDL3 Protocol for 1-channel Data (27-bit)
D0channel CP D1channel res CLK channel
Frame start/end
PD26 PD25 PD24 PD23 PD22 PD21 PD20 PD19 PD18 PD17 PD16 PD15 PD2 res CP PD26
PD14 PD13 PD12 PD11 PD10
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD1
PD0
res
PD14
Fig.8. MSDL3 Protocol for 2-channel Data (27-bit)
D0channel CP
PD26 PD25 PD24 PD23 PD22 PD21 PD20 PD19 PD18 PD17 PD16 PD15 PD2 res CP PD26
CLK channel
Frame start/end
Fig.9. MSDL3 Protocol for 1-channel Data (13-bit) "res" is reserved bit for the future use, the default state of those is `0.' CP is the parity bit of data payload. BU7961GUW adds an odd parity on CP of the high-speed channel data. When the number of `H' bits in parallel data is even, CP bit is `H.' When the number of `H' bits in parallel data is odd, CP bits is `L.'
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
10/19
2010.04 - Rev.A
BU7963GUW
Electrical Characteristics 1) DC Characteristics Table 11. Digital Input / Output DC Characteristics
Ta=25C, DVDD=MSVDD=1.80V and DGND=MSGND=0.00V, unless otherwise noted.
Technical Note
Parameter `L' Input Voltage 1 `H' Input Voltage 1 `L' Input Current 1 `H' Input Current 1 `L' Input Current 2 `H' Input Current 2 `L' Output Voltage 1 `H' Output Voltage 1
Symbol VIL1 VIH1 IIL1 IIH1 IIL2 IIH2 VOL1 VOH1
Limits Min DGND 0.7 x DVDD -5 -5 -5 -5 DGND 0.7 x DVDD Typ Max 0.3 x DVDD DVDD +5 +5 +5 +5 0.3 x DVDD DVDD
Unit V V A A A A V V
Conditions PCLK, PD[26:0], LS[1:0], RVS, POL_PCLK, XSD, PLL_BW, TEST[1:0] pin PCLK, PD[26:0], LS[1:0], RVS, POL_PCLK, PLL_BW, TEST[1:0] pin VIN = DGND VIN = DVDD VIN = MSGND VIN = MSVDD IO = 1mA,CKD pin IO = -1mA,CKD pin
Table 12 Current Consumption
Ta=25C, DVDD=MSVDD=1.80V and DGND=MSGND=0.00V, unless otherwise noted.
Parameter Shutdown Current Standby Current
Symbol Iop_sht_rx Iop_stb_rx
Limits Min Typ 0.2 0.2 Max 10 10
Unit A A
Conditions XSD = `L', IDVDD + IMSVDD XSD = `H', IDVDD + IMSVDD LS[1:0] = `LL,' PLL_BW[1:0] = `H' DVDD = MSVDD PCLK=15MHz,XSD=`H CL=10pF Total operating current (IDVDD + IMSVDD ) with PD[26:0] inputs to ggling 0x2AAAAAA and 0x5555555 LS[1:0] = `LH,' PLL_BW[1:0] = `H' DVDD = MSVDD PCLK=30MHz,XSD=`H' CL=10pF Total operating current (IDVDD + IMSVDD) with PD[26:0] inputs to ggling 0x2AAAAAA and 0x5555555 LS[1:0] = `HL,' PLL_BW[1:0] = `H' DVDD = MSVDD PCLK=45MHz,XSD=`H' CL=10pF Total operating current (IDVDD + IMSVDD) with PD[26:0] inputs to ggling 0x2AAAAAA and 0x5555555
Active Current 1-channel / 27-bit Format
Iop_act_rx1
-
14.0
18.5
mA
Active Current 2-channel / 27-bit Format
Iop_act_rx2
-
19.7
25.7
mA
Active Current 3-channel/ 27-bit Format
Iop_act_rx3
-
25.4
32.9
mA
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
11/19
2010.04 - Rev.A
BU7963GUW
2) AC Characteristics Parallel Data Input Timing
Technical Note
tTX_DS
tTX_DH
0.7xDVDD
PD[26:0]
0.3xDVDD
0.7xDVDD
PCLK
tTX_R1/tTX_R2
tTX_F1/tTX_F2
0.3xDVDD
Fig.10 Parallel Data Input AC Timing Table 13. Parallel Data Input AC Timing
Ta=25C, DVDD=MSVDD=1.80V and DGND=MSGND=0.00V, unless otherwise noted.
Parameter
Symbol fTX_PCLK1
Limits Min 4 8 12 33 5.0 5.0 Typ Max 15 30 45 67 10 5 10 5
Unit MHz MHz MHz % ns ns ns ns ns ns
Conditions LS0=L, LS1=L LS0=H, LS1=L LS0=L, LS1=H POL_PCLK=H POL_PCLK=H PCLK Frequency30MHz PCLK Frequency30MHz PCLK Frequency30MHz PCLK Frequency30MHz
PCLK Input Frequency PCLK Input Duty Cycle Input Data Setup Time Input Data Hold Time Input Signal Rise Time 1 Input Signal Rise Time 2 Input Signal Fall Time 1 Input Signal Fall Time 2
fTX_PCLK2 fTX_PCLK3 tTX_DUTY tTX_DS tTX_DH tTX_R1 tTX_R2 tTX_F1 tTX_F2
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
12/19
2010.04 - Rev.A
BU7963GUW
3) Serial Data Input Timing Fig.11 and Table 14 shows Serial Data Input Timing of BU7963GUW.
1.0000 xUI
Technical Note
CLK+/ -
tTXO _N
tTXO _N
tTXON _
tTXO _N
D0+/ -
UI = (1 cycle time of CLK +/ - ) / 30 N = Bit position (0 N 30 )
Fig.11. Serial Data input AC Timing Table 14. Serial Data input AC Timing
Ta=25C, DVDD=MSVDD=1.80V and DGND=MSGND=0.00V, unless otherwise noted.
Parameter Output location CLKL+/- of N bit
Symbol tTXO_N
Limits Min -0.1845xUI + UIxN Typ UIxN Max 0.1845xUI + UIxN
Unit sec
Conditions
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
13/19
2010.04 - Rev.A
BU7963GUW
4) Power-On / Off Sequence Power-On Sequence Fig.12 shows power-on sequence of BU7963GUW.
Technical Note
DVDD,MSVDD of Tx XSD of Tx PCLK of Tx Tx MSDL3 Output
Stopped HiZ
tTX_VDD_XSD t TX_IN_VAL
Provided
tTX_OUT_VAL
Valid
DVDD,MSVDD of Rx XSD of Rx Rx Power mode Rx All Outputs
tRX_VDD_XSD t RX_IN_VAL
Shutdown Standby / Active
t RX_OUT_VAL
Initial Value Valid Outputs
Tx: BU7963GUW Rx: BU7964GUW Fig.12. Power-On / Off Sequence Table 15. Power-On Sequence Timing
Ta=25C, DVDD=MS VDD=1.80V, and DGND=MSGND=0.00V, unless otherwise noted.
Parameter Core power supply startup time Reset Valid After Power Supplied PCLK clock input startup time MSDL3 output delay time
Symbol tTX_VDD_IOV tTX_VDD_XSD tTX_IN_VAL tTX_OUT_VAL
Limits Min 0.0 10 10 Typ Max 2 2
Unit ms s s ms
Conditions
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
14/19
2010.04 - Rev.A
BU7963GUW
Power-Off Sequence Fig.13 shows the power-off sequence of BU7963GUW.
Technical Note
PCLK of Tx
Provided
Stopped
t
Tx MSDL3 Output
Valid
TX_ OUT_ INV
HiZ
t RX_OUT_INV
Rx All Outputs
Valid Outputs Initial Value
XSD of Tx DVDD,MSVDD of Tx XSD of Rx DVDD,MSVDD of Rx
t TX_XSD_VDD
t RX_XSD_VDD
Tx: BU7963GUW Rx: BU7964GUW Fig.13. Power-Off Sequence Table 16. Power-Off Sequence Timing
Ta=25C, DVDD=MSVDD=1.80V, and DGND=MSGND=0.00V, unless otherwise noted.
Parameter MSDL3 output delay time XSD hold time Core power off time
Symbol tTX_OUT_INV tTX_XSD_VDD tTX_VDD_IOV
Limits Min 10 0.0 Typ Max 100 2
Unit s s ms
Conditions
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
15/19
2010.04 - Rev.A
BU7963GUW
Frequency Change Sequence Fig.14 shows the frequency change sequence of BU7963GUW.
DVDD, MSVDD of Tx and Rx
Technical Note
XSD of Tx PCLK of Tx
tTX_XSD_OUT
Frequency1
tTX_IN_XSD
Frequency2
tTX_XSD_CTL
PLL_BW of Tx State1
tTX_CTL_XSD
State2
XSD of Rx
tRX_XSD_CTL
PLL_BW[1:0] of Rx State1
tRX_CTL_XSD
State2 TxBU7963GUW RxBU7964GUW
Fig.14. Frequency Change Sequence Table 17. Frequency Change Sequence
Ta=25C, DVDD=MSVDD=1.80V, and DGND=MSGND=0.00V, unless otherwise noted.
Parameter PCLK Clock Input Suspend Time PCLK Clock Input Restart Time Control Signal Hold Time Control Signal Setup Time
Symbol tTX_XSD_OUT tTX_IN_XSD tTX_XSD_CTL tTX_CTL_XSD
Limits Min 1.0 1.0 2.0 2.0 Typ Max -
Unit s s s s
Conditions
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
16/19
2010.04 - Rev.A
BU7963GUW
High-speed Channel Characteristic Table 18. High-speed channel characteristic
Ta=25C, DVDD=MSVDD=1.80V and DGND=MSGND=0.00V, unless otherwise noted.
Technical Note
Parameter Differential Voltage Range Common Mode Voltage Range Vdiff_tx Rise Time Vdiff_tx Fall Time Operating Frequency TX Hi-Z State Leak Current
Symbol Vdiff_tx Vcm_tx tr_tx tf_tx fopr_tx ILEAK_TX
Limits Min 100 0.8 200 200 -3 Typ 150 0.9 Max 200 1.0 500 500 225 3
fopr_tx
Unit mVpp V ps ps MHz A
Conditions
Shutdown mode or standby mode
OutP(D0+,D1+,D2+) Vcm_tx OutN(D0-,D1-,D2-)
Single-ended
20% Differential (OutP-OutN) Vdiff_tx
0
60% 20% tr_tx tf_tx
Fig.15. High-Speed Channel Electrical Characteristics Fig.16 shows high-speed channel equivalent schematic. MSDL3 TX MSVDD Transmission line MSDL3 RX
VO+
ILEAK_TX
ILEAK_RX MSVDD
RTX/ 2
RRX/ 2
VI+ VI-
Logical input to MSDL3 TX
RTX/ 2
RRX/ 2
Logical output from MSDL3 RX MSGND MSVDD
VO- I LEAK_ TX
ILEAK_RX
IPULL_RX MSGND MSGND
V CM
VLINK_RX MSGND
Link detection comparator output
Fig.16. high-speed channel equivalent schematic.
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
17/19
2010.04 - Rev.A
BU7963GUW
Application Circuit Example
1.8V 0.1x3 100px3 1.8V 0.1x2 100px2 1.8V 1.8V 0.1x3 0.1x2 100px2 100px3
Technical Note
MSGND
DGND
MSVDD
MSGND
MSVDD
MPU
1.8V GND
1.8V GND
DVDD
DGND
DVDD
Video Mode LCD Controller
CLK+ Pixel clock 27 PD[26:0] CKD PCLK CLKD0+ D0D1+ D1D2+ D2-
CLK+ CLKD0+ D0D1+ D1D2+ D2PCLK Pixel clock 27 PD[26:0] CPO PLLBW1 PLLBW0
10K5% 10K5%
BU7963GUW Tx device
BU7964GUW Rx device
R[7:0],G[7:0],B[7:0], HS,VS,DE
R[7:0],G[7:0],B[7:0], HS,VS,DE
DVD D Reset
DVDD
RVS TEST[1:0] XSD
F_XS TEST[1:0] XSD
DGND
MSGND
MSGND
DGND
Fig.17. Application circuit
PCB Layout for MSDL3 The following points should be considered about the wiring for PCB of MSDL3. Wire for the PCB wiring pattern of high-speed channel (CLK, D0+/-, D1+/-, D2+/-) as short as possible. The PCB wiring for high-speed channel must not use the through-hole. Do not bend the wiring for high-speed channel squarely. Make the wiring length of each high-speed channel the same length (within 0.5mm).
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
Reset
PLLBW POL_PCLK LS1 LS0
DRVR
DRVR
LS1 LS0
WVGA LCD panel
18/19
2010.04 - Rev.A
BU7963GUW
Ordering Part Number
Technical Note
B
U
7
Part No.
9
6
3
G
U
W
-
E
2
Part No.
Package GUW: VBGA063W050
Packaging and forming specification E2: Embossed tape and reel
VBGA063W050

1PIN MARK 5.00.1
5.0 0.1
Tape Quantity
0.1 0.9MAX
Embossed carrier tape (with dry pack) 2500pcs E2
The direction is the 1pin of product is at the upper left when you hold
S
Direction of feed
( reel on the left hand and you pull out the tape on the right hand
)
0.08 S 63- 0.2950.05 0.05 M S AB
H G F E D C B A
P=0.5x7 0.5 A
0.750.1
B
0.5
12345678
0.75 0.1
P=0.5x 7
1pin
Direction of feed
(Unit : mm)
Reel
Order quantity needs to be multiple of the minimum quantity.
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
19/19
2010.04 - Rev.A
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuelcontroller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact us.
ROHM Customer Support System
http://www.rohm.com/contact/
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
R1010A

▲Up To Search▲

Price & Availability of BU7963GUW

	To Download BU7963GUW Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .