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6.5 Gbps Dual Buffer Mux/Demux AD8155
FEATURES
Dual 2:1 mux/1:2 demux Optimized for dc to 6.5 Gbps NRZ data Per-lane P/N pair inversion for routing ease Programmable input equalization Compensates up to 40 inches of FR4 Loss-of-signal detection Programmable output preemphasis up to 12 dB Programmable output levels with squelch and disable Accepts ac-coupled or dc-coupled differential CML inputs 50 on-chip termination 1:2 demux supports unicast or bicast operation Port-level loopback Port or single lane switching 1.8 V to 3.3 V flexible core supply User-settable I/O supply from VCC to 1.2 V Low power, typically 2.0 W in basic configuration 64-lead LFCSP -40C to +85C operating temperature range
FUNCTIONAL BLOCK DIAGRAM
RECEIVE EQUALIZATION Ix_A[1:0] EQ 2:1 Ix_B[1:0] EQ Ox_C[1:0] TRANSMIT PREEMPHASIS
Ox_A[1:0] 1:2 Ox_B[1:0] DUAL 2:1 MULTIPLEXER/ 1:2 DEMULTIPLEXER EQ Ix_C[1:0]
TRANSMIT PREEMPHASIS
RECEIVE EQUALIZATION
SCL SDA I2C_A[2:0]
I2C CONTROL LOGIC CONTROL LOGIC
APPLICATIONS
Low cost redundancy switch SONET OC48/SDH16 and lower data rates RXAUI, 4x Fibre Channel, Infiniband, and GbE over backplane OIF CEI 6.25 Gbps over backplane Serial data-level shift 2-/4-/6-lane equalizers or redrivers
AD8155
Figure 1.
GENERAL DESCRIPTION
The AD8155 is an asynchronous, protocol-agnostic, dual-lane 2:1 switch with a total of six differential CML inputs and six differential CML outputs. The signal path supports NRZ signaling with data rates up to 6.5 Gbps per lane. Each lane offers programmable receive equalization, programmable output preemphasis, programmable output levels, and loss-ofsignal detection. The nonblocking switch core of the AD8155 implements a 2:1 multiplexer and 1:2 demultiplexer per lane and supports independent lane switching through the two select pins, SEL[1:0]. Each port is a two-lane link. Every lane implements an asynchronous path supporting dc to 6.5 Gbps NRZ data, fully independent of other lanes. The AD8155 has low latency and very low lane-to-lane skew.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
The main application of the AD8155 is to support redundancy on both the backplane and the line interface sides of a serial link. The demultiplexing path implements unicast and bicast capability, allowing the part to support either 1 + 1 or 1:1 redundancy. The AD8155 is also suited for testing high speed serial links because of its ability to duplicate incoming data. In a portmonitoring application, the AD8155 can maintain link connectivity with a pass-through connection from Port C to Port A while sending a duplicate copy of the data to test equipment on Port B. The rich feature set of the AD8155 can be controlled either through external toggle pins or by setting on-chip control registers through the I2C(R) interface.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2009 Analog Devices, Inc. All rights reserved.
08262-001
LB_A LB_B LB_C PE_A PE_B PE_C EQ_A EQ_B EQ_C SEL[1:0] BICAST SEL4G RESET LOS_INT
AD8155 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 I2C Timing Specifications ............................................................ 5 Absolute Maximum Ratings............................................................ 6 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ............................................. 9 Theory of Operation ...................................................................... 15 The Switch (Mux/Demux/Unicast/Bicast/Loopback) ........... 16 Receivers ...................................................................................... 18 Loss of Signal (LOS) ................................................................... 20 Transmitters ................................................................................ 21 AD8155 Power Consumption .................................................. 22 I2C Control Interface ...................................................................... 24 Serial Interface General Functionality..................................... 24 I2C Interface Data Transfers: Data Write ................................ 24 I2C Interface Data Transfers: Data Read ................................. 25 Applications Information .............................................................. 26 Output Compliance ................................................................... 27 Signal Levels and Common-Mode Shift for AC-Coupled and DC-Coupled Outputs ................................................................ 28 Supply Sequencing ..................................................................... 30 Single Supply vs. Multiple Supply Operation ......................... 30 Initialization Sequence for Low Power and LOS_INT Operation .................................................................................... 30 Printed Circuit Board (PCB) Layout Guidelines ................... 31 Register Map ................................................................................... 33 Outline Dimensions ....................................................................... 35 Ordering Guide .......................................................................... 35
REVISION HISTORY
7/09--Revision 0: Initial Version
Rev. 0 | Page 2 of 36
AD8155 SPECIFICATIONS
VCC = VTTI = VTTO = 1.8 V, DVCC = 3.3 V, VEE = 0 V, RL = 50 , basic configuration 1 , data rate = 6.5 Gbps, data pattern = PRBS7, accoupled inputs and outputs, differential input swing = 800 mV p-p, TA = 25C, unless otherwise noted. Table 1.
Parameter DYNAMIC PERFORMANCE Data Rate/Channel (NRZ) Deterministic Jitter (No Channel) Random Jitter (No Channel) Residual Deterministic Jitter with Receive Equalization Residual Deterministic Jitter with Transmit Preemphasis Propagation Delay Lane-to-Lane Skew Switching Time Output Rise/Fall Time INPUT CHARACTERISTICS Differential Input Voltage Swing Conditions Min DC Data rate = 6.5 Gbps, EQ setting = 0 RMS, data rate = 6.5 Gbps Data rate 6.5 Gbps, 20 inch FR4 Data rate 6.5 Gbps, 40 inch FR4 Data rate 6.5 Gbps, 10 inch FR4 Data rate 6.5 Gbps, 30 inch FR4 50% input to 50% output (maximum EQ) Signal path and switch architecture is balanced and symmetric (maximum EQ) 50% logic switching to 50% output data 20% to 80% (PE = lowest setting) VICM 2 = VCC - 0.6 V, VCC = VMIN to VMAX, TA = TMIN to TMAX, LOS control register = 0x05 Single-ended absolute voltage level, VL minimum Single-ended absolute voltage level, VH maximum Differential, PE = 0, default output level, @ dc TX_HEADROOM = 0, VL minimum TX_HEADROOM = 0, VH maximum TX_HEADROOM = 1, VL minimum TX_HEADROOM = 1, VH maximum Port A/B/C, PE_A/B/C = minimum Port A/B/C, PE_A/B/C = 6 dB, VOD = 800 mV p-p Differential, VCC = VMIN to VMAX, TA = TMIN to TMAX 90 590 200 22 1 30 40 35 42 700 90 150 62 2000 Typ Max 6.5 Unit Gbps ps p-p ps ps p-p ps p-p ps p-p ps p-p ps ps ns ps mV p-p diff
Input Voltage Range OUTPUT CHARACTERISTICS Output Voltage Swing Output Voltage Range, SingleEnded Absolute Voltage Level
VEE + 0.6 VCC + 0.3 725 VCC - 1.1 VCC + 0.6 VCC - 1.3 VCC + 0.6 16 32 100 50 300 110 820
V V mV p-p diff V V V V mA mA mV p-p diff mV p-p diff ns ns
Output Current TERMINATION CHARACTERISTICS Resistance LOS CHARACTERISTICS DC Assert Level DC Deassert Level LOS to Output Squelch LOS to Output Enable POWER SUPPLY Operating Range VCC DVCC VTTI VTTO
LOS control = 0, VID = 0 to 50% OP/ON settling, VCC = 1.8 V LOS control = 0, data present to first valid transition, VCC = 1.8 V
21 67
VEE = 0 V, TX_HEADROOM = 0 VEE = 0 V, TX_HEADROOM = 1 DVCC VCC, VEE = 0 V
1.6 2.2 1.6 1.2 1.2
1.8 to 3.3 3.3 1.8 to 3.3
3.6 3.6 3.6 VCC + 0.3 VCC + 0.3
V V V V V
Rev. 0 | Page 3 of 36
AD8155
Parameter Supply Current ICC VCC = 1.8 V Conditions Min Typ Max Unit
VCC = 3.3 V
LB_x = 0, PE = 0 dB on all ports, low power mode 3 LB_x = 1, PE = 6 dB on all ports, low power mode3 LB_x = 0, PE = 0 dB on all ports, default LB_x = 1, PE = 6 dB on all ports, default LB_x = 0, PE = 0 dB on all ports, low power mode3 LB_x = 1, PE = 6 dB on all ports, low power mode3 LB_x = 0, PE = 0 dB on all ports, default LB_x = 1, PE = 6 dB on all ports, default LB_x = 0, PE = 0 dB on all ports, low power mode3 LB_x = 1, PE = 6 dB on all ports, low power mode3 LB_x = 0, PE = 0 dB on all ports, default LB_x = 1, PE = 6 dB on all ports, default LB_x = 0, PE = 0 dB on all ports, low power mode3 LB_x = 1, PE = 6 dB on all ports, low power mode3 LB_x = 0, PE = 0 dB on all ports, default LB_x = 1, PE = 6 dB on all ports, default
233 406 350 690 254 435 380 735 66 186 66 183 69 195 69 193 10 2 -40
270 480 410 800 300 500 450 850 82 226 82 225 85 230 84 230 20 4 +85
mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA C C/W C/W C V V V V V V
ITTO VTTO = 1.8 V
VTTO = 3.3 V
ITTI IDVCC THERMAL CHARACTERISTICS Operating Temperature Range JA JC Maximum Junction Temperature LOGIC CHARACTERISTICS 4 Input High (VIH) Input Low (VIL) Input High (VIH) Input Low (VIL) Output High (VOH) Output Low (VOL)
1 2 3
Still air; JEDEC 4-layer test board, exposed pad soldered Still air; thermal resistance through exposed pad I2C, SDA, SCL, control pins DVCC = 3.3 V DVCC = 3.3 V DVCC = 1.8 V DVCC = 1.8 V 2 k pull-up resistor to DVCC IOL = +3 mA
21.2 1.1 125 0.7 x DVCC VEE VEE VEE 0.8 x DVCC 0.2 x DVCC DVCC DVCC 0.3 x DVCC DVCC
0.4
Bicast is off, loopback is off on all ports, preemphasis is set to minimum on all ports, and equalization is set to minimum on all ports. VICM is the input common-mode voltage. Low power mode is obtained by following the steps identified in the Initialization Sequence for Low Power and LOS_INT Operation section. 4 EQ control pins (EQ_A, EQ_B, EQ_C) require 5 k in series when DVCC > VCC.
Rev. 0 | Page 4 of 36
AD8155
I2C TIMING SPECIFICATIONS
SDA
tF
tLOW
tR
tSU;DAT
tF
tHD;STA
tR
tBUF
SCL
tHD;STA
S NOTES 1. S = START CONDITION. 2. Sr = REPEAT START. 3. P = STOP.
tHD;DAT
tHIGH
tSU;STA
Sr
tSU;STO
P S
08262-002
Figure 2. I2C Timing Diagram
Table 2. I2C Timing Parameters
Parameter SCL Clock Frequency Hold Time for a Start Condition Setup Time for a Repeated Start Condition Low Period of the SCL Clock High Period of the SCL Clock Data Hold Time Data Setup Time Rise Time for Both SDA and SCL Fall Time for Both SDA and SCL Setup Time for Stop Condition Bus Free Time Between a Stop and a Start Condition Bus Free Time After a Reset Reset Pulse Width Capacitance for Each I/O Pin Symbol fSCL tHD;STA tSU;STA tLOW tHIGH tHD;DAT tSU;DAT tR tF tSU;STO tBUF Min 0 0.6 0.6 1.3 0.6 0 10 1 1 0.6 1 1 10 5 Max 400+ Unit kHz s s s s s ns ns ns s s s ns pF
300 300
Ci
7
Rev. 0 | Page 5 of 36
AD8155 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter VCC to VEE DVCC to VEE VTTI VTTO VCC to DVCC Internal Power Dissipation Differential Input Voltage Logic Input Voltage Storage Temperature Range Junction Temperature Rating 3.7 V 3.7 V Lower of (VCC + 0.6 V) or 3.6 V Lower of (VCC + 0.6 V) or 3.6 V 0.6 V 4.85 W 2.0 V VEE - 0.3 V < VIN < VCC + 0.6 V -65C to +125C 125C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Rev. 0 | Page 6 of 36
AD8155 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
SEL4G VEE VTTO ON_A1 OP_A1 VCC ON_A0 OP_A0 VTTI IN_A1 IP_A1 VCC IN_A0 IP_A0 VEE DVCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
BICAST SEL0 SEL1 IP_C0 IN_C0 VCC IP_C1 IN_C1 VTTI VCC PE_A PE_B PE_C LOS_INT LB_A LB_B
PIN 1 INDICATOR
AD8155
TOP VIEW (Not to Scale)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
LB_C VEE OP_C0 ON_C0 VCC OP_C1 ON_C1 VTTO VCC IP_B0 IN_B0 VCC IP_B1 IN_B1 VTTI VEE
NC = NO CONNECT
NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE MUST BE ELECTRICALLY CONNECTED TO VEE.
SCL SDA I2C_A0 I2C_A1 I2C_A2 RESET VTTO ON_B1 OP_B1 VCC ON_B0 OP_B0 VEE EQ_A EQ_B EQ_C
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 2, 15, 29, 33, 47, ePAD 3, 23, 41 4 5 6, 12, 26, 37, 40, 44, 55, 59 7 8 9, 34, 56 10 11 13 14 16 17 18 19 20 21 22 24 25 27 28 Mnemonic SEL4G VEE VTTO ON_A1 OP_A1 VCC ON_A0 OP_A0 VTTI IN_A1 IP_A1 IN_A0 IP_A0 DVCC SCL SDA I2C_A0 I2C_A1 I2C_A2 RESET ON_B1 OP_B1 ON_B0 OP_B0 Type Control Power Power Output Output Power Output Output Power Input Input Input Input Power Control Control Control Control Control Control Output Output Output Output Description Set Transmitter for Low Speed PE, Active High. Negative Supply. The exposed pad on the bottom of the package must be electrically connected to VEE. Port A, Port B, and Port C Output Termination Supply. High Speed Output Complement. High Speed Output. Positive Supply. High Speed Output Complement. High Speed Output. Port A, Port B, and Port C Input Termination Supply. High Speed Input Complement. High Speed Input. High Speed Input Complement. High Speed Input. Digital Power Supply. I2C Clock Input. I2C Data Input/Output. I2C Address Input (LSB). I2C Address Input. I2C Address Input (MSB). Device Reset, Active Low. High Speed Output Complement. High Speed Output. High Speed Output Complement. High Speed Output.
Rev. 0 | Page 7 of 36
08262-003
AD8155
Pin No. 30 31 32 35 36 38 39 42 43 45 46 48 49 50 51 52 53 54 57 58 60 61 62 63 64 Mnemonic EQ_A EQ_B EQ_C IN_B1 IP_B1 IN_B0 IP_B0 ON_C1 OP_C1 ON_C0 OP_C0 LB_C LB_B LB_A LOS_INT PE_C PE_B PE_A IN_C1 IP_C1 IN_C0 IP_C0 SEL1 SEL0 BICAST Type Control Control Control Input Input Input Input Output Output Output Output Control Control Control Interrupt Control Control Control Input Input Input Input Control Control Control Description Port A Equalizer Control Input. Port B Equalizer Control Input. Port C Equalizer Control Input. High Speed Input Complement. High Speed Input. High Speed Input Complement. High Speed Input. High Speed Output Complement. High Speed Output. High Speed Output Complement. High Speed Output. Port A Loopback Control Input, Active High. Port B Loopback Control Input, Active High. Port C Loopback Control Input, Active High. Loss of Signal Interrupt, Active High. Initialization sequence required; see the Applications Information section. Port A Preemphasis Control Input, Active High. Port B Preemphasis Control Input, Active High. Port C Preemphasis Control Input, Active High. High Speed Input Complement. High Speed Input. High Speed Input Complement. High Speed Input. Lane 1 A/B Switch Control Input. Lane 0 A/B Switch Control Input. Enable Bicast for Port A and Port B Outputs, Active High.
Rev. 0 | Page 8 of 36
AD8155 TYPICAL PERFORMANCE CHARACTERISTICS
DATA OUT 2 50 CABLES 2 INPUT PIN OUTPUT 2 PIN 50 CABLES 2 50 TP2
PATTERN GENERATOR
AD8155
TP1 AC-COUPLED EVALUATION BOARD
HIGH SPEED SAMPLING OSCILLOSCOPE
08262-004
Figure 4. Standard Test Circuit (No Channel)
200mV/DIV
200mV/DIV
25ps/DIV
08262-005
25ps/DIV
Figure 5. 6.5 Gbps Input Eye (TP1 from Figure 4)
Figure 6. 6.5 Gbps Output Eye, No Channel (TP2 from Figure 4)
Rev. 0 | Page 9 of 36
08262-006
AD8155
DATA OUT 2 50 CABLES 2 FR4 TEST BACKPLANE 50 CABLES 2 2 INPUT OUTPUT 2 PIN PIN 50 CABLES 2 50 TP3
200mV/DIV
PATTERN GENERATOR
DIFFERENTIAL STRIPLINE TRACES TP1 8mils WIDE, 8mils SPACE, 8mils DIELECTRIC HEIGHT TRACE LENGTHS = 20 INCHES, 40 INCHES
AD8155
TP2 AC-COUPLED EVALUATION BOARD
HIGH SPEED SAMPLING OSCILLOSCOPE
25ps/DIV REFERENCE EYE DIAGRAM AT TP1
Figure 7. Input Equalization Test Circuit
200mV/DIV
200mV/DIV
25ps/DIV
08262-008
25ps/DIV
Figure 8. 6.5 Gbps Input Eye, 20 Inch FR4 Input Channel (TP2 from Figure 7)
Figure 10. 6.5 Gbps Output Eye, 20 Inch FR4 Input Channel (TP3 from Figure 7)
200mV/DIV
200mV/DIV
25ps/DIV
08262-009
25ps/DIV
Figure 9. 6.5 Gbps Input Eye, 40 Inch FR4 Input Channel (TP2 from Figure 7)
Figure 11. 6.5 Gbps Output Eye, 40 Inch FR4 Input Channel (TP3 from Figure 7)
Rev. 0 | Page 10 of 36
08262-011
08262-010
08262-007
AD8155
DATA OUT 2 50 CABLES 2 50 CABLES 2 INPUT OUTPUT 2 PIN PIN FR4 TEST BACKPLANE 2 50 CABLES 2 50 TP3
200mV/DIV
PATTERN GENERATOR
AD8155
TP1 AC-COUPLED EVALUATION BOARD
DIFFERENTIAL STRIPLINE TRACES TP2 8mils WIDE, 8mils SPACE, 8mils DIELECTRIC HEIGHT TRACE LENGTHS = 20 INCHES, 30 INCHES
HIGH SPEED SAMPLING OSCILLOSCOPE
25ps/DIV REFERENCE EYE DIAGRAM AT TP1
Figure 12. Output Preemphasis Test Circuit
200mV/DIV
08262-013
200mV/DIV
25ps/DIV
25ps/DIV
Figure 13. 6.5 Gbps Output Eye, 20 Inch FR4 Input Channel, PE = 0 (TP3 from Figure 12)
Figure 15. 6.5 Gbps Output Eye, 20 Inch FR4 Input Channel, PE = Best Setting, Default Output Level (TP3 from Figure 12)
200mV/DIV
100mV/DIV
25ps/DIV
08262-014
25ps/DIV
Figure 14. 6.5 Gbps Output Eye, 30 Inch FR4 Input Channel, PE = 0 (TP3 from Figure 12)
Figure 16. 6.5 Gbps Output Eye, 30 Inch FR4 Input Channel, PE = Best Setting, 200 mV Output Level (TP3 from Figure 12)
Rev. 0 | Page 11 of 36
08262-016
08262-015
08262-012
AD8155
100 80 70
DETERMINISTIC JITTER (ps)
DETERMINISTIC JITTER (ps)
80
60 50 40 30 20 10 VCC = 1.8V VCC = 3.3V
60
40
20
0
2
4 DATA RATE (GHz)
6
8
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
INPUT COMMON-MODE (V)
Figure 17. Deterministic Jitter vs. Data Rate
Figure 20. Deterministic Jitter vs. Input Common Mode
100
100
DETERMINISTIC JITTER (ps)
60
DETERMINISTIC JITTER (ps)
80
80
60
40
40
20
20
08262-018
0 0 0.5 1.0 1.5 2.0 2.5 DIFFERENTIAL INPUT SWING (V p-p)
1.5
2.0
2.5 VCC (V)
3.0
3.5
4.0
Figure 18. Deterministic Jitter vs. Input Swing
100
Figure 21. Deterministic Jitter vs. VCC
100 90 (VCC = 3.3V) MIN OUTPUT SWING
DETERMINISTIC JITTER (ps)
DETERMINISTIC JITTER (ps)
80
80 70 60 50 40 30 20 10 (VCC = 1.8V) MIN OUTPUT SWING
60
(VCC = 3.3V) DEFAULT OUTPUT SWING
40
20
(VCC = 1.8V) DEFAULT OUTPUT SWING 1.5 2.0 2.5 3.0 3.5 4.0
08262-022
-40
-20
0
20
40
60
80
100
TEMPERATURE (C)
08262-019
0 -60
0 1.0
VTTO VOLTAGE (V)
Figure 19. Deterministic Jitter vs. Temperature
Figure 22. Deterministic Jitter vs. Output Termination Voltage (VTTO)
Rev. 0 | Page 12 of 36
08262-021
0 1.0
08262-020
08262-017
0
0
AD8155
100 90 1.0
DETERMINISTIC JITTER (ps)
80 70 60 50 40 30 20 10 0 0.5 (VCC = 1.8V) 200mV OUTPUT VOLTAGE 1.0 1.5 2.0 (VCC = 3.3V) 200mV OUTPUT VOLTAGE 2.5 3.0 3.5
08262-023
0.9 (VCC = 3.3V) DEFAULT OUTPUT SWING AMPLITUDE (V p-p DIFF)
0.8
0.7
(VCC = 1.8V) DEFAULT OUTPUT SWING
0.6
0.5
1.9
2.4
2.9
3.4
VOCM VOLTAGE (V)
CORE VOLTAGE (V)
Figure 23. Deterministic Jitter vs. Output Common-Mode Voltage (VOCM)
Figure 26. Output Amplitude (Default Setting) vs. VCC
1.0
0.9 AMPLITUDE (V p-p DIFF)
0.8
0.7
0.6
Rj
0.5
200k#/div 2.00ps/div 11.28839M#
CIS 320kS
20.0ns/div Stop 630fs/S
08262-044
0
1
2
3
4
5
6
7
RATE (Gbps)
Figure 24. Random Jitter Histogram
100 1000 950 90 900 850 DELAY (ps)
Figure 27. Output Amplitude vs. Rate
tR/tF (ps)
80
800 750 700 650
70
60
600 550
08262-025
-40
-20
0
20
40
60
80
100
2.1
2.6
3.1
3.6
TEMPERATURE (C)
CORE SUPPLY VOLTAGE (V)
Figure 25. tR/tF vs. Temperature
Figure 28. Propagation Delay vs. Core Supply
Rev. 0 | Page 13 of 36
08262-028
50 -60
500 1.6
08262-027
RjHist
Timebase
0.0ns
Trigger Prescaler
0.4
08262-026
0.4 1.4
AD8155
1000 950 DETERMINISTIC JITTER (ps) 900 850
90 80 70 60 50 40 30 20 10
08262-029
DELAY (ps)
800 750 700 650 600 550 500 -60 -40 -20 0 20 40 60 80 100
0
1
2
TEMPERATURE (C)
3 4 PE SETTING
5
6
7
Figure 29. Propagation Delay vs. Temperature
0" 10" 20" 30" 40" RANDOM JITTER (ps)
Figure 32. Deterministic Jitter vs. PE Setting
140 120 100 80 60 40 20 0
10 9 8 7 6 5 4 3 2
DETERMINISTIC JITTER (ps)
0" DEFAULT OUTPUT SWING 10" DEFAULT OUTPUT SWING 20" DEFAULT OUTPUT SWING 30" DEFAULT OUTPUT SWING 30" MINIMUM OUTPUT SWING
EQ SETTING
0
1
2
3
4 5 PE SETTING
6
7
8
Figure 30. Deterministic Jitter vs. EQ Setting
10 9 8
RANDOM JITTER (ps)
Figure 33. Random Jitter vs. PE Setting
0 -2 -4 -6
LOSS (dB)
7 6 5 4 3 2 1
0" 10" 20" 30" 40"
-8 -10 -12 -14 -16 -18 6" 10" 20" 30" 40" 1M 10M 100M FREQUENCY (Hz) 1G
08262-031
0
1
2
3
4 5 6 EQ SETTING
7
8
9
10
Figure 31. Random Jitter vs. EQ Setting vs. Trace
Figure 34. S21 Test Traces
Rev. 0 | Page 14 of 36
08262-034
0
-20 100k
08262-033
NO DUT
0
1
2
3
4
5
6
7
8
9
08262-030
1 0
08262-032
0
0" DEFAULT OUTPUT SWING 10" DEFAULT OUTPUT SWING 20" DEFAULT OUTPUT SWING 30" DEFAULT OUTPUT SWING 30" 200mV OUTPUT LEVEL
AD8155 THEORY OF OPERATION
The AD8155 is a buffered, asynchronous, three-port transceiver that allows 2:1 multiplexing and 1:2 demultiplexing among its ports. The 1:2 demux path supports bicast operation, allowing the AD8155 to operate as a port replicator as well as a redundancy switch. The AD8155 offers loopback on each lane, allowing the part to be configured as a six-lane equalizer or redriver with FFE.
MUX RXA RXB
features, together with programmable transmitter output levels, allow for a wide range of dc- and ac-coupled I/O configurations. The AD8155 supports several control and configuration modes, shown in Table 5. The pin control mode offers access to a subset of the total feature list but allows for a much simplified control scheme. Table 6 compares the features in all control modes. The primary advantage of using the serial control interface is that it allows finer resolution in setting receive equalization, transmitter preemphasis, loss-of-signal (LOS) behavior, and output levels. By default, the AD8155 starts in the pin control mode. Strobing the RESET pin sets all on-chip registers to their default values and uses pins to configure switch connectivity, PE, and EQ levels. In mixed mode, switch connectivity is still controlled through the SEL[1:0], LB_[A:C], and BICAST pins. The user can override PE and EQ settings in mixed mode. In serial mode, all functions are accessed through registers and the control pin inputs are ignored, except RESET . The AD8155 register set is controlled through a 2-wire I2C interface. The AD8155 acts only as an I2C slave device. The 7-bit slave address for the AD8155 I2C interface contains the static value b1010 for the upper four bits. The lower three bits are controlled by the input pins, I2C_A[2:0].
TXC
DEMUX TXA TXB
RXC
08262-035
Figure 35. Mux/Demux Paths, Port A to Port C
The part offers extensively programmable transmit output levels and preemphasis settings as well as squelch or full disable. The receivers integrate a programmable, multizero transfer function for aggressive equalization and a programmable loss-of-signal feature. The AD8155 provides a balanced, high speed switch core that maintains low lane-to-lane skew while preserving edge rates. The I/O on-chip termination resistors are tied to user-settable supplies for increased flexibility. The AD8155 supports a wide primary supply range; VCC can be set from 1.8 V to 3.3 V. These Table 5. Control Interface Mode Register
Address 0x0F Default 0x00 Register Name Control interface mode Bit 7:2 1:0 Bit Name Reserved Mode[1:0]
Functionality Description Set to 0. 00: toggle pin control. Asynchronous control through toggle pins only. 10: mixed control. Switch configuration via toggle pins, register-based control through the I2C serial interface. 11: serial control. Register-based control through the I2C serial interface.
Rev. 0 | Page 15 of 36
AD8155
Table 6. Features Available Through Toggle Pin or Serial Control
Feature Switch Features BICAST A/B Lane Select Loopback Rx Features EQ Levels N/P Swap Squelch Tx Features Programmable Output Levels PE Levels
1
Pin Control One pin Two pins Three pins Two settings Not available Enabled 400 mV diff fixed1 Two settings
Serial Control One bit Two bits Three bits 10 settings Available Three bits 200 mV diff/300 mV diff/400 mV diff/600 mV diff >7 settings
400 mV diff indicates a 400 mV amplitude signal measured between two differential nodes. The voltage swing at differential I/O pins is described in this data sheet both in terms of the differentially measured voltage range (400 mV diff, for example) and in terms of peak-to-peak differential swing, denoted as mV p-p diff. An output level setting of 400 mV diff delivers a differential peak-to-peak output voltage of 800 mV p-p diff.
THE SWITCH (MUX/DEMUX/UNICAST/BICAST/LOOPBACK)
The mux and demux functions of the AD8155 can be controlled either with the toggle pins or through the register map. The multiplexer path switches received data from Input Port A or Input Port B to Output Port C. The SEL[1:0] pins allow switching lanes independently. The demultiplexer path switches received data from Input Port C to Output Port A, Output Port B, or (if bicast mode is enabled) to both Output Port A and Output Port B. Table 7. Port Selection and Configuration with All Loopbacks Disabled
BICAST 0 0 1 1 SELx 0 1 0 1 Output Port A Ix_C[1:0] Idle Ix_C[1:0] Ix_C[1:0] Output Port B Idle Ix_C[1:0] Ix_C[1:0] Ix_C[1:0] Output Port C Ix_A[1:0] Ix_B[1:0] Ix_A[1:0] Ix_B[1:0]
When the device is in unicast mode, the output lanes on either Port A or Port B are in an idle state. In the idle state, the transmitter output current is set to 0, and the P and N sides of the lane are pulled up to the output termination voltage through the on-chip termination resistors. To save power, the unused receiver automatically disables. The AD8155 supports port-level loopback, illustrated in Figure 36. The loopback control pins override the lane select (SEL[1:0]) and bicast control (BICAST) pin settings at the port level. In serial control mode, Bits [6:4] of Register 0x01 control loopback and are equivalent to asserting Pin LB_A, Pin LB_B, and Pin LB_C. Table 8 summarizes the different loopback configurations. The loopback feature is useful for system debug, self-test, and initialization, allowing system ASICs to compare Tx and Rx data sent over a single bidirectional link. Loopback can also be used to configure the device as a two- to six-lane receive equalizer or backplane redriver.
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AD8155
X4 Ix_C[1:0] X4 1:2 DEMUX X4 Ox_B[1:0] PORT A LOOPBACK PORT C LOOPBACK PORT B LOOPBACK X4 X4 2:1 MUX X4 Ix_B[1:0]
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Ox_A[1:0]
Ix_A[1:0]
Ox_C[1:0]
Figure 36. Port-Level Loopback
Table 8. Switch Connectivity vs. Loopback, BICAST, and Port Select Settings
LB_A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LB_B 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 LB_C 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BICAST 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SEL[1:0] 00 11 00 1 00 11 00 11 00 11 00 11 00 11 00 11 00 11 00 11 00 11 00 11 00 11 00 11 00 11 00 11 Output Port A Ix_C[1:0] Idle Ix_C[1:0] Ix_C[1:0] Ix_C[1:0] Idle Ix_C[1:0] Ix_C[1:0] Ix_C[1:0] Idle Ix_C[1:0] Ix_C[1:0] Ix_C[1:0] Idle Ix_C[1:0] Ix_C[1:0] Ix_A[1:0] Ix_A[1:0] Ix_A[1:0] Ix_A[1:0] Ix_A[1:0] Ix_A[1:0] Ix_A[1:0] Ix_A[1:0] Ix_A[1:0] Ix_A[1:0] Ix_A[1:0] Ix_A[1:0] Ix_A[1:0] Ix_A[1:0] Ix_A[1:0] Ix_A[1:0] Output Port B Idle Ix_C[1:0] Ix_C[1:0] Ix_C[1:0] Idle Ix_C[1:0] Ix_C[1:0] Ix_C[1:0] Ix_B[1:0] Ix_B[1:0] Ix_B[1:0] Ix_B[1:0] Ix_B[1:0] Ix_B[1:0] Ix_B[1:0] Ix_B[1:0] Idle Ix_C[1:0] Ix_C[1:0] Ix_C[1:0] Idle Ix_C[1:0] Ix_C[1:0] Ix_C[1:0] Ix_B[1:0] Ix_B[1:0] Ix_B[1:0] Ix_B[1:0] Ix_B[1:0] Ix_B[1:0] Ix_B[1:0] Ix_B[1:0] Output Port C Ix_A[1:0] Ix_B[1:0] Ix_A[1:0] Ix_B[1:0] Ix_C[1:0] Ix_C[1:0] Ix_C[1:0] Ix_C[1:0] Ix_A[1:0] Ix_B[1:0] Ix_A[1:0] Ix_B[1:0] Ix_C[1:0] Ix_C[1:0] Ix_C[1:0] Ix_C[1:0] Ix_A[1:0] Ix_B[1:0] Ix_A[1:0] Ix_B[1:0] Ix_C[1:0] Ix_C[1:0] Ix_C[1:0] Ix_C[1:0] Ix_A[1:0] Ix_B[1:0] Ix_A[1:0] Ix_B[1:0] Ix_C[1:0] Ix_C[1:0] Ix_C[1:0] Ix_C[1:0]
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AD8155
RECEIVERS
The AD8155 receivers incorporate 50 on-chip termination, ESD protection, and a multizero equalization function capable of delivering up to 18 dB of boost at 4.25 GHz. The AD8155 can compensate signal degradation at 6.5 Gbps from over 40 inches of FR4 backplane trace. The receive path also incorporates a loss-of-signal (LOS) function that squelches the associated transmitter when the midband differential voltage falls below a specified threshold value. Finally, the receivers implement a signswapping option (P/N swap), which allows the user to invert the sign of the input signal path and eliminates the need for boardlevel crossovers in the receive channels.
Equalizer Settings
Every input lane offers a low power, asynchronous, programmable receive equalizer for NRZ data up to 6.5 Gbps. The pin control interface allows two levels of receive equalization. Register-based control allows the user 10 equalizer settings. Register and pin control boost settings are listed in Table 10. Equalization capability and resulting jitter performance are illustrated in Figure 30, Figure 31, and Figure 34. Figure 34 shows the loss characteristic of various reference channels, and Figure 30 and Figure 31 show resulting DJ and RJ performance vs. equalizer setting against these channels. The two LSBs of Register 0x41, Register 0x81, and Register 0xC1 allow programming of all the equalizers in a port simultaneously (see Table 13). The 0x42, 0x82, and 0xC2 registers allow per-lane programming of the equalizers (see Table 22). Be aware that writing to the port-level equalizer registers updates and overwrites per-lane settings. Table 10. Equalizer Settings
Equalization Boost (dB) 0 2 4 6 8 10 12 14 16 18 EQ Register Setting 0 1 2 3 4 5 6 7 8 9 EQ Pin 0 N/A N/A N/A 1 N/A N/A N/A N/A N/A
Input Structure and Allowed Input Levels
The AD8155 tolerates an input common-mode range (measured with zero differential input) of VEE + 0.6 V < VICM < VCC + 0.3 V Typical supply configurations include, but are not limited to, those listed in Table 9. Table 9. Typical Input Supply Configurations
Configuration Low VTTI, AC-Coupled Input Single 1.8 V Supply 3.3 V Core Single 3.3 V Supply DVCC 3.3 V - 1.8 V 3.3 V - 1.8 V 3.3 V 3.3 V VCC 1.8 V 1.8 V 3.3 V 3.3 V VTTI 1.6 V 1.8 V 1.8 V 3.3 V
When dc-coupling with LVDS, CML, or ECL signals, it can be advantageous to operate with split or negative supplies (see the Applications Information section). In these applications, it is necessary to observe the maximum voltage ratings between VCC and VEE and to select supply voltages for VTTO and VTTI in the range of VCC to VEE to avoid activating the ESD protection devices.
VCC VTTI RP 52 IP_xx IN_xx RN R1 52 750 RLN RL Q1 R3 1k Q2 RLP RL
VCC VTTI
ESD
ON-CHIP TERMINATION
VTHRESH LOSS OF SIGNAL DETECT
IP_xx IN_xx
RP RTERM
RN RTERM
SIG
EQ OUT EQUALIZER
VEE I1
VEE
Figure 37. Simplified Receiver Input Structure
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Figure 38. Functional Diagram of the AD8155 Receiver
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R2 750
AD8155
Lane Disables
By default, the receivers and transmitters enable in an on-demand fashion according to the state of the SEL[1:0], LB_[A:C], and BICAST pins or to the state of the equivalent registers in serial control mode. Register 0x40, Register 0x80, and Register 0xC0 implement per-lane disables for the receivers, and Register 0x48, Register 0x88, and Register 0xC8 implement per-lane transmitter disables. These disables override the default settings. Each bit in the register is named for the lane and function it disables. For example, RXDIS B0 disables the receiver on Lane 0 of Port B whereas TXDIS C1 disables the Lane 1 transmitter of Port C (see Table 11).
Lane Inversion: P/N Swap
The receiver P/N swap function is a convenience intended to allow the user to implement the equivalent of a board-level routing crossover in a much smaller area while eliminating vias (impedance discontinuities) that compromise the high frequency integrity of the signal path. Using this feature to correct an inversion downstream of the receiver may require the user to be aware of the sign of the data when switching connectivity (the mux/demux path). The feature is available on a per-lane setting through Register 0x44, Register 0x84, and Register 0xC4. Setting the bit true flips the sign sense of the P and N inputs for the associated lane. The default setting is 0 (no inversion).
Table 11. Per-Lane Disables
Address 0x40 0x80 0xC0 Port Port A Port B Port C Default 0x00 0x00 0x00 Register Name RX[A/B/C] disable Bit 7:4 3:2 1 0 0x48 0x88 0xC8 Port A Port B Port C 0x00 0x00 0x00 TX[A/B/C] disable 7:4 3:2 1 0 Bit Name Reserved Reserved RXDIS [A/B/C]1 RXDIS [A/B/C]0 Reserved Reserved TXDIS [A/B/C]1 TXDIS [A/B/C]0 Functionality Description Set to 0 0: RX Port [A/B/C], Lane 1, enabled 1: RX Port [A/B/C], Lane 1, disabled 0: RX Port [A/B/C], Lane 0, enabled 1: RX Port [A/B/C], Lane 0, disabled Set to 0 0: TX Port [A/B/C], Lane 1, enabled 1: TX Port [A/B/C], Lane 1, disabled 0: TX Port [A/B/C], Lane 0, enabled 1: TX Port [A/B/C], Lane 0, disabled
Table 12. Lane Inversion
Address 0x44 0x84 0xC4 Port Port A Port B Port C Default 0x00 0x00 0x00 Register Name RX[A/B/C] P/N swap Bit 7:2 1 0 Bit Name Reserved PN[A/B/C]1 PN[A/B/C]0 Functionality Description Set to 0 0: Lane 1, noninverted 1: Lane 1, inverted 0: Lane 0, noninverted 1: Lane 0, inverted
Table 13. Port-Level EQ Setting
Address 0x41 0x81 0xC1 Port Port A Port B Port C Default 0x00 0x00 0x00 Register Name RX[A/B/C] EQ setting Bit 7:4 3:0 Bit Name Reserved [A/B/C]EQ[3:0] Functionality Description Set to 0
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AD8155
LOSS OF SIGNAL (LOS)
The serial control interface allows access to the AD8155 loss of signal features (LOS is not available in pin control mode). Each receiver includes a low power, loss-of-signal detector. The lossof-signal circuit monitors the received data stream and generates a system interrupt when the received signal power falls below a fixed threshold. The threshold is 50 mV p-p diff, referred to the input pins. The LOS circuit monitors the equalized receive waveform and integrates the rms power of the equalized waveform over a selectable interval of either 2 ns or 10 ns. The detectors are enabled on a per-port basis with Bit 0 of the RXA/B/C LOS control registers (0x51, 0x91, 0xD1). By default, when the receiver detects an LOS event, it squelches its associated transmitter, lowering the output current to submicroamps. This prevents the high gain, wide bandwidth signal path from turning low level system noise on an undriven input pair into a source of hostile crosstalk at the transmitter. The squelch feature can be disabled with Bit 3 of the global squelch control register (0x04). Table 14. Global Loss-of-Signal Squelch Control Register
Address 0x04 Default 0x0F Register Name Global Squelch Ctrl Bit 7:4 3 2:0 Bit Name Reserved GSQLCH_ENB Reserved Functionality Description Set to 0 0: LOS auto squelch disabled 1: LOS auto squelch enabled Set to 1
The LOS_INT pin evaluates a logical OR of all LOS status register bits for all enabled receivers (LOS status registers are located at 0x45, 0x85, and 0xC5). The upper two bits in the RXA, RXB, and RXC LOS status registers are sticky, whereas the two LSBs are continuously updated to indicate the instantaneous status of LOS for an enabled receiver. The sticky bits are cleared by writing 0 to the RXA, RXB, and RXC LOS status registers. The LOS_INT pin remains high after an LOS event until all sticky registers are cleared and all active status registers (for example, Bits[1:0]) read 0. The LOS_INT pin requires that an initialization sequence be enabled (see the Applications Information section). The LOS_INT pin can be used to generate an interrupt for the system control software. In a standard implementation, when LOS_INT goes high, the system software registers the interrupt and polls the RXA, RXB, and RXC LOS status registers to determine which input lost signal and whether the signal has been restored.
Table 15. Port-Level Loss-of-Signal Control Registers
Address 0x51 0x91 0xD1 Port Port A Port B Port C Default 0x05 0x05 0x05 Register Name RX[A/B/C] LOS control Bit 7:3 2 1 0 Bit Name Reserved LOS_FILT Reserved LOS_ENB Functionality Description Set to 0 0: LOS filter time constant = 2 ns 1: LOS filter time constant = 10 ns Set to 0 0: LOS disabled 1: LOS enabled
Table 16. Port-Level Loss-of-Signal Status Registers
Address 0x45 0x85 0xC5 Port Port A Port B Port C Default Read only Write 0 to clear Register Name RX[A/B/C] LOS status Bit 7:6 5:4 Bit Name Reserved LOS[A/B/C][1:0] sticky Functionality Description 00: LOS event has not occurred. 01: LOS event has occurred on Lane 0. 10: LOS event has occurred on Lane 1. 11: LOS event has occurred on both lanes. Read only; write 0 to clear. 00: active signals on both lanes. 01: inactive signal on Lane 0. 10: inactive signal on Lane 1. 11: inactive signals on both lanes. Read only.
3:2 1:0
Reserved LOS[A/B/C][1:0] active
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AD8155
TRANSMITTERS
The AD8155 transmitter offers programmable preemphasis, programmable output levels, output disable, and transmit squelch. The SEL4G pin lets the user lower the transmitter frequency of maximum boost from 3.25 GHz to 2.0 GHz, allowing the AD8155 to offer exceptional transmit channel compensation for legacy applications (4.5 Gbps and slower).
ON-CHIP TERMINATION V3 VC RP RTERM V2 VP V1 VN Q1 Q2 IT IDC + IPE VEE RN RTERM ESD VCC VTTO
Preemphasis can be programmed per port or per lane. Register 0x49, Register 0x89, and Register 0xC9 set all outputs in a port at once. Registers 0x4A, 0x8A, and 0xCA allow setting PE on a per-lane basis. The following equation sets preemphasis boost:
Gain[dB] = 20 x log10 (1 + VSW - PE - VSW - DC VSW - DC )
(1)
Table 18. Setting Transmitter Preemphasis
Output Level (mV diff) 200 200 200 200 200 200 200
300 300 300 300 300 300 300 400 400 400 400 400 400 400 600 600
OP_xx ON_xx
Figure 39. Simplified Transmitter Structure
Output Level Programming and Output Structure
The output level of the transmitter of each lane is independently programmable. In pin control mode, a default output amplitude of 800 mV p-p diff (400 mV diff) is delivered (see Table 17). Register-based control allows the user to set the transmitter output levels on a per-port or per-lane basis to four predefined levels. Port-level programming overwrites lane-level configuration. The ALEV, BLEV, and CLEV bits in Register 0x49, Register 0x89, and Register 0xC9, respectively, are used to set the output levels for all transmitters. The A[1:0]OLEV[1:0], B[1:0]OLEV[1:0], and C[1:0]OLEV[1:0] bits in Register 0x4C, Register 0x8C, and Register 0xCC allow per-lane settings (see Table 22). Table 17. Predefined Output Levels
[A/B/C][1:0]OLEV[1] 0 0 1 1 [A/B/C][1:0]OLEV[0] 0 1 0 1 Output Level 200 mV diff 300 mV diff 400 mV diff (default) 600 mV diff
600 600 600 600 600
Pin PE_[A/B/C] N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 0 N/A N/A N/A 1 N/A N/A N/A N/A N/A N/A N/A N/A N/A
Bit PE[2:0] 000 001 010 011 100 101 110 000 001 010 011 100 101 110 000 001 010 011 100 101 110 000 001 010 011 100 101 110
PE Boost (%) 0 50 100 150 200 250 300 0 33 67 100 133 167 200 0 25 50 75 100 125 150 0 17 33 50 67 83 100
PE Boost (dB) 0 3.52 6.02 7.96 9.54 10.88 12.04 0 2.5 4.44 6.02 7.36 8.52 9.54 0 1.94 3.52 4.86 6.02 7.04 7.96 0 1.34 2.5 3.52 4.44 5.26 6.02
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Squelch and Disable
Each transmitter is equipped with disable and squelch controls. Disable is a full power-down state: the transmitter current is reduced to zero and the output pins pull up to VTTO, but there is a delay of approximately 1 s associated with reenabling the transmitter. Squelch keeps the output current enabled such that both output pins are at the output common-mode voltage. The transmitter recovers from squelch in less than 64 ns.
Note that the choice of output level influences the output common-mode level. A 600 mV diff output level with a full PE range requires a supply and output termination voltage of 2.5 V or higher (VTTO, VCC 2.5 V).
Preemphasis
Transmitter preemphasis levels can be set by pin control or through the control registers. Pin control allows two settings of PE, 0 dB and 6 dB. The control registers provide seven levels of PE. Note that a larger range of boost settings is available for lower output levels. Note that toggle pin control of PE is limited to the 400 mV diff output level settings. Table 18 lists the available preemphasis settings for each output level.
Speed Select
The SEL4G pin lets the user lower the transmitter frequency of maximum boost from 3.25 GHz to 2.0 GHz, allowing the AD8155 to offer exceptional transmit channel compensation for legacy applications (4.5 Gbps and slower). SEL4G = 1 lowers the
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AD8155
frequency of maximum boost without sacrificing the amount of boost delivered. The final section is the outputs section. For an individual output, the programmed output current flows through two separate paths. One is the on-chip termination resistor, and the other is the transmission line and the destination termination resistor. The nominal parallel impedance of these two paths is 25 . The sum of these two currents flows through the switches and the current source of the AD8155 output circuit and out through VEE. The power dissipated in the transmission line and the destination resistor is not dissipated in the AD8155 but must be supplied from the power supply and is a factor in overall system power. The current in the on-chip termination resistors and the output current source dissipate power in the AD8155 itself.
AD8155 POWER CONSUMPTION
There are several sections of the AD8155 that draw varying power depending on the supply voltages, the type of I/O coupling used, and the status of the AD8155 operation. Figure 40 shows a block diagram of these sections. An initialization sequence is required to enable the AD8155 in a low power mode (see the Applications Information section). The first section consists of the input termination resistors. The power dissipated in the termination resistors is due to the input differential swing and any common-mode current resulting from dc-coupling the input. In the next section (the receiver section), each input is powered only when it is selected, and the disable bits are set to 0. If a receiver is not selected, it is powered down. Thus, the total number of active inputs affects the total power consumption. Furthermore, the loss-of-signal detection circuits can be disabled independent of the receiver for even greater power savings. The core of the device performs the multiplexer and demultiplexer switching functions. It draws a fixed quiescent current of 2 mA whenever the AD8155 is powered from VCC to VEE. The switch draws an additional 4 x 4.6 mA in normal mux/demux operation and an additional 6 x 4.6 mA with all ports in loopback or with bicast selected. The switch core can be disabled to save power. An output predriver section draws a current, IPRED, that is related to the programmed output current, ITTO. The predriver current always flows from VCC to VEE. It is treated separately from the output current, which flows from VTTO and may not be the same voltage as VCC.
VTTI VCC
Outputs
The output current is set by a combination of output level and preemphasis settings (see Table 19). For the two logic switch states, this current flows through an on-chip termination resistor and a parallel path to the destination device and its termination resistor. The power in this parallel path is not dissipated by the AD8155. With preemphasis enabled, some current always flows in both the P and N termination resistors. This preemphasis current gives rise to an output commonmode shift, which varies with ac-coupling or dc-coupling and which is calculated for both cases in Table 19. Perhaps the most direct method for calculating power dissipated in the output is to calculate the power that would be dissipated if all of ITOT were to flow on-die from VTTO to VEE and to subtract from this the power dissipated off die in the destination device termination resistors and the channel. For this purpose, the destination device and channel can be modeled as 50 load resistors, RL, in parallel with the AD8155 termination resistors.
.
DVCC VTTO OUTPUT TERMINATIONS IOUT P= x 50 2 50 VTT
50
50
50
IN_xx INPUT TERMINATION AC-COUPLING CAPS (OPTIONAL) P= (VIN_DIFF_RMS )2 100 LOSS OF SIGNAL RECEIVER SWITCH
OUTPUT PREDRIVERS
DIGITAL CONTROL
IP_xx
EQUALIZER
REFERENCES/ BIAS CIRCUITRY
OPTIONAL COUPLING CAPACITORS IOUT P = (VOL) (IOUT) VOL = VTTO - (IOUT x 25)
VEE
Figure 40. AD8155 Power Distribution Block Diagram
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AD8155
Power Saving Considerations
Whereas the AD8155 power consumption is very low compared to similar devices, careful control of its operating conditions can yield further power savings. Significant power reduction can be realized by operating the part at a lower voltage. Compared to 3.3 V operation, a supply voltage of 1.8 V can result in power savings of ~45%. There is no performance penalty when operting at lower voltage. An initialization sequence is required to enable the AD8155 in a low power mode (see the Applications Information section). A second measure is to disable transmitters when they are not being used. This can be done on a static basis if the output is not used or on a dynamic basis if the output does not have a constant stream of traffic. On transmit disable (Register 0x48, Register 0x88, Register 0xC8), both the predriver and output switch currents are disabled. The LOS-activated squelch disables only the output switch current, ITOT. Superior power saving is achieved by using the TX and RX disable registers to turn off an unused lane as opposed to relying on the AD8155 transmit squelch feature. Because the majority of the power dissipated is in the output stage, some of its flexibility can be used to lower the power consumption. First, the output current and output preemphasis settings can be programmed to the smallest amount required to maintain BER performance. If an output circuit always has a short length and the receiver has good sensitivity, then a lower output current can be used. It is also possible to lower the voltage on VTTO to lower the power dissipation. The amount that VTTO can be lowered is dependent on the lowest of all the output's VOL and VCC. This is determined by the output that is operating at the highest programmed output current. Table 1 and Table 19 list minimum output levels.
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AD8155 I2C CONTROL INTERFACE
SERIAL INTERFACE GENERAL FUNCTIONALITY
The AD8155 register set is controlled through a 2-wire I2C interface. The AD8155 acts only as an I2C slave device. The 7-bit slave address for the AD8155 I2C interface contains the static value b1010 for the upper four bits. The lower three bits are controlled by the input pins, I2C_A[2:0]. Therefore, the I2C bus in the system must include an I2C master to configure the AD8155 and other I2C devices that may be on the bus. Data transfers are controlled through the use of the two I2C wires: the SCL input clock pin and the SDA bidirectional data pin. The AD8155 I2C interface can be run in the standard (64 kHz) and fast (400 kHz) modes. The SDA line changes value only when the SCL pin is low, with two exceptions. To indicate the beginning or continuation of a transfer, the SDA pin is driven low while the SCL pin is high, and to indicate the end of a transfer, the SDA line is driven high while the SCL line is high. Therefore, it is important to control the SCL clock to toggle only when the SDA line is stable unless indicating a start, repeated start, or stop condition. 6. 7. 8. 9. Wait for the AD8155 to acknowledge the request. Send the data (eight bits) to be written to the register whose address was set in Step 5. This transfer should be MSB first. Wait for the AD8155 to acknowledge the request. Do one or more of the following: a. Send a stop condition (while holding the SCL line high, pull the SDA line high) and release control of the bus. b. Send a repeated start condition (while holding the SCL line high, pull the SDA line low) and continue with Step 2 in this procedure to perform another write. c. Send a repeated start condition (while holding the SCL line high, pull the SDA line low) and continue with Step 2 of the read procedure (in the I2C Interface Data Transfers: Data Read section) to perform a read from another address. d. Send a repeated start condition (while holding the SCL line high, pull the SDA line low) and continue with Step 8 of the read procedure (in the I2C Interface Data Transfers: Data Read section) to perform a read from the same address set in Step 5.
I2C INTERFACE DATA TRANSFERS: DATA WRITE
To write data to the AD8155 register set, a microcontroller or any other I2C master must send the appropriate control signals to the AD8155 slave device. The following steps must be taken, where the signals are controlled by the I2C master, unless otherwise specified. For a diagram of the procedure, see Figure 41. 1. 2. Send a start condition (while holding the SCL line high, pull the SDA line low). Send the AD8155 part address (seven bits) whose upper four bits are the static value b1010 and whose lower three bits are controlled by the I2C_A[2:0] input pins. This transfer should be MSB first. Send the write indicator bit (0). Wait for the AD8155 to acknowledge the request. Send the register address (eight bits) to which data is to be written. This transfer should be MSB first.
SCL
In Figure 41, the AD8155 write process is shown. The SCL signal is shown along with a general write operation and a specific example. In this example, the value 0x92 is written to Address 0x6D of an AD8155 device with a part address of 0x53. The part address is seven bits wide and is composed of the AD8155 static upper four bits (b1010) and the pin-programmable lower three bits (I2C_A[2:0]). The address pins are set to b011. In Figure 41, the corresponding step number is visible in the circle under the waveform. The SCL line is driven by the I2C master and never by the AD8155 slave. As for the SDA line, the data in the shaded polygons is driven by the AD8155, whereas the data in the nonshaded polygons is driven by the I2C master. The end phase case shown is that of Step 9a. It is important to note that the SDA line changes only when the SCL line is low, except for the case of sending a start, stop, or repeated start condition (Step 1 and Step 9 in this case).
3. 4. 5.
SDA
START
b1010
ADDR [2:0]
R/W ACK
REGISTER ADDR
ACK
DATA
ACK
STOP
SDA 1 2 2 3 4
2
5
6
7
8
9a
Figure 41. I C Write Diagram
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AD8155
I2C INTERFACE DATA TRANSFERS: DATA READ
To read data from the AD8155 register set, a microcontroller or any other I2C master must send the appropriate control signals to the AD8155 slave device. The following steps must be taken, where the signals are controlled by the I2C master, unless otherwise specified. For a diagram of the procedure, see Figure 42. 1. 2. Send a start condition (while holding the SCL line high, pull the SDA line low). Send the AD8155 part address (seven bits) whose upper four bits are the static value b1010 and whose lower three bits are controlled by the I2C_A[2:0] input pins. This transfer should be MSB first. Send the write indicator bit (0). Wait for the AD8155 to acknowledge the request. Send the register address (eight bits) from which data is to be read. This transfer should be MSB first. The register address is kept in memory in the AD8155 until the part is reset or the register address is written over with the same procedure (Step 1 to Step 6). Wait for the AD8155 to acknowledge the request. Send a repeated start condition (while holding the SCL line high, pull the SDA line low). Send the AD8155 part address (seven bits) whose upper four bits are the static value b1010 and whose lower three bits are controlled by the I2C_A[2:0] input pins. This transfer should be MSB first. Send the read indicator bit (1). Wait for the AD8155 to acknowledge the request. The AD8155 then serially transfers the data (eight bits) held in the register indicated by the address set in Step 5. Acknowledge the data. Do one or more of the following: a. Send a stop condition (while holding the SCL line high, pull the SDA line high) and release control of the bus.
SCL
b.
c.
d.
Send a repeated start condition (while holding the SCL line high, pull the SDA line low) and continue with Step 2 of the write procedure (see the I2C Interface Data Transfers: Data Write section) to perform a write. Send a repeated start condition (while holding the SCL line high, pull the SDA line low) and continue with Step 2 of this procedure to perform a read from another address. Send a repeated start condition (while holding the SCL line high, pull the SDA line low) and continue with Step 8 of this procedure to perform a read from the same address.
3. 4. 5.
6. 7. 8.
In Figure 42, the AD8155 read process is shown. The SCL signal is shown along with a general read operation and a specific example. In this example, the value 0x49 is read from Address 0x6D of an AD8155 device with a 0x53 part address. The part address is seven bits wide and is composed of the AD8155 static upper four bits (b1010) and the pin-programmable lower three bits (I2C_A[2:0]). The address pins are set to b011. In Figure 42, the corresponding step number is visible in the circle under the waveform. The SCL line is driven by the I2C master and never by the AD8155 slave. As for the SDA line, the data in the shaded polygons is driven by the AD8155, whereas the data in the nonshaded polygons is driven by the I2C master. The end phase case shown is that of Step 13a. It is important to note that the SDA line changes only when the SCL line is low, except for the case of sending a start, stop, or repeated start condition, as in Step 1, Step 7, and Step 13. In Figure 42, A is the same as ACK. Equally, Sr represents a repeated start where the SDA line is brought high before SCL is raised. SDA is then dropped while SCL is still high.
9. 10. 11. 12. 13.
SDA START
b1010
ADDR [2:0]
R/ W
A
REGISTER ADDR
A
Sr
b1010
ADDR [2:0]
R/ A W
DATA
A
STOP
SDA 1 2 2 3 4 5 6 7 8 8 9 10 11 12 13a
08262-043
Figure 42. I2C Read Diagram
Rev. 0 | Page 25 of 36
AD8155 APPLICATIONS INFORMATION
The main application of the AD8155 is to support redundancy on both the backplane side and the line interface side of a serial link. Each port consists of four lanes to support standards such as RXAUI. Figure 43 illustrates redundancy in an RXAUI backplane system. Each line card is connected to two switch fabrics (primary and redundant). The device can be configured
FABRIC INTERFACE TRAFFIC MANAGERS NETWORK PROCESSOR
to support either 1 + 1 or 1:1 redundancy. Also, the AD8155 can enable module redundancy, as shown in Figure 44, and can be used as a four- or six-lane signal conditioning device to enable high speed serial communication over long copper links.
PHYSICAL INTERFACE
MACs FRAMERS
PRIMARY SWITCH FABRIC
AD8155
LINE CARDS FABRIC CARDS
PHYSICAL INTERFACE
MACs FRAMERS
FABRIC INTERFACE TRAFFIC MANAGERS NETWORK PROCESSOR
AD8155
BACKPLANE
Figure 43. Using the AD8155 for Switch Redundancy
PRIMARY MODULE MACs FRAMERS REDUNDANT MODULE FABRIC INTERFACE TRAFFIC MANAGERS NETWORK PROCESSOR
LINE CARD
Figure 44. Using the AD8155 for Module Redundancy
Z0 IN 1 Z0 Z0 IN 2 ASIC 1 Z0 Z0 OUT 3 Z0 Z0 OUT 4 Z0 LOSSY CHANNEL PE EQ IN 4 Z0 LOSSY CHANNEL
08262-047
Z0 EQ PE OUT 1 Z0 Z0 EQ PE OUT 2 Z0 Z0 PE EQ IN 3 Z0 Z0 ASIC 2
Figure 45. Using the AD8155 for Signal Conditioning
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08262-046
AD8155
08262-045
REDUNDANT SWITCH FABRIC
AD8155
OUTPUT COMPLIANCE
In low voltage applications, users must pay careful attention to both the differential and common-mode signal levels. The choice of output voltage swing, preemphasis setting, supply voltages (VCC and VTTO), and output coupling (ac or dc) affect peak and settled single-ended voltage swings and the commonmode shift measured across the output termination resistors. These choices also affect output current and, consequently, power consumption. For certain combinations of supply voltage and output coupling, output voltage swing and preemphasis settings may violate the single-ended absolute output low voltage, as specified in Table 1. Under these conditions, the performance is degraded; therefore, these settings are not recommended. Table 19 includes annotations that identify these settings. Table 19 shows the change in output common mode (VOCM = VCC - VOCM) with output level (VSW) and preemphasis setting. Table 19 also shows the minimum and maximum peak singleended output levels (VL-PE and VH-PE, respectively). The singleended output levels are calculated for VTTO supplies of 3.3 V and 1.8 V for both ac- and dc-coupled outputs to illustrate the practical challenges of reducing the supply voltage. 0 dB or 6 dB. Table 19 shows that with preemphasis disabled, a dc-coupled transmitter causes a 200 mV common-mode shift across the termination resistors, whereas an ac-coupled transmitter causes twice the common-mode shift. Notice that with VCC and VTTO powered from a 1.8 V supply, the single-ended output voltage swings between 1.8 V and 1.4 V when dc-coupled and between 1.6 V and 1.2 V when ac-coupled. In both cases, these levels are greater than the minimum VL limit of 725 mV, and VCC satisfies the minimum VCC limit of 1.8 V with the TX_HEADROOM bit set to 0. Note that setting TX_HEADROOM = 1 violates the minimum VCC limit of 2.5 V.
Example 2: 1.8 V, PE = 6 dB
With a PE setting of 6.02 dB, the ac-coupled transmitter has single-ended swings from 1.4 V to 0.6 V, whereas the dccoupled transmitter outputs swing between 1.8 V and 1 V. The peak minimum single-ended swing (VL-PE) of the ac-coupled transmitter, in this case, exceeds the minimum VL limit of 725 mV by 125 mV. While theoretically in violation of the specification, in practice, this setting is viable, especially at high data rates. The transmitter theoretical peak voltage is rarely achieved in practice because the high frequency characteristic of the preemphasis is attenuated at the output pins by the lowpass nature of the PC board environment and the channel. For 6.5 Gbps PE (SEL4G = 0), a 30% reduction of overshoot as measured at the PC board is possible. For an output level of 400 mV diff and a PE setting of 6 dB, the user can calculate a maximum overshoot of 400 mV diff but can measure only a 270 mV overshoot. With the preemphasis configured for 4.25 Gbps operation (SEL4G = 1), the measured overshoot more closely matches the theoretical maximum. In this case, the peak minimum voltage limit should be more closely observed.
TX_HEADROOM
For output levels greater than 400 mV diff (800 mV p-p diff), setting the TX_HEADROOM bit to 1 allows the transmitter an extra 200 mV of output compliance range. When the TX_ HEADROOM bit is enabled, a core supply voltage, VCC 2.5 V, is required. Enabling TX_HEADROOM increases the core supply current. TX_HEADROOM can be enabled on a per-port basis through Bits[6:4] in Register 0x05. A value of 0 disables the headroom-generating circuitry; a value of 1 enables it.
Example 1: 1.8 V, PE Disabled
Consider a typical application using pin control mode. In this case, the default output level of 400 mV diff (800 mV p-p diff) is selected, and the user can choose preemphasis settings of
Rev. 0 | Page 27 of 36
AD8155
SIGNAL LEVELS AND COMMON-MODE SHIFT FOR AC-COUPLED AND DC-COUPLED OUTPUTS
Table 19. Output Voltage Range and Output Common-Mode Shift vs. Output Level and PE Setting
AC-Coupled Transmitter Register Output Levels and PE Boost Setting PE TX[A/B/C] VSW-DC 1 VSW-PE1 Boost Level/PE (mV) (mV) (%) PE (dB) Control 2 200 200 0.00 0.00 0x00 200 300 50.00 3.52 0x01 200 400 100.00 6.02 0x02 200 500 150.00 7.96 0x03 200 600 200.00 9.54 0x04 200 700 250.00 10.88 0x05 200 800 300.00 12.04 0x06 300 300 0.00 0.00 0x10 300 400 33.33 2.50 0x11 300 500 66.67 4.44 0x12 300 600 100.00 6.02 0x13 300 700 133.33 7.36 0x14 300 800 166.67 8.52 0x15 300 900 200.00 9.54 0x16 400 400 0.00 0.00 0x20 400 500 25.00 1.94 0x21 400 600 50.00 3.52 0x22 400 700 75.00 4.86 0x23 400 800 100.00 6.02 0x24 400 900 125.00 7.04 0x25 400 1000 150.00 7.96 0x26 600 600 0.00 0.00 0x30 600 700 16.67 1.34 0x31 600 800 33.33 2.50 0x32 600 900 50.00 3.52 0x33 600 1000 66.67 4.44 0x34 600 1100 83.33 5.26 0x35 600 1200 100.00 6.02 0x36
1 2
DC-Coupled Transmitter VCC = VTTO = 3.3 V VCC = VTTO = 1.8 V VOCM1 (mV) 100 150 200 250 300 350 400 150 200 250 300 350 400 450 200 250 300 350 400 450 500 300 350 400 450 500 550 600 VH-PE1 (V) 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 VL-PE1 (V) 3.1 3 2.9 2.8 2.7 2.6 2.5 3 2.9 2.8 2.7 2.6 2.5 2.4 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.7 2.6 2.5 2.4 2.3 2.2 2.13 VH-PE1 (V) 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 VL-PE1 (V) 1.6 1.5 1.4 1.3 1.2 1.1 1 1.5 1.4 1.3 1.2 1.1 1 0.9 1.4 1.3 1.2 1.1 1 0.9 0.8 1.2 1.1 1 0.9 0.8 0.7 0.6 5
Output Current VOCM1 (mV) 200 300 400 500 600 700 800 300 400 500 600 700 800 900 400 500 600 700 800 900 1000 600 700 800 900 1000 1100 1200
VCC = VTTO = 3.3 V VCC = VTTO = 1.8 V VH-PE1 (V) 3.2 3.15 3.1 3.05 3 2.95 2.9 3.15 3.1 3.05 3 2.95 2.9 2.85 3.1 3.05 3 2.95 2.9 2.85 2.8 3 2.95 2.9 2.85 2.8 2.75 2.7 VL-PE1 (V) 3 2.85 2.7 2.55 2.4 2.25 2.1 2.85 2.7 2.55 2.4 2.25 2.1 1.95 2.7 2.55 2.4 2.25 2.1 3 1.95 4 1.84 2.4 2.25 2.13 1.954 1.84 1.654 1.54 VH-PE1 (V) 1.7 1.65 1.6 1.55 1.5 1.45 1.4 1.65 1.6 1.55 1.5 1.45 1.4 1.35 1.6 1.55 1.5 1.45 1.4 1.35 1.3 1.5 1.45 1.4 1.35 1.3 1.25 1.2 VL-PE1 (V) 1.5 1.35 1.2 1.05 0.9 0.75 0.6 1.35 1.2 1.05 0.9 0.75 0.6 0.45 1.2 1.05 0.9 0.75 0.6 0.45 0.3 0.9 0.75 0.65 0.454 0.34 0.154 04
ITTO1 (mA) 8 12 16 20 24 28 32 12 16 20 24 28 32 36 16 20 24 28 32 36 40 24 28 32 36 40 44 48
Symbol definitions are shown in Table 20. TX[A/B/C] level/PE control registers are port level control registers at Address 0x49, Address 0x89, and Address 0xC9. Per-lane level and PE control are in separate registers. 3 This setting requires TX_HEADROOM = 1 to ensure adequate output compliance. 4 This setting is not recommended for ac-coupled outputs because the theoretical output low level is below the minimum output voltage limit listed in Table 1. 5 This setting is not recommended because the output level is below the minimum output voltage limit listed in Table 1. Use VCC = 2.5 V and TX_HEADROOM = 1.
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AD8155
Table 20. Symbol Definitions
Symbol IDC IPE ITTO VDPP-DC VDPP-PE VSW-DC VSW-PE VOCM_DC-COUPLED VOCM_AC-COUPLED VOCM VH-DC VL-DC VH-PE VL-PE Formula Programmable Programmable IDC + IPE 25 x IDC x 2 25 x ITTO x 2 VDPP-DC/2 = VH-DC - VL-DC VDPP-PE/2 = VH-PE - VL-PE 25 x ITTO/2 50 x ITTO/2 VTTO - VOCM = ( VH-DC + VL-DC )/2 VTTO - VOCM + VDPP-DC/2 VTTO - VOCM - VDPP-DC/2 VTTO - VOCM + VDPP-PE/2 VTTO - VOCM - VDPP-PE/2 Definition Output current that sets output level Output current for PE delayed tap Total transmitter output current Peak-to-peak differential voltage swing of nonpreemphasized waveform Peak-to-peak differential voltage swing of preemphasized waveform DC single-ended voltage swing Preemphasized single-ended voltage swing Output common-mode shift, dc-coupled outputs Output common-mode shift, ac-coupled outputs Output common-mode voltage DC single-ended output high voltage DC single-ended output low voltage Maximum single-ended output voltage Minimum single-ended output voltage
VTTO VH-PE VH-DC VOCM VSW-DC VL-DC VL-PE VSW-PE
tPE
Figure 46. VH, VL, and VOCM
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08262-040
AD8155
SUPPLY SEQUENCING
Ideally, all power supplies should be brought up to the appropriate levels simultaneously (power supply requirements are set by the supply limits in Table 1 and the absolute maximum ratings listed in Table 3). In the event that the power supplies to the AD8155 are brought up separately, the supply power-up sequence is as follows: DVCC is powered first, followed by VCC, and lastly VTTI and VTTO. The power-down sequence is reversed, with VTTI and VTTO being powered off first. VTTI and VTTO contain ESD protection diodes to the VCC power domain (see Figure 38 and Figure 39). To avoid a sustained high current condition in these devices (ISUSTAINED < 64 mA), the VTTI and VTTO supplies should be powered on after VCC and should be powered off before VCC. If the system power supplies have a high impedance in the powered off state, then supply sequencing is not required provided the following limits are observed: * * Peak current from VTTI or VTTO to VCC < 200 mA Sustained current from VTTI or VTTO to VCC < 64 mA Table 21. Alternate Supply Configuration Examples
Signal Level 1.2 V CML GND - 400 mV diff VCC, VTTI, VTTO 1.2 V GND VEE -2.1 V VEE -0.6 V -3.3 V VEE -1.8 V
The AD8155 control signals are always referenced between DVCC and VEE and, when using a split supply configuration, logic level-shift circuits should be used. The evaluation board design shows the use of the Analog Devices, Inc., ADUM1250 I2C isolator and a level shifter to level-shift the SCL and SDA signals (for information about the evaluation board, see the Ordering Guide).
Evaluation of DC-Coupled Links
When evaluating the AD8155 dc-coupled, note that most lab equipment is ground referenced whereas the AD8155 high speed I/O are connected by 50 on-die termination resistors to VTTI and VTTO. To interface the AD8155 to ground-referenced, high speed instrumentation (for example, the 50 inputs of a high speed oscilloscope), it is necessary to level-shift the outputs by either using a dc-blocking network or powering the AD8155 between ground and a negative supply. For example, to evaluate 1.8 V dc-coupled transmitter performance with a 50 ground-referenced oscilloscope, use the following supply configuration: VCC = VTTO = VTTI = Ground VEE = -1.8 V Ground < DVCC < 1.5 V
SINGLE SUPPLY vs. MULTIPLE SUPPLY OPERATION
The AD8155 supports a flexible supply voltage of 1.8 V to 3.3 V. For some dc-coupled links, 1.2 V or ground-referenced signaling may be desired. In these cases, the AD8155 can be run with a split supply configuration. An example is shown in Figure 47.
0V VTTI VCC DVCC VTTO
INITIALIZATION SEQUENCE FOR LOW POWER AND LOS_INT OPERATION
Z0 RX
TX +
Z0
50
50
50
50
CML - Z0 VOH = 0mV VOL = -400mV Z0
AD8155
VEE = -3.3V (OR -1.8V)
The following programming sequence is required to initialize the device in a low power mode and to enable the LOS_INT: set the reserved bits to Logic 1 in the RX and TX control registers by writing the value 0x0C to the 0x40, 0x48, 0x80, 0x88, 0xC0, and 0xC8 registers.
MCU_V DD
DVCC I2C_SCL I2C_SDA
MCU
ADuM1250
TO AD8155
08262-048
MCU_V SS
VEE
Figure 47. Multiple Supply Operation
Rev. 0 | Page 30 of 36
AD8155
PRINTED CIRCUIT BOARD (PCB) LAYOUT GUIDELINES
The high speed differential inputs and outputs should be routed with 100 controlled impedance differential transmission lines. The transmission lines, either microstrip or stripline, should be referenced to a solid low impedance reference plane. An example of a PCB cross-section is shown in Figure 48. The trace width (W), differential spacing (S), height above reference plane (H), and dielectric constant of the PCB material determine the characteristic impedance. Adjacent channels should be kept apart by a distance greater than 3 W to minimize crosstalk.
W S W
It is recommended that a via array of 4 x 4 or 5 x 5 with a diameter of 0.3 mm to 0.33 mm be used to set a pitch between 1.0 mm and 1.2 mm. A representative of these arrays is shown in Figure 49.
THERMAL VIA
SOLDERMASK SIGNAL (MICROSTRIP) PCB DIELECTRIC REFERENCE PLANE PCB DIELECTRIC SIGNAL (STRIPLINE) PCB DIELECTRIC REFERENCE PLANE PCB DIELECTRIC W S W
08262-049
Figure 49. PCB Thermal Paddle and Via
H
Stencil Design for the Thermal Paddle
To effectively remove heat from the package and to enhance electrical performance, the thermal paddle must be soldered (bonded) to the PCB thermal paddle, preferably with minimum voids. However, eliminating voids may not be possible because of the presence of thermal vias and the large size of the thermal paddle for larger size packages. Also, outgassing during the reflow process may cause defects (splatter, solder balling) if the solder paste coverage is too big. It is recommended that smaller multiple openings in the stencil be used instead of one big opening for printing solder paste on the thermal paddle region. This typically results in 50% to 80% solder paste coverage. Figure 50 shows how to achieve these levels of coverage. Voids within solder joints under the exposed paddle can have an adverse affect on high speed and RF applications, as well as on thermal performance. Because the LFCSP package incorporates a large center paddle, controlling solder voiding within this region can be difficult. Voids within this ground plane can increase the current path of the circuit. The maximum size for a void should be less than via pitch within the plane. This assures that any one via is not rendered ineffectual when any void increases the current path beyond the distance to the next available via.
Figure 48. Example of a PCB Cross-Section
Thermal Paddle Design
The LFCSP is designed with an exposed thermal paddle to conduct heat away from the package and into the PCB. By incorporating thermal vias into the PCB thermal paddle, heat is dissipated more effectively into the inner metal layers of the PCB. To ensure device performance at elevated temperatures, it is important to have a sufficient number of thermal vias incorporated into the design. An insufficient number of thermal vias results in a JA value larger than specified in Table 1. Additional PCB footprint and assembly guidelines are described in the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP).
Rev. 0 | Page 31 of 36
08262-050
THERMAL PADDLE
AD8155
SOLDER MASK VIA COPPER PLATING
1.35mm x 1.35mm SQUARES AT 1.65mm PITCH COVERAGE: 68%
08262-051
(A)
(B)
(C)
(D)
Figure 50.Typical Thermal Paddle Stencil Design
Large voids in the thermal paddle area should be avoided. To control voids in the thermal paddle area, solder masking may be required for thermal vias to prevent solder wicking inside the via during reflow, thus displacing the solder away from the interface between the package thermal paddle and thermal paddle land on the PCB. There are several methods employed for this purpose, such as via tenting (top or bottom side), using dry film solder mask; via plugging with liquid photo-imagible (LPI) solder mask from the bottom side; or via encroaching. These options are depicted in Figure 51. In case of via tenting, the solder mask diameter should be 100 microns larger than the via diameter.
Figure 51. Solder Mask Options for Thermal Vias: (a) Via Tenting from the Top; (b) Via Tenting from the Bottom; (c)Via Plugging, Bottom; and (d) Via Encroaching, Bottom
A stencil thickness of 0.125 mm is recommended for 0.4 mm and 0.5 mm pitch parts. The stencil thickness can be increased to 0.15 mm to 0.2 mm for coarser pitch parts. A laser-cut, stainless steel stencil is recommended with electropolished trapezoidal walls to improve the paste release. Because not enough space is available underneath the part after reflow, it is recommended that no clean Type 3 paste be used for mounting the LFCSP. Inert atmosphere is also recommended during reflow.
Rev. 0 | Page 32 of 36
08262-052
AD8155 REGISTER MAP
All registers are port-level and global registers, unless otherwise noted. Table 22. Register Definitions
Mnemonic Reset Switch Control 1 Switch Control 2 Global Squelch Ctrl Switch Core/ Headroom Mode RXA Disable RXA EQ Setting RXA LOS Control RXA Lane 1/ RXA Lane 0 EQ Setting RXA P/N Swap RXA LOS Status TXA Disable TXA Level/PE Control TXA Lane1/ TXA Lane 0 PE Setting TXA Per-Lane Level Setting RXB Disable RXB EQ Setting RXB LOS Ctrl RXB Lane 1/ RXB Lane 0 EQ Setting RXB P/N Swap RXB LOS Status TXB Disable TXB Level/PE Control TXB Lane1/ TXB Lane 0 PE Setting TXB Per-Lane Level Setting RXC Disable Addr. 0x00 0x01 0x02 0x04 0x05 0x0F 0x40 0x41 0x51 0x421 Reserved; set to 0 Reserved; set to 0 Reserved; set to 0 Reserved; set to 0 A1EQ[3] Reserved; set to 0 Reserved; set to 0 TX_HEAD ROOM_C Reserved; set to 0 Reserved; set to 0 Reserved; set to 0 Reserved; set to 0 A1EQ[2] Reserved; set to 0 TX_HEAD ROOM_B Reserved; set to 0 Reserved; set to 0 Reserved; set to 0 Reserved; set to 0 A1EQ[1] Bit 7 Bit 6 LBC Bit 5 LBB Bit 4 LBA SEL4G Reserved; set to 0 TX_HEAD ROOM_A Reserved; set to 0 Reserved; set to 0 Reserved; set to 0 Reserved; set to 0 A1EQ[0] GSQLCH_ENB Reserved; set to 1 Reserved; set to 1 Bit 3 Set to 0 Bit 2 Set to 0 Bit 1 SELAb/B[1] Bit 0 RESET SELAb/B[0] BICAST Reserved; set to 1 XCORE_ENB MODE[0] RXDIS A0 AEQ[0] LOS_ENB A0EQ[0] Default 0x00 0x00 0x0F 0x01 0x00 0x00 0x00 0x05 0x00
Reserved; set to 0 Reserved AEQ[3] Reserved; set to 0 A0EQ[3]
Reserved; set to 0 Reserved AEQ[2] LOS_FILT A0EQ[2]
MODE[1] RXDIS A1 AEQ[1] Reserved; set to 0 A0EQ[1]
0x441 0x451 0x48 0x49 0x4A1
Reserved; set to 0 Reserved Reserved; set to 0
Reserved; set to 0 Reserved Reserved; set to 0
Reserved; set to 0 LOSA1 sticky Reserved; set to 0 ALEV[1] A1PE[1]
Reserved; set to 0 LOSA0 sticky Reserved; set to 0 ALEV[0] A1PE[0]
Reserved; set to 0 Reserved Reserved
Reserved; set to 0 Reserved Reserved APE[2] A0PE[2]
PNA1 LOSA1 active TXDIS A1 APE[1] A0PE[1]
PNA0 LOSA0 active TXDIS A0 APE[0] A0PE[0]
0x00
0x00 0x20 0x00
A1PE[2]
0x4C1 0x80 0x81 0x91 0x821
Reserved Reserved; set to 0 Reserved; set to 0 Reserved; set to 0 B1EQ[3]
Reserved Reserved; set to 0 Reserved; set to 0 Reserved; set to 0 B1EQ[2]
Reserved Reserved; set to 0 Reserved; set to 0 Reserved; set to 0 B1EQ[1]
Reserved Reserved; set to 0 Reserved; set to 0 Reserved; set to 0 B1EQ[0]
A1OLEV[1] Reserved BEQ[3] Reserved; set to 0 B0EQ[3]
A1OLEV[0] Reserved BEQ[2] LOS_FILT B0EQ[2]
A0OLEV[1] RXDIS B1 BEQ[1] Reserved; set to 0 B0EQ[1]
A0OLEV[0] RXDIS B0 BEQ[0] LOS_ENB B0EQ[0]
0xAA 0x00 0x00 0x05 0x00
0x841 0x851 0x88 0x89 0x8A1
Reserved; set to 0 Reserved Reserved; set to 0
Reserved; set to 0 Reserved Reserved; set to 0
Reserved; set to 0 LOSB1 sticky Reserved; set to 0 BLEV[1] B1PE[1]
Reserved; set to 0 LOSB0 sticky Reserved; set to 0 BLEV[0] B1PE[0]
Reserved; set to 0 Reserved Reserved
Reserved; set to 0 Reserved Reserved BPE[2] B0PE[2]
PNB1 LOSB1 active TXDIS B1 BPE[1] B0PE[1]
PNB0 LOSB0 active TXDIS B0 BPE[0] B0PE[0]
0x00
0x00 0x20 0x00
B1PE[2]
0x8C1 0xC0
Reserved; set to 0 Reserved; set to 0
Reserved; set to 0 Reserved; set to 0
Reserved; set to 0 Reserved; set to 0
Reserved; set to 0 Reserved; set to 0
B1OLEV[1] Reserved
B1OLEV[0] Reserved
B0OLEV[1] RXDIS C1
B0OLEV[0] RXDIS C0
0xAA 0x00
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AD8155
Mnemonic RXC EQ Setting RXC LOS Ctrl RXC Lane 1/ RXC Lane 0 Setting RXC P/N Swap RXC LOS Status TXC Disable TXC Level/PE Control TXC Lane1/ TXC Lane 0 PE Setting TXC Per-Lane Level Setting
1
Addr. 0xC1 0xD1 0xC21
Bit 7 Reserved; set to 0 Reserved; set to 0 C1EQ[3]
Bit 6 Reserved; set to 0 Reserved; set to 0 C1EQ[2]
Bit 5 Reserved; set to 0 Reserved; set to 0 C1EQ[1]
Bit 4 Reserved; set to 0 Reserved; set to 0 C1EQ[0]
Bit 3 CEQ[3] Reserved; set to 0 C0EQ[3]
Bit 2 CEQ[2] LOS_FILT C0EQ[2]
Bit 1 CEQ[1] Reserved; set to 0 C0EQ[1]
Bit 0 CEQ[0] LOS_ENB C0EQ[0]
Default 0x00 0x05 0x00
0xC41 0xC51 0xC8 0xC9 0xCA1
Reserved; set to 0 Reserved Reserved; set to 0
Reserved; set to 0 Reserved Reserved; set to 0
Reserved; set to 0 LOSC1 sticky Reserved; set to 0 CLEV[1] C1PE[1]
Reserved; set to 0 LOSC0 sticky Reserved; set to 0 CLEV[0] C1PE[0]
Reserved; set to 0 Reserved Reserved
Reserved; set to 0 Reserved Reserved CPE[2] C0PE[2]
PNC1 LOSC1 active TXDIS C1 CPE[1] C0PE[1]
PNC0 LOSC0 active TXDIS C0 CPE[0] C0PE[0]
0x00
0x00 0x20 0x00
C1PE[2]
0xCC1
Reserved
Reserved
Reserved
Reserved
C1OLEV[1]
C1OLEV[0]
C0OLEV[1]
C0OLEV[0]
0xAA
Per-lane registers.
Rev. 0 | Page 34 of 36
AD8155 OUTLINE DIMENSIONS
9.00 BSC SQ 0.60 MAX 0.60 MAX
49 48
0.30 0.25 0.18
64 1
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
8.75 BSC SQ
EXPOSED PAD
(BOTTOM VIEW)
*6.15 6.00 SQ 5.85
0.50 0.40 0.30
33 32
17 16
1.00 0.85 0.80
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC 0.20 REF
7.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
080108-B
SEATING PLANE
*COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 EXCEPT FOR EXPOSED PAD DIMENSION
Figure 52. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm x 9 mm Body, Very Thin Quad (CP-64-2) Dimensions shown in millimeters
ORDERING GUIDE
Model AD8155ACPZ 1 AD8155ACPZ-R71 AD8155-EVALZ1
1
Temperature Range -40C to +85C -40C to +85C
Package Description 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board
Package Option CP-64-2 CP-64-2
Z = RoHS Compliant Part.
Rev. 0 | Page 35 of 36
AD8155 NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
(c)2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08262-0-7/09(0)
Rev. 0 | Page 36 of 36

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