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Serial EEPROM Series
High Reliability Series EEPROMs I2C BUS
BR24A-WM series
Description BR24A-WM series is a serial EEPROM of I2C BUS interface method. Features 2 1) Completely conforming to the world standard I C BUS. All controls available by 2 ports of serial clock(SCL) and serial data(SDA) 2) Other devices than EEPROM can be connected to the same port, saving microcontroller port 3) 2.5V~5.5V single power source action most suitable for battery use 4) Page write mode useful for initial value write at factory shipment 5) Highly reliable connection by Au pad and Au wire 6) Auto erase and auto end function at data rewrite 7) Low current consumption *1 At write operation (5V) : 1.2mA (Typ.) At read operation (5V) : 0.2mA (Typ.) At standby operation (5V) : 0.1A (Typ.) 8) Write mistake prevention function Write (write protect) function added Write mistake prevention function at low voltage 9) SOP8/SOP-J8/MSOP8 compact package *2 10) Data rewrite up to 100,000 times 11) Data kept for 40 years 12) Noise filter built in SCL / SDA terminal 13) Shipment data all address FFh
*1 BR24A32-WM,BR24A64-WM : 1.5mA *2 Refer to following list
No.09001ECT02
Page write Number of Pages Product number
8Byte BR24A01A-WM BR24A02-WM
16Byte BR24A04-WM BR24A08-WM BR24A16-WM
32Byte BR24A32-WM BR24A64-WM
BR24A series Capacity 1Kbit 2Kbit 4Kbit 8Kbit 16Kbit 32Kbit 64Kbit
Bit format 128x8 256x8 512x8 1Kx8 2Kx8 4Kx8 8Kx8
Type BR24A01A-WM BR24A02-WM BR24A04-WM BR24A08-WM BR24A16-WM BR24A32-WM BR24A64-WM
Power source Voltage 2.55.5V 2.55.5V 2.55.5V 2.55.5V 2.55.5V 2.55.5V 2.55.5V
SOP8
SOP-J8
MSOP8
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1/17
2009.08 - Rev.C
BR24A-WM series
Absolute maximum ratings (Ta=25) Parameter Impressed voltage Permissible dissipation Storage temperature range Action temperature range Terminal voltage Memory cell characteristics (VCC=2.55.5V) Parameter Number of data rewrite times Data hold years *1
Shipment data all address FFh *1 Not 100% TESTED
*1
Technical Note
symbol VCC Pd Tstg Topr -
Limits -0.3+6.5 450 (SOP8) *1 450 (SOP-J8) *2 310 (MSOP8) *3 -65+125 -40+105 -0.3VCC+1.0
Unit V mW V
When using at Ta=25 or higher, 4.5mW(*1,*2) , 3.1mW(*3) to be reduced per 1
Min. 100,000 40
Limits Typ. -
Max. -
Unit Times Years
Test Condition Ta=-40105 Ta=25
Recommended operating conditions Parameter Power source voltage Input voltage
Symbol VCC VIN
Limits 2.55.5 0VCC
Unit V
Electrical characteristics (Unless otherwise specified, Ta=-40+105, VCC=2.55.5V) Limits Parameter Symbol Unit Conditions Min. Typ. Max. "HIGH" input voltage VIH 0.7VCC V "LOW" input voltage VIL 0.3 VCC V "LOW" output voltage 1 VOL 0.4 V IOL=3.0mA (SDA) Input leak current ILI -1 1 A VIN=0VVCC Output leak current ILO -1 1 A VOUT=0VVCC, (SDA) 2.0 *1 VCC=5.5V,fSCL=400kHz, tWR=5ms, ICC1 mA Byte write, Page write Current consumption 3.0 *2 at action VCC=5.5V,fSCL=400kHz ICC2 0.5 mA Random read, current read, sequential read VCC=5.5V, SDASCL=VCC Standby current ISB 2.0 A A0, A1, A2=GND, WP=GND
Radiation resistance design is not made. *1 BR24A01A/02/04/08/16-WM, *2 BR24A32/64-WM
Action timing characteristics
(Unless otherwise specified, Ta=-40+105, VCC=2.55.5V) FAST-MODE STANDARD-MODE 2.5VVCC5.5V 2.5VVCC5.5V Parameter Symbol Min. Typ. Max. Min. Typ. Max. SCL frequency fSCL 400 100 Data clock "HIGH" time tHIGH 0.6 4.0 Data clock "LOW" time tLOW 1.2 4.7 SDA, SCL rise time *1 tR 0.3 1.0 SDA, SCL fall time *1 tF 0.3 0.3 Start condition hold time tHD:STA 0.6 4.0 Start condition setup time tSU:STA 0.6 4.7 Input data hold time tHD:DAT 0 0 Input data setup time tSU:DAT 100 250 Output data delay time tPD 0.1 0.9 0.2 3.5 Output data hold time tDH 0.1 0.2 Stop condition setup time tSU:STO 0.6 4.7 Bus release time before transfer start tBUF 1.2 4.7 Internal write cycle time tWR 5 5 Noise removal valid period (SDA, SCL terminal) tI 0.1 0.1 WP hold time tHD:WP 0 0 WP setup time tSU:WP 0.1 0.1 WP valid time tHIGH:WP 1.0 1.0 *1 Not 100% tested
Unit kHz s s s s s s ns ns s s s s ms s ns s s
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2/17
2009.08 - Rev.C
BR24A-WM series
Technical Note
FAST-MODE and STANDARD-MODE FAST-MODE and STANDARD-MODE are of same actions, and mode is changed. They are distinguished by action speeds. 100kHz action is called STANDARD-MODE, and 400kHz action is called FAST-MODE. This action frequency is the maximum action frequency, so 100kHz clock may be used in FAST-MODE. At VCC=2.5V5.5V , 400kHz, namely, action is made in FASTMODE. (Action is made also in STANDARD-MODE.)
Sync data input / output timing
tR SCL tHD:STA SDA () (input) tBUF
(output) ()
tF
tHIGH
SCL
tSU:DAT tLOW tHD:DAT
tSU:STA
SDA
tHD:STA
tSU:STO
tPD
tDH
SDA
START BIT
STOP BIT
Input read at the rise edge of SCL Data output in sync with the fall of SCL
Fig.1-(a) Sync data input / output timing
Fig.1-(b) Start-stop bit timing
SCL
SCL
SDA
D0
Write data
DATA(1) D1 D0 ACK
ACK WR
Stop condition Start condition
DATA(n) ACK WR
SDA
(n-th address)
WP
Stop condition
tSUWP
HDWP
Fig.1-(c) Write cycle timing
Fig.1-(d) WP timing at write execution
SCL DATA(1) SDA D1 D0 ACK tHIGH:WP WP DATA(n) ACK tWR
At write execution, in the area from the D0 taken clock rise of the first DATA(1), to tWR, set WP="LOW". By setting WP "HIGH" in the area, write can be cancelled. When it is set WP="HIGH" during tWR, write is forcibly ended, and data of address under access is not guaranteed, therefore write it once again.
Fig.1-(e) WP timing at write cancel
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3/17
2009.08 - Rev.C
BR24A-WM series
Block diagram
Technical Note
*2
A0
1
*1
1Kbit~64Kbit EEPROM array
7bit 11bit 8bit 12bit 9bit 13bit 10bit
8
8bit
Vcc
*2
A1
2
Address decoder
*1
7bit 11bit 8bit 12bit 9bit 13bit 10bit
Slave - word address register
Data register
7
WP
*2
A2
3
START
STOP
Control circuit
ACK
6
SCL
GND
4
1
High voltage generating circuit
7bit : BR24A01A-WM 8bit : BR24A02-WM 9bit : BR24A04-WM
Power source voltage detection
10bit : BR24A08-WM 11bit : BR24A16-WM 12bit : BR24A32-WM 13bit : BR24A64-WM
5
: BR24A04-WM : BR24A08-WM : BR24A16-WM
SDA
2
A0=N.C. A0, A1=N.C. A0, A1= N.C. A2=Don't Use
Fig.2 Block diagram
Pin assignment and description
A0 A1 A2 GND 1 2 3 4 BR24A01A-WM BR24A02-WM BR24A04-WM BR24A08-WM BR24A16-WM BR24A32-WM BR24A64-WM 8 7 6 5
Vcc WP SCL SDA
Terminal name A0 A1 A2 GND SDA SCL WP Vcc
Input / output Input Input Input Input / output Input Input -
Function
BR24A01A-WM BR24A02-WM BR24A04-WM BR24A08-WM BR24A16-WM BR24A32-WM BR24A64-WM
Slave address setting Slave address setting Slave address setting
Not connected Not connected Not used
Slave address setting Slave address setting Slave address setting
Reference voltage of all input / output, 0V Slave and word address, Serial data input serial data output Serial clock input Write protect terminal Connect the power source.
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4/17
2009.08 - Rev.C
BR24A-WM series
Characteristic data (The following values are Typ. ones.)
6 5 4 VIH1,2[V] 3 2 1 0 0 3 4 5 6 Vcc[V] Fig.3 H input voltage VIH1,2(SCL,SDA,WP) 1.2
SPEC SPEC SPEC
Technical Note
6 5 4 VIL1,2[V] 3 2 1 0 1 2 0 1 2 3 4 5 6 Vcc[V] Fig.4 L input voltageVIL1,2(SCL,SDA,WP)
SPEC Ta=105 Ta=-40 Ta=25
1 0.8
VOL1[V]
0.6
SPEC Ta=105 Ta=25
0.4 0.2
Ta=105 Ta=-40 Ta=25
Ta=-40
0 0 1 2 3 4 5 6 IOL1[mA] Fig.5 L output voltageVOL1-IOL1(VCC=2.5V)
1.2 1 0.8 ILI[A] ILO[A] 0.6 0.4 0.2 0 0 3 4 5 Vcc[V] Fig.6 Input leak current ILI(SCL,WP) 1 2 6
Ta=105 Ta=25 Ta=-40
2.5
[BR24A01/02/04/08/16 series]
1 0.8 0.6 0.4 0.2 0 0 1 2 3 Vcc[V] 4 5 6
Ta=105 Ta=25 Ta=-40
2 ICC1[mA] 1.5 1 0.5 0 0
fSCL=400kHz DATA=AAh
SPEC
Ta=25 Ta=105 Ta=-40
Fig.7 Output leak currentILO(SDA)
3 4 5 6 Vcc[V] Fig.8 Current consumption at WRITE action ICC1 (fscl=400kHz)
[BR24A01/02/04/08/16 series]
1
2
3.5
[BR24A32/64 series]
0.6
SPEC fSCL=400kHz DATA=AAh SPEC
2.5
fSCL=400kHz DATA=AAh
3 2.5 ICC1[mA] 2 1.5 1 0.5 0 0
0.5 ICC2[mA] 0.4 0.3 0.2 0.1 0
2 ICC1[mA] 1.5 1 0.5 0
fSCL=100kHz DATA=AAh
SPEC
Ta=105 Ta=25
Ta=25 Ta=105 Ta=-40
Ta=-40
Ta=25 Ta=105 Ta=-40
1
2
3 Vcc[V]
4
5
6
0
1
2
3 Vcc[V]
4
5
6
0
1
2
3 Vcc[V]
4
5
6
Fig.9 Current consumption at WRITE action ICC1 (fSCL=400kHz) 3.5
[BR24A32/64 series]
Fig.10 Current consumption at READ action ICC2 (fSCL=400kHz) 0.6
SPEC
Fig.11 Current consumption at WRITE action ICC1 (fSCL=100kHz) 2.5
SPEC
3 2.5 ICC1[mA] 2 1.5 1 0.5 0 0 1 2 3 Vcc[V] 4 5 6
Ta=25 Ta=105 Ta=-40 fSCL=100kHz DATA=AAh SPEC
0.5 ICC2[mA] 0.4 0.3 0.2 0.1 0 0 3 4 5 6 Vcc[V] Fig.13 Current consumption at READ action ICC2 (fSCL=100kHz) 1 2
Ta=105 Ta=25 fSCL=100kHz DATA=AAh
2 ISB[A] 1.5 1 0.5
Ta=-40 Ta=105 Ta=-40 Ta=25
0 0 1 2 3 Vcc[V] 4 5 6
Fig.12 Current consumption at WRITE action ICC1 (fSCL=100kHz) 10000 5
Fig.14 Standby currentISB 5
SPEC2
SPEC2
1000 fSCL[kHz]
4 tHIGH [s] tLOW[s]
Ta=105 Ta=25 Ta=-40 SPEC1
4 3 2 1 0 0 1 2 3 Vcc[V] 4 5 6 0 3 4 5 Vcc[V] Fig.17 Data clock "L" time tLOW 1 2 6
Ta=105 Ta=25 Ta=-40 SPEC1
3 2 1 0
Ta=-40 Ta=25 Ta=105 SPEC1
100
SPEC2
10
1 0 1 2 3 Vcc[V] 4 5 6
Fig.15 SCL frequencyfSCL 5
SPEC2
Fig.16 Data clock "H" time tHIGH 6 5 tSU:STA[s] 4 3 2 1 0
Ta=-40 Ta=25 Ta=105 SPEC2
50
SPEC1,2
tHD:DAT(HIGH)[ns]
4 tHD:STA[s] 3 2 1 0 0 1 2 3 Vcc[V] 4 5 6
Ta=105 Ta=25 Ta=-40 SPEC1
0 -50
Ta=-40 Ta=25 Ta=105
-100 -150 -200
SPEC1
0
1
2
3 Vcc[V]
4
5
6
0
1
2
3 Vcc[V]
4
5
6
Fig.18 Start condition hold timetHD:STA
Fig.19 Start condition setup time tSU:STA
Fig.20 Input data hold time tHD:DAT(HIGH)
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5/17
2009.08 - Rev.C
BR24A-WM series
Characteristic data (The following values are Typ. ones.)
50
SPEC1,2
Technical Note
300 200 tSU:DAT(HIGH)[ns] 100 0
Ta=105 Ta=25 Ta=-40 SPEC2
300 200 tSU:DAT(LOW)[ns] 100 0
Ta=25 Ta=105 SPEC2 SPEC1
0 tHD:DAT(LOW)[ns] -50
Ta=105 Ta=25
SPEC1
-100 -150 -200 0 3 4 5 6 Vcc[V] Fig.21 Input data hold timetHD:DAT(LOW) 1 2
Ta=-40
-100 -200 0 1 2 3 Vcc[V] 4
-100 -200
Ta=-40
5
6
0
1
2
Vcc[V]
3
4
5
6
Fig.22 Input data setup timetSU:DAT(HIGH) 4 5
Fig.23 Input data setup time tSU:DAT(LOW)
4
SPEC2
SPEC2
3 tPD0[s]
3 tPD1[s]
SPEC2
4 tBUF[s] 3 2 1 0 0 1 2 3 Vcc[V] 4 5 6
Ta=-40 Ta=25 Ta=105 SPEC1
2
Ta=105 Ta=25 Ta=-40 SPEC2 SPEC1 SPEC1
2
Ta=-40 Ta=25 Ta=105 SPEC1
1
1
SPEC2 SPEC1
0 0 1 2 3 Vcc[V] 4 5 6
0 0 1 2 3 Vcc[V] 4 5 6
Fig.24 Output data delay time tPD0 6
SPEC1,2
Fig.25 Output data delay timetPD1 0.6 0.5
Fig.26 Bus release time before transfer start tBUF 0.6 0.5 tI(SCL L)[s]
5
Ta=25
tI(SCL H)[s]
4 tWR[ms] 3 2 1 0 0 1 2
Ta=-40
0.4 0.3 0.2
SPEC1,2 Ta=25
Ta=-40
0.4 0.3
Ta=-40
Ta=105
Ta=105
0.2 0.1 0
Ta=25 Ta=105 SPEC1
0.1 0 3 Vcc[V] 4 5 6 0 1 2 3 Vcc[V] 4 5 6
0
1
2
3 Vcc[V]
4
5
6
Fig.27 Internal write cycle timetWR 0.6 0.5 tI(SDA H)[s] tI(SDA L)[s] 0.4 0.3 0.2
SPEC1,2 Ta=25 Ta=105 Ta=-40
Fig.28 Noise removal valid time tI(SCL H) 0.6 0.5 0
Ta=-40
Fig.29 Noise removal valid time tI(SCL L) 0.2
SPEC1,2
0.3
Ta=25
tSU:WP[s]
0.4
-0.2
Ta=105 Ta=25 Ta=-40
0.2
SPEC1
Ta=105
0.1 0 0 1 2 3 Vcc[V] 4 5 6
-0.4
0.1 0 0 3 4 5 6 Vcc[V] Fig.31 Noise removal valid time tI(SDA L) 1 2 -0.6 0 1 2
3 Vcc[V]
4
5
6
Fig.30 Noise removal valid time tI(SDA H) 1.2 1
SPEC1,2
Fig.32 WP setup timetSU:WP
tHIGH:WP[s]
0.8 0.6 0.4 0.2 0 0 1 2 3 Vcc[V] 4 5 6
Ta=-40 Ta=25 Ta=105
Fig.33 WP valid timetHIGH:WP
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6/17
2009.08 - Rev.C
BR24A-WM series
Technical Note
I2C BUS communication I2C BUS data communication 2 I C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long, and 2 acknowledge is always required after each byte. I C BUS carries out data transmission with plural devices connected by 2 communication lines of serial data (SDA) and serial clock (SCL). Among devices, there are "master" that generates clock and control communication start and end, and "slave" that is controlled by address peculiar to devices. EEPROM becomes "slave". And the device that outputs data to bus during data communication is called "transmitter", and the device that receives data is called "receiver".
SDA
SCL
1-7 S START ADDRESS condition
8
9
1-7
8
9
1-7
8
9 P STOP condition
R/W
ACK
DATA
ACK
DATA
ACK
Fig.34 Data transfer timing
Start condition (Start bit recognition) Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL is 'HIGH' is necessary. This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this confdition is satisfied, any command is executed. Stop condition (stop bit recongnition) Each command can be ended by SDA rising from 'LOW' to 'HIGH' when stop condition (stop bit), namely, SCL is 'HIGH' Acknowledge (ACK) signal This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In master and slave, the device (-COM at slave address input of write command, read command, and this IC at data output of readcommand) at the transmitter (sending) side releases the bus after output of 8bit data. The device (this IC at slave address input of write command, read command, and -COM at data output of read command) at the receiver (receiving) side sets SDA 'LOW' during 9 clock cycles, and outputs acknowledge signal (ACK signal) showing that it has received the 8bit data. This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'. Each write action outputs acknowledge signal (ACK signal) 'LOW', at receiving 8bit data (word address and write data). Each read action outputs 8bit data (read data), and detects acknowledge signal (ACK signal) 'LOW'. When acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (-COM) side, this IC continues data output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and recognizes stop cindition (stop bit), and ends read action. And this IC gets in status. Device addressing Output slave address after start condition from master. The significant 4 bits of slave address are used for recognizing a device type. The device code of this IC is fixed to '1010'. Next slave addresses (A2 A1 A0 --- device address) are for selecting devices, and plural ones can be used on a same bus according to the number of device addresses. The most insignificant bit (R/W --- READ / WRITE) of slave address is used for designating write or read action, and is as shown below. Setting R / W to 0 ------- write (setting 0 to word address setting of random read) Setting R / W to 1 ------- read
Type BR24A01A-WM BR24A02-WM BR24A04-WM BR24A08-WM BR24A16-WM BR24A32-WM BR24A64-WM 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 Slave address A2 A2 A2 A2 P2 A2 A2 A1 A1 A1 P1 P1 A1 A1 A0 A0 PS P0 P0 A0 A0
R/W R/W R/W R/W R/W R/W

R/W PS, P0P2 are page select bits. Note) Up to 4 units BR24A04-WM, up to 2 units of BR24A08-WM, and one unit of BR24A16-WM can be connected. Device address is set by 'H' and 'L' of each pin of A0, A1, and A2.
Maximum number of connected buses 8 8 4 2 1 8 8
A0 A1 A2 GND
1 2 3 4
8 BR24A01A-WM BR24A02-WM 7 BR24A04-WM BR24A08-WM 6 BR24A16-WM BR24A32-WM BR24A64-WM 5
Vcc WP SCL SDA
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7/17
2009.08 - Rev.C
BR24A-WM series
Technical Note
Write Command Write cycle Arbitrary data is written to EEPROM. When to write only 1 byte, byte write is normally used, and when to write continuous data of 2 bytes or more, simultaneous write is possible by page write cycle. The maximum number of write bytes is specified per device of each capacity. Up to 32 arbitrary bytes can be written. (In the case of BR24A32 / A64-WM)
S T A R T SDA LINE W R I T E WA 7 R A *1 /C WK S T O P D0 A C K
SLAVE ADDRESS 1 0 1 0 A2 A1 A0
WORD ADDRESS WA 0 A C K D7
DATA
*1 As for WA7, BR24A01A-WM becomes Don't care.
Note)
Fig.35 Byte write cycle (BR24A01A/02/04/08/16-WM)
S T A R T SDA LINE W R I T E S T O P D0 A C K
SLAVE ADDRESS 1 0 1 0 A2 A1 A0
1st WORD ADDRESS
WAWA 12 11
2nd WORD ADDRESS
WA 0
DATA
*
*
*
D7 A C K
Note)
RA /C WK
*1
A C K
*1 As for WA12, BR24A32-WM becomes Don't care.
Fig.36 Byte write cycle (BR24A32/64-WM)
S T A R T SDA L IN E W R I T E
*
SLAVE ADDRESS 1 0 1 0 A 2A 1A 0
1 st W O R D A D D R E S S (n )
WA WA 1 2 11
2nd W ORD A D D R E S S (n )
WA 0
D A T A (n ) D7 A C K D0 A C K
D A TA (n + 3 1 ) D0 A C K
S T O P
*
*
*1 As for WA7, BR24A01A-WM becomes Don't care. *2 As for BR24A01A/02-WM becomes (n+7).
N ote )
RA /C WK
*1
A C K
Fig.37 Page write cycle
S T A R T SDA L IN E W R I T E WA 7 RA / C *1 WK
(BR24A01A/02/04/08/16-WM)
S T O P
SLAVE ADDRESS 1 0 1 0 A 2A 1A 0
W ORD A D D R E S S (n ) WA 0 A C K D7
D A TA (n ) D0 A C K
D A TA (n +1 5 )
*2
D0 A C K
*1 As for WA12, BR24A32-WM becomes Don't care.
N o te )
Fig.38 Page write cycle
(BR24A32/64-WM)
Data is written to the address designated by word address (n-th address) By issuing stop bit after 8bit data input, write to memory cell inside starts. When internal write is started, command is not accepted for tWR (5ms at maximum). By page write cycle, the following can be written in bulk : Up to 8 bytes ( BR24A01A-WM, BR24A02-WM : Up to 16bytes (BR24A04-WM, BR24A08-WM,BR24A16-WM : Up to 32bytes (BR24A32-WM, BR24A64-WM And when data of the maximum bytes or higher is sent, data from the first byte is overwritten. (Refer to "Internal address increment" of "Notes on page write cycle" in P8/16.) As for page write cycle of BR24A01A-WM and BR24A02-WM, after the significant 5 bits (4 significant bits in BR24A01A-WM) of word address are designated arbitrarily, and as for page write command of BR24A04-WM, BR24A08-WM, and BR24A16-WM, after page select bit (PS) of slave address is designated arbitrarily, by continuing data input of 2 bytes or more, the address of insignificant 4 bits (insignificant 3 bit in BR24A01A-WM, and BR24A02-WM) is incremented internally, and data up to 16 bytes (up to 8 bytes in BR24A01A-WM and BR24A02-WM) can be written. As for page write cycle of BR24A32-WM and BR24A64-WM, after the significant 7 bits (in the case of BR24A32-WM) of word address, or the significant 8 bits (in the case of BR24A64-WM) of word address are designated arbitrarily, by continuing data
input of 2 byte or more, the address of insignificant 5 bits is incremented internally, and data up to 32 bytes can be written.
Note)
*1 *2 *3
1 0 1 0 A 2A 1 0 A
*1 *2 *3
In BR24A16-WM, A2 becomes P2. In BR24A08-WM, BR24A16-WM, A1 becomes P1. In BR24A04-WM, A0 becomes PS, and in BR24A08-WM and BR24A16-WM, A0 becomes P0.
Fig.39 Difference of slave address of each type
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8/17
2009.08 - Rev.C
BR24A-WM series
Notes on write cycle continuous input
At STOP (stop bit), write starts.
Technical Note
S T A R T SDA LINE
SLAVE ADDRESS
W R I T E
WORD ADDRESS
*1 WA 7 WA 0
DATA(n)
DATA(n+7)*3
*2
S T O P
S T A R T
10 10
1 0 1 0 A2A1A0
D7
D0
D0
Note)
RA /C WK
A C K
A C K
A C K
Next command
Fig.40 Page write cycle
*1 *2 *3
*1 *2 *3
Note)
1 0 1 0 A 2A 1 0 A
BR24A01A-WM becomes Don't care. BR24A04-WM, BR24A08-W, and BR24A16-WM become (n+15). BR24A32-WM and BR24A64-WM become (n+31). In BR24A16-WM, A2 becomes P2. In BR24A08-WM, BR24A16-WM, A1 becomes P1. In BR24A04-WM, A0 becomes PS, and in BR24A08-WM and in BR24A16-WM, A0 becomes P0.
tWR(maximum : 5ms) Command is not accepted for this period.
*1 *2 *3
Fig.42 Difference of each type of slave address Notes on page write cycle List of numbers of page write Number of Pages Product number
8Byte BR24A01A-WM BR24A02-WM
16Byte BR24A04-WM BR24A08-WM BR24A16-WM
32Byte BR24A32-WM BR24A64-WM
The above numbers are maximum bytes for respective types. Any bytes below these can be written. In the case BR24A02-WM, 1 page=8bytes, but the page write cycle write time is 5ms at maximum for 8byte bulk write. It does not stand 5ms at maximum x 8byte=40ms(Max.). Internal address increment Page write mode (in the case of BR24A02-WM)
WA7 ----0 ----0 ----0 ------------0 0 0 ------------0 0 0 WA4 0 0 0 WA3 0 0 0 --------0 0 0 1 1 0 WA2 0 0 0 WA1 0 0 1 WA0 0 1 0
Increment
--------1 1 0 0 1 0
06h
Significant bit is fixed. No digit up
For example, when it is started from address 06h,therefore, increment is made as below, 06h 07h 00h 01h ---, which please note.
*06h06 in hexadecimal, therefore, 00000110 becomes a binary number.
Write protect (WP) terminal Write protect (WP) function When WP terminal is set VCC (H level), data rewrite of all addresses is prohibited. When it is set GND (L level), data rewrite of all address is enabled. Be sure to connect this terminal to VCC or GND, or control it to H level or L level. Do not use it open. At extremely low voltage at power ON / OFF, by setting the WP terminal 'H', mistake write can be prevented. During tWR, set the WP terminal always to 'L'. If it is set 'H', write is forcibly terminated.
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9/17
2009.08 - Rev.C
BR24A-WM series
Technical Note
Read Command Read cycle Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle. Random read cycle is a command to read data by designating address, and is used generally. Current read cycle is a command to read data of internal address register without designating address, and is used when to verify just after write cycle. In both the read cycles, sequential read cycle is available, and the next address data can be read in succession.
S T A R T SDA L IN E W R I T E WA 7 R A *1 /C WK S T A R T R E A D D7 RA /C WK S T O P D0 A C K
It is necessary to input 'H' to the last ACK.
SLAVE ADDRESS 1 0 1 0 A 2 A 1A 0 N o te )
W ORD A D D R E S S (n ) WA 0 A C K
SLAVE ADDRESS 1 0 1 0 A 2 A 1A 0
D A TA (n )
Fig.42 Random read cycle (BR24A01A/02/04/08/16-WM)
S T A R T SDA LINE W R I T E S T A R T R E A D S T O P
*1 As for WA7, BR24A01A-WM become Don't care.
SLAVE ADDRESS
1st WORD ADDRESS
2nd WORD ADDRESS
WA 0
SLAVE ADDRESS
DATA(n)
1 0 1 0 A2A1A0
*** RA /C WK
WAWA 12 11
1 0 1 0 A2 A1A0
D7
D0
Note)
*1
A C K
A C K
RA /C WK
A C K
Fig.43 Random read cycle (BR24A32/64 -WM)
S T A R T SDA L IN E R E A D D7 RA /C WK S T O P D0 A C K
*1 As for WA12, BR24A32-WM become Don't care.
S LA V E ADDRESS 1 0 1 0 A 2 A 1A 0
D A TA (n )
It is necessary to input 'H' to the last ACK.
N o te)
Fig.44 Current read cycle
S T A R T SDA LINE SLAVE ADDRESS R E A D S T O P D0 A C K
DATA(n)
DATA(n+x)
1 0 1 0 A2 A1A0 RA /C WK
D7
D0 A C K A C K
D7
Note
Fig.45 Sequential read cycle (in the case of current read cycle) In random read cycle, data of designated word address can be read. When the command just before current read cycle is random read cycle, current read cycle (each including sequential read cycle), data of incremented last read address (n)-th address, i.e., data of the (n+1)-th address is output. When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (-COM) side, the next address data can be read in succession. Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal is started at SCL signal 'H' . When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output. Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to input 'H' to ACK signal after D0, and to start SDA at SCL signal 'H'. Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is started at SCL signal 'H'. Note)
*1 *2 *3
*1 *2 *3
In BR24A16-WM, A2 becomes P2. In BR24A08-WM, BR24A16-WM, A1 becomes P1. In BR24A04-WM, A0 becomes PS, and in BR24A08-WM and BR24A16-WM, A0 becomes P0.
1 0 1 0 A 2A 1 0 A
Fig.46 Difference of slave address of each type
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10/17
2009.08 - Rev.C
BR24A-WM series
Technical Note
Software reset Software reset is executed when to avoid malfunction after power on, and to reset during command input. Software reset has several kinds, and 3 kinds of them are shown in the figure below. (Refer to Fig.47(a), Fig.47(b), and Fig.47(c).) In dummy clock input area, release the SDA bus ('H' by pull up). In dummy clock area, ACK output and read data '0' (both 'L' level) may be output from EEPROM, therefore, if 'H' is input forcibly, output may conflict and over current may flow, leading to instantaneous power failure of system power source or influence upon devices.
Dummy clockx14 Startx2
SCL SDA
1
2
13
14
Normal command Normal command
Fig.47-(a) The case of dummy clock +START+START+ command input
Start Dummy clockx9 Start
SCL SDA
1
2
8
9
Normal command Normal command
Fig.47-(b) The case of START +9 dummy clocks +START+ command input
Startx9
SCL SDA
1
2
3
7
8
9
Normal command Normal command
Fig.47-(c) STARTx9+ command input
Start command from START input.
Acknowledge polling During internal write execution, all input commands are ignored, therefore ACK is not sent back. During internal automatic write execution after write cycle input, next command (slave address) is sent, and if the first ACK signal sends back 'L', then it means end of write action, while if it sends back 'H', it means now in writing. By use of acknowledge polling, next command can be executed without waiting for tWR = 5ms. When to write continuously, R/W = 0, when to carry out current read cycle after write, slave address R/W = 1 is sent, and if ACK signal sends back 'L', then execute word address input and data output and so forth.
During internal write, ACK = HIGH is sent back. S T O P S T Slave A R address T A C K H S T Slave A R address T A C K H
First write command
S T A R T
Write command
tWR Second write command
S T Slave A R address T A C K H S T Slave A R address T A C Word K address L A C K L A C K L S T O P
...
Data
tWR
After completion of internal write, ACK=LOW is sent back, so input next word address and data in succession.
Fig.48 Case to continuously write by acknowledge polling
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11/17
2009.08 - Rev.C
BR24A-WM series
Technical Note
WP valid timing (write cancel) WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so forth, pay attention to the following WP valid timing. During write cycle execution, in cancel valid area, by setting WP='H', write cycle can be cancelled. In both byte write cycle and page write cycle, the area from the first start condition of command to the rise of clock to taken in D0 of data(in page write cycle, the first byte data) is cancel invalid area. WP input in this area becomes Don't care. Set the setup time to rise of D0 taken SCL 100ns or more. The area from the rise of SCL to take in D0 to the end of internal automatic write (tWR) is cancel valid area. And, when it is set WP='H' during tWR, write is ended forcibly, data of address under access is not guaranteed, therefore, write it once again. (Refer to Fig.49.) After execution of forced end by WP, standby status gets in, so there is no need to wait for tWR (5ms at maximum).
Rise of D0 taken clock SCL SCL SDA D1 D0 SDA Rise of SDA
ACK
D0
ACK
Enlarged view S T Slave A address R T
Enlarged view
SDA
A C Word K address L
A C K D7 D6 D5 D4 D3 D2 D1 D0 L
A C K L
Data
A C K L
S T O P
tWR
WP cancel invalid area
WP cancel valid area
Write forced end
WP
Data is not written. Data not guaranteed
Fig.49 WP valid timing Command cancel by start condition and stop condition During command input, by continuously inputting start condition and stop condition, command can be cancelled. (Refer to Fig. 50.) However, in ACK output area and during data read, SDA bus may output 'L', and in this case, start condition and stop condition cannot be input, so reset is not available. Therefore, execute software reset. And when command is cancelled by start, stop condition, during random read cycle, sequential read cycle, or current read cycle, internal setting address is not determined, therefore, it is not possible to carry out current read cycle in succession. When to carry out read cycle in succession, carry out random read cycle.
SCL
SDA
1
0
1
0
Start condition
Stop condition
Fig.50 Case of cancel by start, stop condition during slave address input
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12/17
2009.08 - Rev.C
BR24A-WM series
Technical Note
I/O peripheral circuit Pull up resistance of SDA terminal SDA is NMOS open drain, so requires pull up resistance. As for this resistance value (RPU), select an appropriate value to this resistance value from microcontroller VIL, IL, and VOL-IOL characteristics of this IC. If RPU is large, action frequency is limited. The smaller the RPU, the larger the consumption current at action. Maximum value of RPU The maximum value of RPU is determined by the following factors. (1)SDA rise time to be determined by the capacitance (CBUS) of bus line of RPU and SDA should be tR or below. And AC timing should be satisfied even when SDA rise time is late. A (2)The bus electric potentialto be determined by input leak total (IL) of device connected to bus at output of 'H' to SDA bus and RPU should sufficiently secure the input 'H' level (VIH) of microcontroller and EEPROM including recommended noise margin 0.2VCC. Vcc - ILRPU - 0.2Vcc VIH
RPU
0.8Vcc - VIH IL
Microcontroller
RPU
BR24AXX
Ex. ) When VCC =3V, IL=10A, VIH=0.7 VCC, from (2) RPU 0.8x3- 0.7x3 10x10-6
IL
A
SDA terminal
IL
capacity CBUS CBUS
Bus line
300 [k] Minimum value of RPU The minimum value of RPU is determined by the following factors. (1)When IC outputs LOW, it should be satisfied that VOLMAX=0.4V and IOLMAX=3mA. VCC-VOL RPU IOL
RPU
Fig.51 I/O circuit diagram
VC-VOL IOL
(2)VOLMAX=0.4V should secure the input 'L' level (VIL) of microcontroller and EEPROM including recommended noise margin 0.1VCC. VOLMAX VIL-0.1 VCC Ex. ) When VCC =3V, VOL=0.4V, IOL=3mA, microcontroller, EEPROM VIL=0.3VCC from (1) 30.4 RPU 3x10 -3 867 [] And VOL = 0.4 [V] VIL = 0.3x3 = 0.9 [V] Therefore, the condition (2) is satisfied. Pull up resistance of SCL terminal When SCL control is made at CMOS output port, there is no need, but in the case there is timing where SCL becomes 'Hi-Z', add a pull up resistance. As for the pull up resistance, one of several k ~ several ten k is recommended in consideration of drive performance of output port of microcontroller. A0, A1, A2, WP process Process of device address terminals (A0,A1,A2) Check whether the set device address coincides with device address input sent from the master side or not, and select one among plural devices connected to a same bus. Connect this terminal to pull up or pull down, or VCC or GND. And, pins (N, C, PIN) not used as device address may be set to any of 'H' , 'L', and 'Hi-Z'. Types with N.C.PIN BR24A16/F/FJ -WM A0, A1, A2 BR24A08/F/FJ-WM A0, A1 BR24A04/F/FJ -WM A0 Process of WP terminal WP terminal is the terminal that prohibits and permits write in hardware manner. In 'H' status, only READ is available and WRITE of all address is prohibited. In the case of 'L', both are available. In the case of use it as an ROM, it is recommended to connect it to pull up or VCC. In the case to use both READ and WRITE, control WP terminal or connect it to pull down or GND.
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13/17
2009.08 - Rev.C
BR24A-WM series
Technical Note
Cautions on microcontroller connection Rs 2 In I C BUS, it is recommended that SDA port is of open drain input/output. However, when to use CMOS input / output of tri state to SDA port, insert a series resistance Rs between the pull up resistance Rpu and the SDA terminal of EEPROM. This is controls over current that occurs when PMOS of the microcontroller and NMOS of EEPROM are turned ON simultaneously. Rs also plays the role of protection of SDA terminal against surge. Therefore, even when SDA port is open drain input/output, Rs can be used.
EEPROM
RPU
SCL RS SDA
'H' output of microcontroller 'L' output of EEPROM
Microcontroller
Over current flows to SDA line by 'H' output of microcontroller and 'L' output of EEPROM.
Fig.52 I/O circuit diagram
Fig.53 Input / output collision timing
Maximum value of Rs The maximum value of Rs is determined by the following relations. (1)SDA rise time to be determined by the capacity (CBUS) of bus line of Rpu and SDA should be tR or below. And AC timing should be satisfied even when SDA rise time is late. A (2)The bus electric potential to be determined by Rpu and Rs the moment when EEPROM outputs 'L' to SDA bus should sufficiently secure the input 'L' level (VIL) of microcontroller including recommended noise margin 0.1VCC.
VCC RPU A RS IOL
Bus line capacity CBUS
(VCCV OL)xRS RPU+RS
VOL
+ VOL+0.1VCCVIL
RS
VIL VOL0.1VCC 1.1VCCVIL
x
R PU
Example When V CC=3V,V IL =0.3VCC,VOL=0.4V,R PU=20k,
EEPROM
VIL
Microcontroller
from(2),
R S 0.3x30.40.1x3 1.1x30.3x3 1.67k
x
20x103
Fig.54 I/O circuit diagram
Minimum value of Rs The minimum value of Rs is determined by over current at bus collision. When over current flows, noises in power source line, and instantaneous power failure of power source may occur. When allowable over current is defined as I, the following relation must be satisfied. Determine the allowable current in consideration of impedance of power source line in set and so forth. Set the over current to EEPROM 10mA or below.
VCC RS
'L' output
I VCC I
RPU RS
Over current 'H' output
RS
ExampleWhen VCC=3V, I=10mA RS 3 10x10 -3
Microcontroller
EEPROM
Fig.55 I/O circuit diagram
300
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14/17
2009.08 - Rev.C
BR24A-WM series
I2C BUS input / output circuit Input (A0,A2,SCL)
Technical Note
Fig.56 Input pin circuit diagram Input / output (SDA)
Fig.57 Input / output pin circuit diagram
Input (A1, WP)
Fig.58 Input pin circuit diagram
Notes on power ON At power on, in IC internal circuit and set, VCC rises through unstable low voltage area, and IC inside is not completely reset, and malfunction may occur. To prevent this, functions of POR circuit and LVCC circuit are equipped. To assure the action, observe the following conditions at power on. 1. Set SDA = 'H' and SCL ='L' or 'H' 2. Start power source so as to satisfy the recommended conditions of tR, tOFF, and Vbot for operating POR circuit.
VCC tR
Recommended conditions of tR, tOFF,Vbot tR
tOFF Vbot
tOFF 10ms or longer 10ms or longer
Vbot 0.3V or below 0.2V or below
10ms or below 100ms or below
0
Fig.59 Rise waveform diagram
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15/17
2009.08 - Rev.C
BR24A-WM series
Technical Note
3. Set SDA and SCL so as not to become 'Hi-Z'. When the above conditions 1 and 2 cannot be observed, take the following countermeasures. a) In the case when the above condition 1 cannot be observed. When SDA becomes 'L' at power on . Control SCL and SDA as shown below, to make SCL and SDA, 'H' and 'H'.
VCC SCL
tLOW
SDA
After Vcc becomes stable After Vcc becomes stable
tDH
tSU:DAT
tSU:DAT
Fig.60 When SCL= 'H' and SDA= 'L'
Fig.61 When SCL='L' and SDA='L'
b) In the case when the above condition 2 cannot be observed. After power source becomes stable, execute software reset(P11). c) In the case when the above conditions 1 and 2 cannot be observed. Carry out a), and then carry out b). Low voltage malfunction prevention function LVCC circuit prevents data rewrite action at low power, and prevents wrong write. At LVCC voltage (Typ. =1.2V) or below, it prevent data rewrite. VCC noise countermeasures Bypass capacitor When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is recommended to attach a by pass capacitor (0.1F) between IC VCC and GND. At that moment, attach it as close to IC as possible. And, it is also recommended to attach a bypass capacitor between board VCC and GND. Note of use (1) Described numeric values and data are design representative values, and the values are not guaranteed. (2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin in consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI. (3) Absolute maximum ratings If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded, LSI may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum ratings should not be impressed to LSI. (4)GND electric potential Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that of GND terminal. (5)Terminal design In consideration of permissible loss in actual use condition, carry out heat design with sufficient margin. (6)Terminal to terminal shortcircuit and wrong packaging When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may destruct LSI. And in the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND owing to foreign matter, LSI may be destructed. (7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently.
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16/17
2009.08 - Rev.C
BR24A-WM series
Ordering part number
Technical Note
B
Part No.
R
2
24 :I2C
4
A
A:-40 +105
0
04= 4K 16=16K 64=64K
1
02= 2K 08= 8K 32=32K
F
Package
-
W
M
E
2
BUS type
Operating Capacity temperature 01= 1K
Double cell
F : SOP8 FJ : SOP-J8 FVM : MSOP8
Packaging and forming specification E2: Embossed tape and reel TR: Embossed tape and reel
Package specifications
SOP8

5.00.2 (MAX 5.35 include BURR)
8 7 6 5
+6 4 -4
Tape Quantity
0.90.15 0.3MIN
Embossed carrier tape 2500pcs E2
The direction is the 1pin of product is at the upper left when you hold
6.20.3
4.40.2
Direction of feed
( reel on the left hand and you pull out the tape on the right hand
)
12
3
4
0.595
1.50.1
+0.1 0.17 -0.05 S
0.11
1.27 0.420.1
1pin
(Unit : mm)
Direction of feed
Reel
Order quantity needs to be multiple of the minimum quantity.
SOP-J8
4.90.2 (MAX 5.25 include BURR) +6 4 -4
8 7 6 5

Tape Quantity
0.45MIN
Embossed carrier tape 2500pcs E2
The direction is the 1pin of product is at the upper left when you hold
6.00.3
3.90.2
Direction of feed
( reel on the left hand and you pull out the tape on the right hand
)
1
2
3
4
0.545 S
0.20.1
1.3750.1
0.175
1.27 0.420.1 0.1 S
1pin (Unit : mm) Reel
Direction of feed
Order quantity needs to be multiple of the minimum quantity.
MSOP8

2.90.1 (MAX 3.25 include BURR)
8765
Tape
0.290.15 0.60.2
+6 4 -4
Embossed carrier tape 3000pcs TR
The direction is the 1pin of product is at the upper right when you hold
Quantity Direction of feed
4.00.2
2.80.1
( reel on the left hand and you pull out the tape on the right hand
1pin
)
1 234
1PIN MARK 0.475 S +0.05 0.22 -0.04 0.08 S 0.65
+0.05 0.145 -0.03
0.9MAX 0.750.05
0.080.05
Direction of feed
(Unit : mm)
Reel
Order quantity needs to be multiple of the minimum quantity.
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17/17
2009.08 - Rev.C
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
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