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| SSM9563GM P-channel Enhancement-mode Power MOSFET PRODUCT SUMMARY BVDSS R DS(ON) ID DESCRIPTION The SSM9563GM acheives fast switching performance with low gate charge without a complex drive circuit. It is suitable for low voltage applications such as DC/DC converters and general load-switching circuits. The SSM9563GM is supplied in an RoHS-compliant SO-8 package, which is widely used for medium power commercial and industrial surface mount applications. -40V 40m -6A Pb-free; RoHS-compliant SO-8 D D D D G SO-8 S S S ABSOLUTE MAXIMUM RATINGS Symbol VDS VGS ID IDM PD TSTG TJ Parameter Drain-source voltage Gate-source voltage Continuous drain current , TC = 25C TC = 70C Pulsed drain current 1 3 Value -40 25 -6 -4.8 -30 2.5 0.02 -55 to 150 -55 to 150 Units V V A A A W W/C C C Total power dissipation, TC = 25C Linear derating factor Storage temperature range Operating junction temperature range THERMAL CHARACTERISTICS Symbol RJA Parameter Maximum thermal resistance, junction-ambient 3 Value 50 Units C/W Notes: 1.Pulse width must be limited to avoid exceeding the maximum junction temperature of 150C. 2.Pulse width <300us, duty cycle <2%. 3.Mounted on a square inch of copper pad on FR4 board; 125C/W when mounted on the minimum pad area required for soldering. 9/26/2006 Rev.3.01 www.SiliconStandard.com 1 of 5 SSM9563GM ELECTRICAL CHARACTERISTICS Symbol BVDSS Parameter Drain-source breakdown voltage Breakdown voltage temperature coefficient (at Tj = 25C, unless otherwise specified) Test Conditions VGS=0V, ID=-250uA Reference to 25C, ID=-1mA VGS=-10V, ID=-6A VGS=-4.5V, ID=-4A Min. -40 -1 Typ. -0.03 10 19 5 8 12 7 68 38 1600 240 190 Max. Units 40 60 -3 -1 -25 100 30 2560 V V/C m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF BV DSS/Tj RDS(ON) Static drain-source on-resistance2 VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Gate threshold voltage Forward transconductance VDS=VGS, ID=-250uA VDS=-10V, ID=-6A Drain-source leakage current VDS=-40V, VGS=0V, Tj = 25C VDS=-32V ,VGS=0V, Tj = 70C VGS=25V ID=-6A VDS=-32V VGS=-4.5V VDS=-20V ID=-1A RG=3.3 , VGS=-10V RD=20 VGS=0V VDS=-25V f=1.0MHz Gate-source leakage current Total gate charge 2 Gate-source charge Gate-drain ("Miller") charge Turn-on delay time Rise time Turn-off delay time Fall time Input capacitance Output capacitance Reverse transfer capacitance 2 Source-Drain Diode Symbol VSD trr Qrr Parameter Forward voltage 2 Test Conditions IS=-2A, VGS=0V IS=-6A, VGS=0V, dI/dt=100A/s Min. - Typ. 37 54 Max. Units -1.2 V ns nC Reverse-recovery time 2 Reverse-recovery charge Notes: 1.Pulse width must be limited to avoid exceeding the maximum junction temperature of 150C. 2.Pulse width <300us, duty cycle <2%. 9/26/2006 Rev.3.01 www.SiliconStandard.com 2 of 5 SSM9563GM 100 90 90 T A = 25 C o -10V -7.0V -ID , Drain Current (A) 80 TA=150 C o -10V -7.0V -ID , Drain Current (A) 80 70 70 60 60 -5.0V -4.5V 50 50 -5.0V -4.5V 40 40 30 30 20 20 V G = -3.0 V 10 V G = -3.0 V 10 0 0 2 4 6 8 10 12 14 0 0 2 4 6 8 10 12 14 -V DS , Drain-to-Source Voltage (V) -V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 50 2.0 46 ID=-4A T A =25C Normalized R DS(ON) 1.8 ID=-6A V G =-10V 1.6 42 RDS(ON) (m ) 1.4 38 1.2 1.0 34 0.8 30 0.6 26 0.4 3 5 7 9 11 -50 0 50 100 150 -V GS , Gate-to-Source Voltage (V) T j , Junction Temperature ( C) o Fig 3. On-Resistance vs. Gate Voltage Fig 4. Normalized On-Resistance vs. Junction Temperature 3 6 4 2 T j =150 o C 2 T j =25 o C -VGS(th) (V) 1 0 1.4 -50 -IS(A) 0 0 0.2 0.4 0.6 0.8 1 1.2 0 50 100 150 -V SD , Source-to-Drain Voltage (V) T j , Junction Temperature ( C) o Fig 5. Forward Characteristic of Reverse Diode 9/26/2006 Rev.3.01 Fig 6. Gate Threshold Voltage vs. Junction Temperature www.SiliconStandard.com 3 of 5 SSM9563GM f=1.0MHz 12 10000 -VGS , Gate to Source Voltage (V) 10 I D = -6A V DS = -32V 8 C (pF) C iss 1000 6 4 C oss 2 C rss 0 0 10 20 30 40 50 60 70 100 1 5 9 13 17 21 25 29 Q G , Total Gate Charge (nC) -V DS , Drain-to-Source Voltage (V) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 100 1 Normalized Thermal Response (Rthja) Duty factor=0.5 0.2 10 1ms -ID (A) 0.1 0.1 0.05 1 10ms 100ms 1s 0.02 0.01 PDM 0.01 Single Pulse t T Duty factor = t/T Peak Tj = PDM x Rthja + Ta Rthja=125 C/W o 0.1 T A =25 C Single Pulse 0.01 0.1 1 10 o DC 0.001 100 0.0001 0.001 0.01 0.1 1 10 100 1000 -V DS , Drain-to-Source Voltage (V) t , Pulse Width (s) Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance VDS 90% VG QG -4.5V QGS QGD 10% VGS td(on) tr td(off) tf Charge Q Fig 11. Switching Time Waveform 9/26/2006 Rev.3.01 Fig 12. Gate Charge Waveform www.SiliconStandard.com 4 of 5 SSM9563GM PHYSICAL DIMENSIONS D SYMBOL A H E MIN 1.35 0.10 0.33 0.19 4.80 3.80 5.80 0.38 MAX 1.75 0.25 0.51 0.25 5.00 4.00 6.50 1.27 A1 B C D E e A C A1 e H L L 1.27(TYP) B All dimensions in millimeters. Dimensions do not include mold protrusions. PART MARKING PART NUMBER: 9563GM = SSM9563GM 9563GM YWWSSS DATE/LOT CODE: (YWWSSS) Y = last digit of the year WW = week SSS = lot code sequence PACKING: Moisture sensitivity level MSL3 3000 pcs in antistatic tape on a 13 inch (330mm) reel packed in a moisture barrier bag (MBB). Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, expressed or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 9/26/2006 Rev.3.01 www.SiliconStandard.com 5 of 5 |
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