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19-4858; Rev 0; 8/09
KIT ATION EVALU BLE AVAILA
+3.3V, Low-Jitter Crystal to LVPECL Clock Generator
General Description Features
Crystal Oscillator Interface: 25MHz CMOS Input: 25MHz Output Frequencies for Ethernet 62.5MHz, 125MHz, 156.25MHz, 312.5MHz Low Jitter 0.14psRMS (1.875MHz to 20MHz) 0.36psRMS (12kHz to 20MHz) Excellent Power-Supply Noise Rejection No External Loop Filter Capacitor Required
MAX3679A
The MAX3679A is a low-jitter precision clock generator with the integration of three LVPECL and one LVCMOS outputs optimized for Ethernet applications. The device integrates a crystal oscillator and a phase-locked loop (PLL) clock multiplier to generate high-frequency clock outputs for Ethernet applications. Maxim's proprietary PLL design features ultra-low jitter (0.36psRMS) and excellent power-supply noise rejection, minimizing design risk for network equipment.
Applications
Ethernet Networking Equipment
Ordering Information
PART MAX3679AETJ+ TEMP RANGE -40C to +85C PIN-PACKAGE 32 TQFN-EP*
Pin Configuration appears at end of data sheet.
+Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad.
Typical Application Circuit
+3.3V 5% 10.5 0.1F 0.1F 0.1F 0.01F 0.1F
10F
VCC VCCA 0.1F MR REF_IN IN_SEL QAC_OE QA_OE QB0_OE VCC QB1_OE BYPASS SELA1 SELA0 SELB1 SELB0 RES1 RES0 X_OUT
VCCO_A
VCCO_B
VDDO_A QA_C 125MHz QA QA 125MHz
36 Z0 = 50 ASIC
Z0 = 50 Z0 = 50 50 50
ASIC
(VCC - 2V)
MAX3679A
QB0 QB0 312.5MHz
Z0 = 50 Z0 = 50 50 50
ASIC
(VCC - 2V) QB1 QB1 X_IN GND GNDO_A 312.5MHz 50 50 (VCC - 2V) Z0 = 50 Z0 = 50 ASIC
25MHz (CL = 18pF) 33pF 27pF
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
+3.3V, Low-Jitter Crystal to LVPECL Clock Generator MAX3679A
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range VCC, VCCA, VDDO_A, VCCO_A, VCCO_B ................................-0.3V to +4.0V Voltage Range at REF_IN, IN_SEL, SELA[1:0], SELB[1:0], RES[1:0], QAC_OE, QA_OE, QB0_OE, QB1_OE, MR, BYPASS ..........................................-0.3V to (VCC + 0.3V) Voltage Range at X_IN Pin ...................................-0.3V to +1.2V Voltage Range at GNDO_A...................................-0.3V to +0.3V Voltage Range at X_OUT ............................-0.3V to (VCC - 0.6V) Current into QA_C ...........................................................50mA Current into QA, QA, QB0, QB0, QB1, QB1 .....................-56mA Continuous Power Dissipation (TA = +70C) 32-Pin TQFN (derate 34.5mW/C above +70C) .......2759mW Operating Junction Temperature Range ...........-55C to +150C Storage Temperature Range .............................-65C to +160C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.) (Notes 1, 2, and 3)
PARAMETER Power-Supply Current SYMBOL ICC (Note 4) CONDITIONS MIN TYP 77 MAX 100 UNITS mA
CONTROL INPUT CHARACTERISTICS (SELA[1:0], SELB[1:0], IN_SEL, QAC_OE, QA_OE, QB1_OE, QB0_OE, MR, BYPASS Pins) Input Capacitance Input Pulldown Resistor Input Logic Bias Resistor Input Pullup Resistor CIN RPULLDOWN Pin MR RBIAS RPULLUP Pins SELA[1:0], SELB[1:0], QB0_OE Pins QAC_OE, QA_OE, QB1_OE, IN_SEL, BYPASS VCC 1.13 VCC 1.18 VCC 1.85 VCC 1.90 0.6 200 48 40 0.72 350 50 50 VCC 1.7 2 75 50 75 pF k k k
LVPECL OUTPUT SPECIFICATIONS (QA, QA, QB0, QB0, QB1, QB1 Pins) TA = 0C to +85C Output High Voltage VOH TA = -40C to 0C TA = 0C to +85C Output Low Voltage VOL TA = -40C to 0C Peak-to-Peak Output-Voltage Swing (Single-Ended) Clock Output Rise/Fall Time Output Duty-Cycle Distortion (Note 2) 20% to 80% (Note 2) PLL enabled PLL bypassed (Note 5) VCC 0.98 VCC 0.83 VCC 0.83 VCC 1.55 V VCC 1.55 0.9 600 52 60 VP-P ps %
V
LVCMOS/LVTTL INPUT SPECIFICATIONS (SELA[1:0], SELB[1:0], IN_SEL, QAC_OE, QA_OE, QB1_OE, QB0_OE, MR, BYPASS Pins) Input-Voltage High Input-Voltage Low VIH VIL 2.0 0.8 V V
2
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+3.3V, Low-Jitter Crystal to LVPECL Clock Generator
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.) (Notes 1, 2, and 3)
PARAMETER Input High Current Input Low Current SYMBOL I IH I IL VIN = VCC VIN = 0V PLL enabled PLL bypassed VIH VIL I IH I IL VIN = VCC VIN = 0V PLL enabled -240 30 2.5 VOH VOL QA_C sourcing 12mA QA_C sinking 12mA (Notes 3, 6) PLL enabled PLL bypassed (Note 5) 250 42 40 14 625 RJRMS 12kHz to 20MHz 1.875MHz to 20MHz LVPECL output (Notes 7, 8, 9) LVPECL output LVCMOS output 0.36 0.14 5.0 -59 -47 -70 Between QB0 and QB1 Output Skew Between QA and QB0 or QB1, PECL outputs f = 1kHz f = 10kHz Clock Output SSB Phase Noise at 125MHz (Note 11) f = 100kHz f = 1MHz f > 10MHz 15 20 -124 -125 -130 -145 -153 dBc/Hz ps 1.0 MHz psRMS psP-P dBc dBc 500 50 2.6 0.4 1000 58 60 70 2.0 0.8 240 -80 25 320 CONDITIONS MIN TYP MAX 80 UNITS A A
MAX3679A
REF_IN SPECIFICATIONS (Input DC- or AC-Coupled) Reference Clock Frequency Input-Voltage High Input-Voltage Low Input High Current Input Low Current Reference Clock Duty Cycle Input Capacitance QA_C SPECIFICATIONS Output High Voltage Output Low Voltage Output Rise/Fall Time Output Duty-Cycle Distortion Output Impedance CLOCK OUTPUT AC SPECIFICATIONS VCO Frequency Range Random Jitter (Note 7) Deterministic Jitter Due to Supply Noise Spurs Induced by Power-Supply Noise (Notes 7, 9, 10) Nonharmonic and Subharmonic Spurs V V ps % MHz V V A A % pF
Note 1:
A series resistor of up to 10.5 is allowed between VCC and VCCA for filtering supply noise when system power-supply tolerance is VCC = 3.3V 5%. See Figure 2.
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+3.3V, Low-Jitter Crystal to LVPECL Clock Generator MAX3679A
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.) (Notes 1, 2, and 3) Guaranteed up to 320MHz for LVPECL output. Guaranteed up to 160MHz for LVCMOS output. All outputs enabled and unloaded. IN_SEL set high. Measured with crystal or AC-coupled, 50% duty-cycle signal on REF_IN. Measured using setup shown in Figure 1 with VCC = 3.3V 5%. Measured with crystal source. Total TIE including random and deterministic jitter. Measured with Agilent DSO81304A 40GS/s real-time oscilloscope using 2M sample record length. Note 9: Measured with 40mVP-P, 100kHz sinusoidal signal on the supply. Note 10: Measured at 156.25MHz output. Note 11: Measured with 25MHz crystal or 25MHz reference clock at LVCMOS input with a slew rate of 0.5V/ns or greater. Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8:
MAX3679A
QA_C
36
499 4.7pF
0.1F Z0 = 50
OSCILLOSCOPE
50
Figure 1. LVCMOS Output Measurement Setup
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+3.3V, Low-Jitter Crystal to LVPECL Clock Generator
Typical Operating Characteristics
(Typical values are at VCC = +3.3V, TA = +25C, crystal frequency = 25MHz.)
MAX3679A
SUPPLY CURRENT vs. TEMPERATURE
MAX3679A toc01
DIFFERENTIAL OUTPUT WAVEFORM AT 156.25MHz (LVPECL OUTPUT)
MAX3679A toc02
OUTPUT WAVEFORM AT 125MHz (LVCMOS OUTPUT)
MAX3679A toc03
250 225 200 SUPPLY CURRENT (mA) 175 150 125 100 75 50 25 0 -40 -15 10 35 60 ALL OUTPUTS ACTIVE AND UNTERMINATED ALL OUTPUTS ACTIVE AND TERMINATED
MEASURED USING 50 OSCILLOSCOPE INPUT THROUGH NETWORK SHOWN IN FIGURE 1 AMPLITUDE (200mV/div) AMPLITUDE (50mV/div)
85
1ns/div
1ns/div
AMBIENT TEMPERATURE (C)
PHASE NOISE AT 312.5MHz CLOCK FREQUENCY
MAX3679A toc04
PHASE NOISE AT 125MHz CLOCK FREQUENCY
-90 -100 -110 -120 -130 -140 -150 -160
MAX3679A toc05
-80 NOISE POWER DENSITY (dBc/Hz) -90 -100 -110 -120 -130 -140 -150 -160 0.1 1 10 100
-80 NOISE POWER DENSITY (dBc/Hz)
1000 10,000 100,000
0.1
1
10
100
1000 10,000 100,000
OFFSET FREQUENCY (kHz)
OFFSET FREQUENCY (kHz)
JITTER HISTOGRAM (312.5MHz OUTPUT, 40mVP-P SUPPLY NOISE AT 100kHz)
MAX3679A toc06
NOISE SPUR AMPLITUDE vs. NOISE FREQUENCY
-10 SPUR AMPLITUDE (dBc) -20 -30 -40 -50 -60 -70 -80 -90 10 100 1000 10,000 fC = 156.25MHz NOISE AMPLITUDE = 40mVP-P
MAX3679A toc07
0
DJ = 5.0psP-P
5ps/div
NOISE FREQUENCY (kHz)
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+3.3V, Low-Jitter Crystal to LVPECL Clock Generator MAX3679A
Pin Description
PIN 1 2, 19, 24 3 4, 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20 21, 22 23 25 26 27 28 29 30 31 32 -- NAME VCCO_B GND QB0_OE SELB1, SELB0 QAC_OE MR GNDO_A QA_C VDDO_A VCCO_A QA QA BYPASS RES1 RES0 VCCA VCC QA_OE SELA0, SELA1 QB1_OE X_OUT X_IN REF_IN IN_SEL QB1 QB1 QB0 QB0 EP Supply Ground LVCMOS/LVTTL Input. Enables/disables QB0 clock output. Connect pin high to enable LVPECL clock output QB0. Connect low to set QB0 to a logic 0. Has internal 50k input impedance. LVCMOS/LVTTL Input. Controls NB divider setting. Has 50k more information. input impedance. See Table 2 for FUNCTION Power Supply for QB0 and QB1 Clock Outputs. Connect to +3.3V.
LVCMOS/LVTTL Input. Enables/disables QA_C clock output. Connect pin high to enable QA_C. Connect low to set QA_C to a high-impedance state. Has internal 75k pullup to VCC. LVCMOS/LVTTL Input. Master reset input. Pulse high for > 1s to reset all dividers. Has internal 75k pulldown to GND. Not required for normal operation. Ground for QA_C Output. Connect to supply ground. LVCMOS Clock Output Power Supply for QA_C Clock Output. Connect to +3.3V. Power Supply for QA Clock Output. Connect to +3.3V. Noninverting Clock Output, LVPECL Inverting Clock Output, LVPECL LVCMOS/LVTTL Input (Active Low). Connect low to bypass the internal PLL. Connect high for normal operation. When in bypass mode the output dividers are set to divide by 1. Has internal 75k pullup to VCC. Not Internally Connected. Connect to GND, VCC, or leave open for normal operation. Reserved for Test. Connect to GND for normal operation. Analog Power Supply for the VCO. Connect to +3.3V. For additional power-supply noise filtering, this pin can connect to VCC through 10.5 as shown in Figure 2 (requires VCC = +3.3V 5%). Core Power Supply. Connect to +3.3V. LVCMOS/LVTTL Input. Enables/disables the QA clock output. Connect this pin high to enable the LVPECL clock output QA. Connect low to set QA to a logic 0. Has internal 75k pullup to VCC. LVCMOS/LVTTL Input. Controls NA divider setting. See Table 2 for more information. Has 50k input impedance. LVCMOS/LVTTL Input. Enables/disables QB1 clock output. Connect pin high to enable LVPECL clock output QB1. Connect low to set QB1 to a logic 0. Has internal 50k input impedance. Crystal Oscillator Output Crystal Oscillator Input LVCMOS Reference Clock Input. Self-biased to allow AC- or DC-coupling. LVCMOS/LVTTL Input. Connect high or leave open to use a crystal. Connect low to use REF_IN. Has internal 75k pullup to VCC. LVPECL, Inverting Clock Output LVPECL, Noninverting Clock Output LVPECL, Inverting Clock Output LVPECL, Noninverting Clock Output Exposed Pad. Connect to supply ground for proper electrical and thermal performance.
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+3.3V, Low-Jitter Crystal to LVPECL Clock Generator
Detailed Description
The MAX3679A is a low-jitter clock generator designed to operate at Ethernet frequencies. It consists of an onchip crystal oscillator, PLL, programmable dividers, LVCMOS output buffer, and LVPECL output buffers. Using a low-frequency clock (crystal or CMOS input) as a reference, the internal PLL generates a high-frequency output clock with excellent jitter performance.
LVCMOS Driver
QA_C, the LVCMOS output, is designed to drive a single-ended high-impedance load. The maximum operating frequency is specified up to 160MHz. This output can be disabled by the QAC_OE pin if not used and goes to a high impedance when disabled.
MAX3679A
Reset Logic/POR
During power-on, the power-on reset (POR) signal is generated to synchronize all dividers. An external master reset (MR) signal is not required.
Crystal Oscillator
An integrated oscillator provides the low-frequency reference clock for the PLL. This oscillator requires an external crystal connected between X_IN and X_OUT. Crystal frequency is 25MHz.
Applications Information
Power-Supply Filtering
The MAX3679A is a mixed analog/digital IC. The PLL contains analog circuitry susceptible to random noise. In addition to excellent on-chip power-supply noise rejection, the MAX3679A provides a separate powersupply pin, VCCA, for the VCO circuitry. Figure 2 illustrates the recommended power-supply filter network for V CCA . The purpose of this design technique is to ensure clean input power supply to the VCO circuitry and to improve the overall immunity to power-supply noise. This network requires that the power supply is +3.3V 5%. Decoupling capacitors should be used on all other supply pins for best performance.
REF_IN Buffer
An LVCMOS-compatible clock source can be connected to REF_IN to serve as the reference clock. The LVCMOS REF_IN buffer is internally biased to allow AC- or DC-coupling. It is designed to operate up to 320MHz.
PLL
The PLL takes the signal from the crystal oscillator or reference clock input and synthesizes a low-jitter, highfrequency clock. The PLL contains a phase-frequency detector (PFD), a lowpass filter, and a 625MHz voltagecontrolled oscillator (VCO). The VCO output is connected to the PFD input through a feedback divider. The PFD compares the reference frequency to the divideddown VCO output (fVCO/25) and generates a control signal that keeps the VCO locked to the reference clock. The high-frequency VCO output clock is sent to the output dividers. To minimize noise-induced jitter, the VCO supply (VCCA) is isolated from the core logic and output buffer supplies.
Output Divider Configuration
Table 2 shows the input settings required to set the output dividers. Leakage in the OPEN case must be less than 1A. Note that when the MAX3679A is in bypass mode (BYPASS set low), the output dividers are automatically set to divide by 1.
Output Dividers
The output divider is programmable to allow a range of output frequencies. See Table 2 for the divider input settings. The output dividers are automatically set to divide by 1 when the MAX3679A is in bypass mode (BYPASS = 0).
VCC
+3.3V 5%
0.1F 10.5 VCCA
LVPECL Drivers
The high-frequency outputs--QA, QB0, and QB1--are differential PECL buffers designed to drive transmission lines terminated with 50 to VCC - 2.0V. The maximum operating frequency is specified up to 320MHz. Each output can be individually disabled, if not used. The outputs go to a logic 0 when disabled.
0.1F
10F
Figure 2. Analog Supply Filtering
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+3.3V, Low-Jitter Crystal to LVPECL Clock Generator MAX3679A
Table 1. Output Frequency Determination
XO OR CMOS INPUT FREQUENCY (MHz) FEEDBACK DIVIDER, M VCO FREQUENCY (MHz) OUTPUT DIVIDER, NA AND NB /2 25 25 625 /4 /5 /10 OUTPUT FREQUENCY (MHz) 312.5 156.25 125 62.5 Ethernet APPLICATIONS
Table 2. Output Divider Configuration
INPUT SELA1/SELB1 0 1 1 0 SELA0/SELB0 0 0 1 OPEN NA/NB DIVIDER /2* /4 /5 /10
Table 3. Crystal Selection Parameters
PARAMETER Crystal Oscillation Frequency Shunt Capacitance Load Capacitance Equivalent Series Resistance (ESR) Maximum Crystal Drive Level SYMBOL f OSC CO CL RS MIN TYP 25 2.0 18 50 300 W 7.0 MAX UNITS MHz pF pF
*Maximum guaranteed output frequency is 160MHz for CMOS and 320MHz for LVPECL output.
27pF X_IN 25MHz CRYSTAL (CL = 18pF) X_OUT 33pF
Figure 4. Crystal, Capacitors Connection
Crystal Input Layout and Frequency Stability
The crystal, trace, and two external capacitors should be placed on the board as close as possible to the MAX3679A's X_IN and X_OUT pins to reduce crosstalk of active signals into the oscillator. The layout shown in Figure 3 gives approximately 3pF of trace plus footprint capacitors per side of the crystal (Y1). The dielectric material is FR4 and dielectric thickness of the reference board is 15 mils. Using a 25MHz crystal and the capacitor values of C22 = 27pF and C23 = 33pF, the measured output frequency accuracy is -14ppm at +25C ambient temperature.
Figure 3. Crystal Layout
Crystal Selection
The crystal oscillator is designed to drive a fundamental mode, AT-cut crystal resonator. See Table 3 for recommended crystal specifications. See Figure 4 for external capacitance connection.
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+3.3V, Low-Jitter Crystal to LVPECL Clock Generator
Interfacing with LVPECL Outputs
The equivalent LVPECL output circuit is given in Figure 8. These outputs are designed to drive a pair of 50 transmission lines terminated with 50 to VTT = VCC - 2V. If a separate termination voltage (VTT) is not available, other termination methods can be used such as shown in Figures 5 and 6. Unused outputs should be disabled and can be left open. For more information on LVPECL terminations and how to interface with other logic families, refer to Application Note 291: HFAN-01.0: Introduction to LVDS, PECL, and CML.
MAX3679A
+3.3V
Interface Models
Figures 7, 8, and 9 show examples of interface models.
130 VCC HIGH IMPEDANCE 82
130
MAX3679A Qx
Qx
Z0 = 50 Z0 = 50 82
Qx
Figure 5. Thevenin Equivalent of Standard PECL Termination
Qx Z0 = 50 100 0.1F Qx 150 150 Z0 = 50 HIGH IMPEDANCE ESD STRUCTURES
0.1F Qx
MAX3679A
Figure 8. Simplified LVPECL Output Circuit Schematic
NOTE: AC-COUPLING IS OPTIONAL.
Figure 6. AC-Coupled PECL Termination
VDDO_A VCC
DISABLE
VB = 1.4V 10 IN 14.5k 10 REF_IN VB QA_C
VCC
VB
ESD STRUCTURES ESD STRUCTURES
Figure 7. Simplified REF_IN Pin Circuit Schematic
Figure 9. Simplified LVCMOS Output Circuit Schematic
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+3.3V, Low-Jitter Crystal to LVPECL Clock Generator MAX3679A
Layout Considerations
The inputs and outputs are critical paths for the MAX3679A, and care should be taken to minimize discontinuities on these transmission line. Here are some suggestions for maximizing the MAX3679A's performance: * An uninterrupted ground plane should be positioned beneath the clock I/Os. * Ground pin vias should be placed close to the IC and the input/output interfaces to allow a return current path to the MAX3679A and the receive devices. * Supply decoupling capacitors should be placed close to the MAX3679A supply pins. * Maintain 100 differential (or 50 single-ended) transmission line impedance out of the MAX3679A. * Use good high-frequency layout techniques and a multilayer board with an uninterrupted ground plane to minimize EMI and crosstalk. Refer to the MAX3679A Evaluation Kit for more information.
TOP VIEW
Pin Configuration
REF_IN IN_SEL X_IN 26 QB0 QB0 QB1 QB1 X_OUT 25 24 GND QB1_OE SELA1 SELA0 QA_OE GND VCC VCCA 23 22 21 20 19 *EP 18 17 9 QA_C 10 VDDO_A 11 VCCO_A 12 QA 13 QA 14 BYPASS 15 RES1 16 RES0
32 VCCO_B GND QB0_OE SELB1 SELB0 QAC_OE MR GNDO_A 1 2 3 4 5 6 7 8
31
30
29
28
27
+
MAX3679A
Exposed-Pad Package
The exposed pad on the 32-pin TQFN package provides a very low inductance path for return current traveling to the PCB ground plane. The pad is also electrical ground on the MAX3679A and must be soldered to the circuit board ground for proper electrical performance.
THIN QFN (5mm x 5mm)
*EXPOSED PAD CONNECTED TO GROUND.
Chip Information
TRANSISTOR COUNT: 10,780 PROCESS: BiCMOS
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+3.3V, Low-Jitter Crystal to LVPECL Clock Generator
Block Diagram
IN_SEL BYPASS SELA[1:0]
MAX3679A
QAC_OE LVCMOS BUFFER DIVIDER NA LVPECL BUFFER LVCMOS REF_IN 27pF X_IN 25MHz X_OUT 33pF DIVIDERS: NA = 2, 4, 5, 10 NB = 2, 4, 5, 10 LVPECL BUFFER QB0 QB0 CRYSTAL OSCILLATOR /25 DIVIDER NB 1 0 PFD FILTER 625MHz VCO 1 LVPECL BUFFER QB1_OE QB1 QB1 QB0_OE 0
QA_C
QA_OE QA QA
MAX3679A
SELB[1:0]
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 32 TQFN-EP PACKAGE CODE T3255+3 DOCUMENT NO. 21-0140
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11
(c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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