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Ultralow Noise Amplifier at Lower Power ADA4075-2
FEATURES
Ultralow noise: 2.8 nV/Hz at 1 kHz typical Ultralow distortion: 0.0002% typical Low supply current: 1.8 mA per amplifier typical Offset voltage: 1 mV maximum Bandwidth: 6.5 MHz typical Slew rate: 12 V/s typical Unity-gain stable Extended industrial temperature range SOIC package
PIN CONFIGURATION
OUTA 1 -INA 2 +INA 3
8
V+
Figure 1. 8-Lead SOIC
APPLICATIONS
Precision instrumentation Professional audio Active filters Low noise amplifier front end Integrators
GENERAL DESCRIPTION
The ADA4075-2 is a dual, high performance, low noise operational amplifier combining excellent dc and ac characteristics on the Analog Devices, Inc., iPolar(R) process. The iPolar process is an advanced bipolar technology implementing vertical junction isolation with lateral trench isolation. This allows for low noise performance amplifiers in smaller die size at faster speed and lower power. Its high slew rate, low distortion, and ultralow noise make the ADA4075-2 ideal for high fidelity audio and high performance instrumentation applications. It is also especially useful for lower power demands, small enclosures, and high density applications. The ADA4075-2 is specified for the temperature range of -40C to +125C and is available in a standard SOIC package.
Table 1. Low Noise Precision Op Amps
Supply Single 44 V OP27 36 V AD8671 AD8675 AD797 AD8672 AD8676 AD8599 ADA4004-4 AD8674 12 V to 16 V AD8665 OP162 AD8666 OP262 AD8668 OP462 5V AD8605 AD8655 AD8691 AD8606 AD8656 AD8692 AD8608 AD8694
Dual
OP275
Quad
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved.
07642-001
OUTB TOP VIEW 6 -INB (Not to Scale) 5 +INB V- 4
7
ADA4075-2
ADA4075-2 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Pin Configurations ........................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 4 Thermal Resistance ...................................................................... 4 Power Sequencing ........................................................................ 4 ESD Caution .................................................................................. 4 Typical Performance Characteristics ............................................. 5 Applications Information .............................................................. 15 Input Protection ......................................................................... 15 Total Harmonic Distortion ....................................................... 15 Phase Reversal ............................................................................ 15 DAC Output Filter...................................................................... 16 Balanced Line Driver ................................................................. 17 Balanced Line Receiver.............................................................. 18 Low Noise Parametric Equalizer .............................................. 19 Schematic ......................................................................................... 20 Outline Dimensions ....................................................................... 21 Ordering Guide .......................................................................... 21
REVISION HISTORY
10/08--Revision 0: Initial Version
Rev. 0 | Page 2 of 24
ADA4075-2 SPECIFICATIONS
VSY = 15 V, VCM = 0 V, TA = 25C, unless otherwise noted. Table 2.
Parameter INPUT CHARACTERISTICS Offset Voltage Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Ratio Large-Signal Voltage Gain Symbol VOS -40C TA +125C IB -40C TA +125C IOS -40C TA +125C -40C TA +125C VCM = -12.5 V to +12.5 V -40C TA +125C RL = 2 k, VO = -11 V to +11 V -40C TA +125C RL = 600 , VO = -10 V to +10 V -40C TA +125C -40C TA +125C -12.5 110 106 114 108 112 106 5 30 Conditions Min Typ 0.2 Max 1 1.2 100 150 50 75 +12.5 Unit mV mV nA nA nA nA V dB dB dB dB dB dB V/C M pF pF V V V V V V V V V V V V mA dB dB mA mA V/s s MHz Degrees % nV p-p nV/Hz pA/Hz
CMRR AVO
118 117 117 0.3 40 2.4 2.1
Offset Voltage Drift Input Resistance Input Capacitance, Differential Mode Input Capacitance, Common Mode OUTPUT CHARACTERISTICS Output Voltage High
VOS/T RIN CINDM CINCM VOH
Output Voltage Low
VOL
RL = 2 k to GND -40C TA +125C RL = 600 to GND -40C TA +125C VSY = 18 V, RL = 600 to GND -40C TA +125C RL = 2 k to GND -40C TA +125C RL = 600 to GND -40C TA +125C VSY = 18 V, RL = 600 to GND -40C TA +125C f = 100 kHz, AV = 1 VSY = 4.5 V to 18 V -40C TA +125C VSY = 4.5 V to 18 V, IO = 0 mA -40C TA +125C RL = 2 k, AV = 1 To 0.01%, VIN = 10 V step, RL = 1 k RL = 1 M, CL = 35 pF, AV = 1 RL = 1 M, CL = 35 pF, AV = 1 RL = 2 k, AV = 1, VIN = 3 V rms, f = 20 Hz to 20 kHz f = 0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz
Rev. 0 | Page 3 of 24
12.8 12.5 12.4 12 15.4 15
13 12.8 15.8 -14 -13.6 -16.6 40 0.3 -13.6 -13 -13 -12.5 -16 -15.5
Short-Circuit Current Closed-Loop Output Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current per Amplifier DYNAMIC PERFORMANCE Slew Rate Settling Time Gain Bandwidth Product Phase Margin THD + NOISE Total Harmonic Distortion and Noise NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density
ISC ZOUT PSRR ISY
106 100
110 1.8 2.25 3.35
SR tS GBP M THD + N en p-p en in
12 3 6.5 60 0.0002 60 2.8 1.2
ADA4075-2 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Supply Voltage Input Voltage Input Current1 Differential Input Voltage Output Short-Circuit Duration to GND Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature (Soldering, 60 sec)
1
THERMAL RESISTANCE
Rating 20 V VSY 10 mA 1 V Indefinite -65C to +150C -40C to +125C -65C to +150C 300C
JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. This was measured using a standard 2-layer board. Table 3. Thermal Resistance
Package Type 8-Lead SOIC JA 158 JC 43 Unit C/W
POWER SEQUENCING
The op amp supplies must be established simultaneously with, or before, any input signals are applied. If this is not possible, the input current must be limited to 10 mA.
The input pins have clamp diodes to the power supply pins.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Rev. 0 | Page 4 of 24
ADA4075-2 TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25C, unless otherwise noted.
250 VSY = 15V VCM = 0V
250
VSY = 5V VCM = 0V
200
200
NUMBER OF AMPLIFIERS
NUMBER OF AMPLIFIERS
150
150
100
100
50
50
07642-003
-0.5
0 VOS (mV)
0.5
1.0
-0.5
0 VOS (mV)
0.5
1.0
Figure 2. Input Offset Voltage Distribution
Figure 5. Input Offset Voltage Distribution
70 60
VSY = 15V -40C TA +125C
80 70
VSY = 5V -40C TA +125C
NUMBER OF AMPLIFIERS
50 40 30 20 10 0 -2.0
NUMBER OF AMPLIFIERS
60 50 40 30 20 10 0 -2.0
07642-004
-1.6
-1.2
-0.8
-0.4
0
0.4
0.8
1.2
1.6
2.0
TCVOS (V/C)
TCVOS (V/C)
Figure 3. Input Offset Voltage Drift Distribution
Figure 6. Input Offset Voltage Drift Distribution
300
VSY = 15V
300
VSY = 5V
200
200
100
100
VOS (V)
0
VOS (V)
0
-100
-100
-200
-200
07642-005
-4
-3
-2
-1
0 VCM (V)
1
2
3
4
5
VCM (V)
Figure 4. Input Offset Voltage vs. Common-Mode Voltage
Figure 7. Input Offset Voltage vs. Common-Mode Voltage
Rev. 0 | Page 5 of 24
07642-008
-300 -15
-10
-5
0
5
10
15
-300 -5
07642-007
-1.6
-1.2
-0.8
-0.4
0
0.4
0.8
1.2
1.6
2.0
07642-006
0 -1.0
0 -1.0
ADA4075-2
80 VSY = 15V
100 VSY = 5V 80
60
60
40
IB (nA)
40 20 0 -40
IB (nA)
20
TEMPERATURE (C)
TEMPERATURE (C)
Figure 8. Input Bias Current vs. Temperature
Figure 11. Input Bias Current vs. Temperature
60 VSY = 15V 50
60 VSY = 5V 50
40
40
IB (nA)
30
IB (nA)
30
20
20
10
10
VCM (V)
VCM (V)
Figure 9. Input Bias Current vs. Input Common-Mode Voltage
Figure 12. Input Bias Current vs. Input Common-Mode Voltage
10
VSY = 15V
10
VSY = 5V
OUTPUT VOLTAGE TO SUPPLY RAIL (V)
VCC - VOH 1 VOL - VEE
OUTPUT VOLTAGE TO SUPPLY RAIL (V)
VCC - VOH 1 VOL - VEE
0.01
0.1
1
10
100
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 10. Output Voltage to Supply Rail vs. Load Current
Figure 13. Output Voltage to Supply Rail vs. Load Current
Rev. 0 | Page 6 of 24
07642-013
0.01
0.1
1
10
100
07642-010
0.1 0.001
0.1 0.001
07642-049
-10
-5
0
5
10
15
07642-047
0 -15
0 -4
-3
-2
-1
0
1
2
3
4
07642-012
07642-009
0 -40
-25
-10
5
20
35
50
65
80
95
110
125
-25
-10
5
20
35
50
65
80
95
110
125
ADA4075-2
2.5
OUTPUT VOLTAGE TO SUPPLY RAIL (V)
2.0
VCC - VOH
OUTPUT VOLTAGE TO SUPPLY RAIL (V)
VSY = 15V RL = 2k
2.0 VCC - VOH
VSY = 5V RL = 2k
1.5
1.5
1.0
VOL - VEE
1.0
VOL - VEE
0.5
0.5
TEMPERATURE (C)
TEMPERATURE (C)
Figure 14. Output Voltage to Supply Rail vs. Temperature
Figure 17. Output Voltage to Supply Rail vs. Temperature
140 120 100 80 60 PHASE
VSY = 15V
140 120 100 80 60
140 120 100 80 60
PHASE (Degrees)
GAIN (dB)
VSY = 5V PHASE
140 120 100 80
GAIN
60 40 20 0 -20 -40 -60 -80
PHASE (Degrees)
07642-019 07642-018
GAIN (dB)
40 20 0 -20 -40 -60 -80 -100 1k 10k 100k 1M 10M GAIN
40 20 0 -20 -40 -60 -80
40 20 0 -20 -40 -60 -80
07642-015
-100 100M
-100 1k
10k
100k
1M
10M
-100 100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 15. Open-Loop Gain and Phase vs. Frequency
Figure 18. Open-Loop Gain and Phase vs. Frequency
50 40 30 20
AV = +100
VSY = 15V 15V
50 40 30
AV = +100
VSY = 5V 15V
AV = +10
GAIN (dB)
20 10 0 -10 -20
AV = +10
GAIN (dB)
10 0 -10 -20 -30 1k
AV = +1
AV = +1
07642-016
10k
100k
1M
10M
100M
-30 1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 16. Closed-Loop Gain vs. Frequency
Figure 19. Closed-Loop Gain vs. Frequency
Rev. 0 | Page 7 of 24
07642-014
-25
-10
5
20
35
50
65
80
95
110
125
07642-011
0 -40
0 -40
-25
-10
5
20
35
50
65
80
95
110
125
ADA4075-2
1k VSY = 15V
AV = +10
1k
VSY = 5V
AV = +10
100
100
10
AV = +100 AV = +1
10
AV = +100 AV = +1
ZOUT ()
1
ZOUT ()
10M
07642-017
1
0.1
0.1
0.01
0.01
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 20. Output Impedance vs. Frequency
Figure 23. Output Impedance vs. Frequency
140 120 100
VSY = 15V
140 120 100
VSY = 5V
CMRR (dB)
80 60 40 20 0 100
CMRR (dB)
80 60 40 20 0 100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 21. CMRR vs. Frequency
Figure 24. CMRR vs. Frequency
120 100 80
VSY = 15V
120
VSY = 5V
100 80
PSRR (dB)
PSRR (dB)
60 PSRR+ 40 20 0 -20 10
PSRR-
60
PSRR+ PSRR-
40 20 0 -20 10
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 22. PSRR vs. Frequency
Figure 25. PSRR vs. Frequency
Rev. 0 | Page 8 of 24
07642-025
100
1k
10k
100k
1M
10M
100M
07642-022
07642-024
1k
10k
100k
1M
10M
07642-021
07642-020
0.001 10
100
1k
10k
100k
1M
0.001 10
ADA4075-2
40 35 30
40
VSY = 15V AV = +1 RL = 2k
35 30
OVERSHOOT (%)
VSY = 5V AV = +1 RL = 2k
OVERSHOOT (%)
25 20 15 10 5 0 10
25 20 15 10 5 0 10
07642-023
100 CAPACITANCE (pF)
1000
100 CAPACITANCE (pF)
1000
Figure 26. Small-Signal Overshoot vs. Load Capacitance
Figure 29. Small-Signal Overshoot vs. Load Capacitance
VSY = 15V VIN = 20V p-p AV = +1 RL = 2k CL = 100pF
AMPLITUDE (2V/DIV) VOLTAGE (5V/DIV)
VSY = 5V VIN = 7V p-p AV = +1 RL = 2k CL = 100pF
0V
0V
07642-027
TIME (4s/DIV)
TIME (4s/DIV)
Figure 27. Large-Signal Transient Response
Figure 30. Large-Signal Transient Response
VOLTAGE (20mV/DIV)
VSY = 15V VIN = 100mV p-p AV = +1 RL = 2k CL = 100pF
VOLTAGE (20mV/DIV)
0V
VSY = 5V VIN = 100mV p-p AV = +1 RL = 2k CL = 100pF
0V
07642-028
TIME (10s/DIV)
TIME (10s/DIV)
Figure 28. Small-Signal Transient Response
Figure 31. Small-Signal Transient Response
Rev. 0 | Page 9 of 24
07642-031
07642-030
07642-026
ADA4075-2
4 VSY = 15V 2 0 INPUT
4 VSY = 5V 2 0 INPUT
OUTPUT VOLTAGE (V)
OUTPUT
0 -5 -10 -15
OUTPUT
0 -2 -4 -6
07642-029
TIME (1s/DIV)
-20
TIME (1s/DIV)
-8
Figure 32. Negative Overload Recovery
Figure 35. Negative Overload Recovery
4 VSY = 15V 2 0 INPUT
4 VSY = 5V 2 0 OUTPUT VOLTAGE (V) INPUT
-2 15 10 5 OUTPUT 0 -5
-2
4 2 OUTPUT 0 -2
07642-033
TIME (1s/DIV)
-10
TIME (1s/DIV)
-4
Figure 33. Positive Overload Recovery
Figure 36. Positive Overload Recovery
INPUT
VSY = 15V
INPUT
VSY = 5V
VOLTAGE (5V/DIV)
VOLTAGE (5V/DIV)
OUTPUT ERROR BAND
+10mV
+6mV
OUTPUT
0V
0V
ERROR BAND
-10mV
07642-061
-6mV
07642-062
TIME (2s/DIV)
TIME (2s/DIV)
Figure 34. Positive Settling Time to 0.01%
Figure 37. Positive Settling Time to 0.01%
Rev. 0 | Page 10 of 24
07642-034
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
07642-032
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
ADA4075-2
VSY = 15V
VSY = 5V
INPUT
VOLTAGE (5V/DIV)
VOLTAGE (5V/DIV)
INPUT
+10mV
+6mV
OUTPUT
0V
ERROR BAND
OUTPUT
0V
ERROR BAND
-10mV
07642-064
-6mV
07642-063
TIME (2s/DIV)
TIME (2s/DIV)
Figure 38. Negative Settling Time to 0.01%
Figure 41. Negative Settling Time to 0.01%
10
VSY = 15V
10
VSY = 5V
VOLTAGE NOISE DENSITY (nV/Hz)
07642-035
1
10
100
1k
10k
100k
1
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 39. Voltage Noise Density
Figure 42. Voltage Noise Density
10
VSY = 15V
RS1
10
VSY = 5V
RS1
CURRENT NOISE DENSITY (pA/Hz)
RS2 UNCORRELATED RS1 = 0 1
CURRENT NOISE DENSITY (pA/Hz)
RS2 UNCORRELATED RS1 = 0 1
CORRELATED RS1 = RS2
CORRELATED RS1 = RS2
07642-045
1
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 40. Current Noise Density
Figure 43. Current Noise Density
Rev. 0 | Page 11 of 24
07642-046
0.1
1
10
100
1k
10k
100k
0.1
07642-038
1
VOLTAGE NOISE DENSITY (nV/Hz)
1
ADA4075-2
VSY = 15V VSY = 5V
INPUT NOISE VOLTAGE (10nV/DIV)
07642-036
INPUT NOISE VOLTAGE (10nV/DIV)
TIME (1s/DIV)
TIME (1s/DIV)
Figure 44. 0.1 Hz to 10 Hz Noise
Figure 47. 0.1 Hz to 10 Hz Noise
8
6
5 +125C +85C 4 +25C -40C
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
6
VSY = 15V 4 VSY = 5V
3
2
2
1
4
6
8
10
12
14
16
18
SUPPLY VOLTAGE (V)
07642-048
-25
-10
5
20
35
50
65
80
95
110
125
TEMPERATURE (C)
Figure 45. Supply Current vs. Supply Voltage
Figure 48. Supply Current vs. Temperature
0 -20
VSY = 15V VIN = 10V p-p RL = 2k
0 -20
VSY = 5V VIN = 5V p-p RL = 2k
CHANNEL SEPARATION (dB)
-40 -60 -80 -100 -120 -140 100
CHANNEL SEPARATION (dB)
-40 -60 -80 -100 -120 -140 100
1k
10k FREQUENCY (Hz)
100k
FREQUENCY (Hz)
Figure 46. Channel Separation vs. Frequency
Figure 49. Channel Separation vs. Frequency
Rev. 0 | Page 12 of 24
07642-044
1k
10k
100k
07642-041
07642-057
0
0 -40
07642-039
ADA4075-2
10 VSY = 15V f = 1kHz 10 VSY = 5V f = 1kHz
1
1
THD + NOISE (%)
0.01
THD + NOISE (%)
0.1
0.1
0.01
0.001 600 0.0001 2k
0.001
600
0.0001 2k 10 0.001 0.01 0.1 1 10
07642-065
07642-059 07642-067
0.001
0.01
0.1
1
AMPLITUDE (V rms)
07642-058
0.00001 0.0001
0.00001 0.0001
AMPLITUDE (V rms)
Figure 50. THD + Noise vs. Amplitude
Figure 53. THD + Noise vs. Amplitude
1
VSY = 15V VIN = 3V rms
1
VSY = 5V VIN = 1.5V rms
0.1
THD + NOISE (%) THD + NOISE (%)
0.1
0.01
0.01
600
0.001
600
0.001 2k 2k
07642-060
0.0001 10
100
1k FREQUENCY (Hz)
10k
100k
0.0001 10
100
1k FREQUENCY (Hz)
10k
100k
Figure 51. THD + Noise vs. Frequency
Figure 54. THD + Noise vs. Frequency
10
VSY = 18V f = 1kHz
1
VSY = 18V VIN = 8V rms
1
0.1
THD + NOISE (%)
THD + NOISE (%)
0.1
0.01
0.01
0.001 600 0.0001
0.001 600 0.0001 2k 0.001 0.01 0.1 1 10 100
07642-056
2k
0.00001 0.0001
0.00001
10
100
1k FREQUENCY (Hz)
10k
100k
AMPLITUDE (V rms)
Figure 52. THD + Noise vs. Amplitude
Figure 55. THD + Noise vs. Frequency
Rev. 0 | Page 13 of 24
ADA4075-2
2.5
OUTPUT VOLTAGE TO SUPPLY RAIL (V) OUTPUT VOLTAGE TO SUPPLY RAIL (V)
VSY = 18V RL = 2k VCC - VOH
10
VSY = 18V VCC - VOH
2.0
1.5
1
VOL - VEE
1.0
VOL - VEE
0.5
07642-066
-25
-10
5
20
35
50
65
80
95
110
125
0.01
0.1
1
10
100
TEMPERATURE (C)
LOAD CURRENT (mA)
Figure 56. Output Voltage to Supply Rail vs. Temperature
Figure 57. Output Voltage to Supply Rail vs. Load Current
Rev. 0 | Page 14 of 24
07642-068
0 -40
0.1 0.001
ADA4075-2 APPLICATIONS INFORMATION
INPUT PROTECTION
The maximum differential input voltage that can be applied to the ADA4075-2 is determined by the internal diodes connected across its inputs. These diodes limit the maximum differential input voltage to 1 V and are needed to prevent base-emitter junction breakdown from occurring in the input stage of the ADA4075-2 when very large differential voltages are applied. To make sure that the ultralow voltage noise feature of the ADA4075-2 is preserved, the commonly used internal resistors in series with the inputs were not used to limit the current in the diodes. In small-signal applications, this is not an issue; however, in applications where large differential voltages can be inadvertently applied to the device, large currents may flow through these diodes. If the differential voltage of the ADA4075-2 exceeds 1 V, external resistors should be used at both inputs of the op amp to limit the input currents to less than 10 mA (see Figure 58). However, when series resistors are added, the total voltage noise degrades because the resistors may have a thermal noise that is greater than the voltage noise of the op amp itself. For example, a 1 k resistor at room temperature has a thermal noise of 4 nV/Hz, whereas the ADA4075-2 has an ultralow voltage noise of only 2.8 nV/Hz typical.
ADA4075-2
R1 2 1 R2 3
07642-050
1
0.1
THD + NOISE (%)
0.01
VSY = 4V RL = 2k VIN = 1.5V rms VSY = 15V RL = 2k VIN = 3V rms
0.001
100
1k FREQUENCY (Hz)
10k
100k
Figure 59. THD + Noise vs. Frequency
PHASE REVERSAL
Phase reversal occurs in some amplifiers when the input common-mode voltage range is exceeded. When the voltage driving the input to these amplifiers exceeds the maximum input common-mode voltage range, the output of the amplifiers changes polarity. Phase reversal can cause permanent damage to the amplifier as well as system lockups in feedback loops. The ADA4075-2 amplifiers have been carefully designed to prevent output phase reversal when both inputs are maintained within the specified input voltage range. If one or both inputs exceed the input voltage range but remain within the supply rails, the output is capped at the maximum output that it can swing to. For a supply voltage of 15 V and a load resistance of 2 k, the output is capped at 13 V typical when the input voltage exceeds the input voltage range but stays within the supply rails. Figure 60 shows the output voltage of the AD4075-2 configured as a unitygain buffer with a supply voltage of 15 V.
VIN VSY = 15V
Figure 58. Input Protection
TOTAL HARMONIC DISTORTION
The total harmonic distortion + noise (THD + N) of the ADA4075-2 is 0.0002% typical with a load resistance of 2 k. Figure 59 shows the performance of the ADA4075-2 driving a 2 k load with supply voltages of 4 V and 15 V. Notice that there is more distortion for the supply voltage of 4 V than for a supply voltage of 15 V. Thus, it is very important to operate the ADA4075-2 at a supply voltage greater than 5 V for optimum distortion. The THD + noise graphs for supply voltages of 5 V and 18 V are available in Figure 54 and Figure 55.
VOUT
VOLTAGE (5V/DIV)
TIME (40s/DIV)
Figure 60. No Phase Reversal
Rev. 0 | Page 15 of 24
07642-053
07642-069
0.0001 10
ADA4075-2
DAC OUTPUT FILTER
The ultralow voltage noise, low distortion, and high slew rate of the ADA4075-2 make it an ideal choice for professional audio signal processing. Figure 61 shows the ADA4075-2 used in a typical audio DAC output filter configuration. The differential outputs of the DAC are fed into the ADA4075-2. The ADA4075-2 is configured as a differential Sallen-key filter. It operates as an external low-pass filter to remove high frequency noise present
11k 68pF DAC OUTN DAC OUTP 11k 5.62k 560pF 5.62k 3.01k 1.5k 270pF 1/2 100 47F
on the output pins of the DAC. It also provides differential-tosingle-ended conversion from the differential outputs of the DAC. For a DAC output filter, an op amp with reasonable slew rate and bandwidth is required. The slew rate of the ADA4075-2 is at a high 12 V/s, and the bandwidth is 6.5 MHz. The cutoff frequency of the low-pass filter is approximately 167 kHz. In addition, the 100 k and 47 F RC network perform ac coupling to block out the dc components at the output.
+
OUTPUT 100k
07642-054
ADA4075-2
150pF
2.2nF
Figure 61. Typical DAC Output Filter Circuit (Differential)
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ADA4075-2
BALANCED LINE DRIVER
The circuit of Figure 62 shows a balanced line driver designed for audio use. Such drivers are intended to mimic an output transformer in operation, whereby the common-mode voltage can be impressed by the load. Furthermore, either output can be shorted to ground in single-ended applications without affecting the overall operation. Circuits of this type use positive and negative feedback to obtain a high common-mode output impedance, and they are somewhat notorious for component sensitivity and susceptibility to latch-up. This circuit uses several techniques to avoid spurious behavior. First, the 4-op-amp arrangement ensures that the input impedance is load independent (the input impedance can become negative with some configurations). Note that the output op amps are packaged with the input op amps to maximize drive capability. Second, the positive feedback is ac-coupled by C2 and C3, which eliminates the need for offset trim. Because the circuit is ac-coupled at the input, these capacitors do not have significant dc voltage across them, thus tantalum types of capacitors can be used. Finally, even with these precautions, it is vital that the positive feedback be accurately controlled. This is partly achieved by using 1% resistors. In addition, the following setup procedure ensures that the positive feedback does not become excessive: 1. Set R11 to its mid position (or short the ends together, whichever is easier), and temporarily short the negative output to ground. Apply a 10 V p-p sine wave at approximately 1 kHz to the input, and adjust R7 to provide 930 mV p-p at the point marked "test." Remove the short from the negative output (and across R11, if used), and adjust R11 until the output waveforms are symmetric.
2.
3.
The overall gain of the driver is equal to 2, which provides an extra 6 dB of headroom in balanced differential mode. The output noise is about -109 dBV in a 20 kHz bandwidth.
C5 IN C1 10F R1 10k R4 A1 1/2 4.7k 50pF R5 4.7k A2 1/2 R13 100 OUT+
ADA4075-2
R7 250
ADA4075-2
R2 4.7k C4 50pF R3 4.7k A3 1/2 R6 R8 R9
4.7k FEEDBACK TRIM
100 4.7k
R10 4.7k
SYMMETRY TRIM R12 R11 250 4.7k C6 50pF A4
TEST
C2 10F
C3 10F
ADA4075-2
R15 4.7k
1/2
R14 100
OUT-
ADA4075-2
R16 100 R17 4.7k
07642-073
NOTES 1. ALL RESISTORS SHOULD HAVE 1% TOLERANCE. 2. A1/A2 IN SAME PACKAGE; A3/A4 IN SAME PACKAGE.
Figure 62. Balanced Line Driver
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ADA4075-2
BALANCED LINE RECEIVER
Figure 63 depicts a unity-gain balanced line receiver capable of a high degree of hum rejection. The CMRR is approximately given by
R1R4 20 log 10 R2R3 Therefore, R1 to R4 should be close-tolerance components to obtain the best possible CMRR without adjustment. The presence of A2 ensures that the impedances are symmetric at the two inputs (unlike many other designs), and, as a bonus, A2 also provides a
C2 50pF R3 10k
complementary output. A3 raises the common-mode input impedance from about 7.5 k to about 70 k, reducing the degradation of CMRR due to mismatches in source impedance. It should be noted that A3 is not in the signal path, and almost any op amp will work well here. Although it may seem as though the inverting output should be noisier than the noninverting one, they are in fact symmetric at about -111 dBV (20 kHz bandwidth). Sometimes an overall gain of 1/2 is desired to provide an extra 6 dB of differential input headroom. This can be attained by reducing R3 and R4 to 5 k and increasing R9 to 22 k.
C3 50pF R6
OUT+
IN- IN+ R7 5.6k R2 5k R8 5.6k
R1 5k
A1 1/2
R5 5k
5k A2 1/2 OUT-
ADA4075-2
R4 10k
ADA4075-2
C1 22F (NON-POLAR)
A3*
R9 11k
R10 11k
07642-071
*A3 REDUCES THE DEGRADATION OF CMRR (SEE THE BALANCED LINE RECEIVER SECTION FOR MORE DETAILS).
Figure 63. Balanced Line Receiver
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ADA4075-2
LOW NOISE PARAMETRIC EQUALIZER
The circuit of Figure 64 is a reciprocal parametric equalizer yielding 20 dB of cut or boost with variable bandwidth and frequency. The frequency control range is 6.9:1, with the geometric mean center frequency conveniently occurring at the midpoint of the potentiometer setting. The center frequency is equal to
47F IN 6.2k 6.2k
48 Hz/Ct, where Ct is the value of C1 and C2 in microfarads. The bandwidth control adjusts the Q from 0.9 to about 11. The overall noise is setting dependent, but with all controls centered it is about -104 dBV in a 20 kHz bandwidth. Such a low noise level can obviate the need for a bypass switch in many applications.
OUT
620
ADA4075-2
1/2 100
BOOST
CUT 5k 2.7k
BANDWIDTH
1k
1.5k
ADA4075-2
1/2 2.5k 2.5k
1.5k C1* 1.3k 1/2 1.3k 1/2 620 C2*
2.5k
2.5k 620
ADA4075-2
ADA4075-2
FREQUENCY (GANGED POTENTIOMETER) *THE CENTER FREQUENCY IS AFFECTED BY THE VALUE OF C1 AND C2 (SEE THE LOW NOISE PARAMETRIC EQUALIZER SECTION FOR MORE DETAILS).
07642-074
Figure 64. Low Noise Parametric Equalizer
Rev. 0 | Page 19 of 24
ADA4075-2 SCHEMATIC
V+
-INA/ -INB
+INA/ +INB
OUTA/ OUTB
V-
Figure 65. Simplified Schematic
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07642-072
ADA4075-2 OUTLINE DIMENSIONS
5.00 (0.1968) 4.80 (0.1890)
4.00 (0.1574) 3.80 (0.1497)
8 1
5 4
6.20 (0.2441) 5.80 (0.2284)
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE
1.75 (0.0688) 1.35 (0.0532)
0.50 (0.0196) 0.25 (0.0099) 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157)
45
0.51 (0.0201) 0.31 (0.0122)
COMPLIANT TO JEDEC STANDARDS MS-012-A A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 66. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model ADA4075-2ARZ 1 ADA4075-2ARZ-R71 ADA4075-2ARZ-RL1
1
Temperature Range -40C to +125C -40C to +125C -40C to +125C
Package Description 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N
012407-A
Package Option R-8 R-8 R-8
Z = RoHS Compliant Part.
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ADA4075-2 NOTES
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ADA4075-2 NOTES
Rev. 0 | Page 23 of 24
ADA4075-2 NOTES
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07642-0-10/08(0)
Rev. 0 | Page 24 of 24

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