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NUS6189MN Low Profile Overvoltage Protection IC with Integrated MOSFET
This device represents a new level of safety and integration by combining an overvoltage protection circuit (OVP) with a 30 V P-channel power MOSFET, a low VCE(SAT) transistor, and low RDS(on) power MOSFET or charging. The OVP is specifically designed to protect sensitive electronic circuitry from overvoltage transients and power supply faults. During such events, the IC quickly disconnects the input supply from the load, thus protecting it. The integration of the additional transistor and power MOSFET reduces layout space and promotes better charging performance. The IC is optimized for applications that use an external AC-DC adapter or a car accessory charger to power a portable product or recharge its internal batteries.
Features http://onsemi.com MARKING DIAGRAM
1 QFN22 CASE 485AT NUS 6189 ALYWG G
* * * * * * * * * * * * * * *
Overvoltage Turn-Off Time of Less Than 1.0 ms Accurate Voltage Threshold of 6.85 V, Nominal Undervoltage Lockout Protection; 2.8 V, Nominal High Accuracy Undervoltage Threshold of 2.0% -30 V Integrated P-Channel Power MOSFET Low RDS(on) = 50 mW @ -4.5 V High Performance -12 V P-Channel Power MOSFET Single-Low Vce(sat) Transistors as Charging Power Mux Compact 3.0 x 4.0 mm QFN Package Maximum Solder Reflow Temperature @ 260C This is a Pb-Free Device Provide Battery Protection Integrated Solution Offers Cost and Space Savings Integrated Solution Improves System Reliability Optimized for Commercial PMUs from Top Suppliers
NUS6189 = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location)
ORDERING INFORMATION
Device NUS6189MNTWG Package Shipping
QFN22 3000 / Tape & Reel (Pb-Free)
Benefits
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
Applications
* Portable Computers and PDAs * Cell Phones and Handheld Products * Digital Cameras
(c) Semiconductor Components Industries, LLC, 2008
October, 2008 - Rev. 0
Publication Order Number: NUS6189MN/D
NUS6189MN
Control Batt Batt GND Gate1 18 17 Batt
22
Source1
1
Batt
Batt
Batt
Base
VIN
Collector
VCC
Collector
Collector
OVPOUT
OVPOUT
Collector
6
12
Source2
7 Emitter Collector OVPOUT Gate2
11 OVPOUT OVPOUT Emitter BJT OVP 4,5,6,7 3 Base Collector CHG CTL VSense
(Top View)
Figure 1. Pinout
Source2 12 MOSFET2
Adapter Input
9, 11, 13 8
VCHG
10 VCC VIN 14 15
1 18
Source1 VSense Gate1 Batt Vbat
MOSFET1
Bat FET
2,16,17,21,22 Blocks Integrated in NUS6189 GND 19 Batt
Battery
Qualcomm QSC60xx
Figure 2. Typical Charging Solution for Qualcomm QSC60xx
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NUS6189MN
FUNCTIONAL PIN DESCRIPTIONS
Pin 1 2, 16, 17, 21, 22 3 4, 5, 6, 7 8 9, 11, 13 10 12 14 15 Function Source 1 Batt Base Collector Emitter OVPOUT Gate2 Source 2 VCC VIN Description This pin is the source of MOSFET1 and connects to the more negative Vsense pin of the PMIC and to the more negative side of the current sense resistor. These pins are the drain of MOSFET2 and connect to the battery and the Vbat pin of the PMIC. The base of the internal bipolar transistor is connected to this pin. It connects to the Charge Control pin of the PMIC. The collector of the internal bipolar transistor connects to these pins and should be connected to the more positive side of the current sense resistor as well as the more positive Vsense pin of the PMIC. This pin is connected to the emitter of the bipolar transistor. It should be connected externally to the OVPOUT pins. These pins are the output of the OVP circuit. Internally they connect to the drain of MOSFET2. These pins connect externally to the Vcharge pin of the PMIC. This pin is the gate of MOSFET2. It is not normally connected to external circuitry. The source of the OVP FET is connected to this pin. This pin needs to be connected to pins 14 & 15. This pin is the VCC pin of the OVP chip. It needs to be connected to pins 12 and 15. This pin senses the output voltage of the charger. If the voltage on this input rises above the overvoltage threshold (VTH), the OVPOUT pin will be driven to within 1.0 V of VIN, thus disconnecting the FET. The nominal threshold level is 6.85 V. This pin needs to be connected to pins 12 and 14. This pin is the gate of MOSFET1. It connects to the Bat FET pin of the PMIC. This is the ground reference pin for the OVP chip. This logic signal is used to control the state of OVPOUT and turn-on/off the P-channel MOSFET. A logic level high results in the OVPOUT signal being driven to within 1.0 V of VCC which turns off MOSFET2. If this pin is not used, it should be connected to ground.
18 19 20
Gate1 Gnd Control
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NUS6189MN
MAXIMUM RATINGS
Rating VIN to Ground Gate2 Voltage to Ground Control Pin to Ground Shunt Voltage (OVPOUT to Batt) Maximum Power Dissipation (TA = 50C, Notes 1 & 3) Thermal Resistance, Junction-to-Air (Note 1) Average q for chip, minimum copper Maximum q for power device, minimum copper Average q, for chip (Note 2) Maximum q for power device (Note 1) Average q for chip (Note 1) Maximum q for power device (Note 1) Operating Case Temperature (Note 4) Operating Ambient Temperature (PD = 0.5 W, Note 1) Operating Junction Temperature (All Dice) Thermal Resistance Junction-to-Case (Note 4) Storage Temperature Range Continuous Input Current (TA = 50C, Notes 1 & 3) Gate-to-Source Voltage MOSFET1 Drain-to-Source Voltage MOSFET1 Drain-to-Source Voltage MOSFET2 Collector-Emitter Voltage BJT Collector-Base Voltage BJT Emitter-Base Voltage BJT Symbol VIN VG2 VCNTRL Vshunt PD qJ-A Value -0.3 to 30 -0.3 to 30 -0.3 to 13 12 1.2 137 145 98 103 77 82 125 109 150 30 -65 to 150 2.6 8.0 -12 -30 -20 -20 -7.0 Unit V V V V W C/W
TCmax TAmb TJmax YJC Tstg Imax VGS1 VDS1 VDS2 VCEO VCBO VEBO
C C C C/W C A V V V V V V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface-mounted on FR4 board using 1 inch sq pad size (Cu area = 1.127 in sq [1 oz] including traces). 2. Surface-mounted on FR4 board using 0.25 inch sq pad size (Cu area = 0.37 in sq [1 oz] including traces). 3. VIN = 6.0 V, all power devices fully enhanced. 4. Surface-mounted on FR4 board using 400 mm sq pad size, 4 oz Cu, PD < 800 mW.
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NUS6189MN
ELECTRICAL CHARACTERISTICS (TJ = 25C, CNTRL 1.5 V, VCC = 6.0 V, unless otherwise specified)
Characteristic OVP THRESHOLD Input Threshold (VIN Increasing) Input Hysteresis (VIN Decreasing) Input Impedance (VIN = Vth) CONTROL INPUT Control Voltage High (Output On) Control Voltage Low (Output Off) Control Current High (Vih = 5.0 V) Control Current Low (Vil = 0.5 V) OVP GATE DRIVE VOLTAGE Gate2 Voltage High (VIN = 8.0 V; ISource = 10 mA) Gate2 Voltage High (VIN = 8.0 V; ISource = 0.25 mA) Gate2 Voltage High (VIN = 8.0 V; ISource = 0 mA) Gate2 Voltage Low (VIN = 6.0 V; ISink = 0 mA, Control = 0 V) Gate2 Sink Current (VIN < VTh, OVPOUT = 1.0 V, Note 5) TIMING Turn on Delay - Input (VIN stepped down from 8 to 6 V; measured at 50% point of OVPOUT, Note 5) Turn off Delay - Input (VIN stepped up from 6.0 to 8.0 V; CL = 12 nF Output > VIN - 1.0 V) Turn on Delay - Control (Control signal stepped down from 2.0 to 0.5 V; measured to 50% point of OVPOUT, Note 5) Turn off Delay - Control (Control signal stepped up from 0.5 to 2.0 V; CL = 12 nF Output > VIN -1.0 V) TOTAL DEVICE VIN Operating Voltage Range (Note 5) Input Bias Current Undervoltage Lockout (VIN Decreasing) OVP FET (MOSFET2) (TJ = 25C, VCC = 6.0 V, unless otherwise specified) Voltage Drop (VIN to OVPOUT, VGS = -4.5 V) ILoad = 0.6 A ILoad = 1.0 A ILoad = 1.0 A, TJ = 150C (Note 5) On Resistance ILoad = 0.6 A ILoad = 1.0 A ILoad = 1.0 A, TJ = 150C (Note 5) Off State Leakage Current TJ = 125C CHARGING BJT (TJ = 25C, unless otherwise specified) Collector-Emitter Cutoff Current (VCES = -20 V, Note 5) DC Current Gain (IB = -2.0 mA, VCE = -2.0 V, Note 6) Collector-Emitter Saturation Voltage IC = -1.0 A, IB = -0.01 A IC = -1.0 A, IB = -0.1 A ICES hfe VCE(sat) - 180 - - - - -0.10 -0.069 -0.1 - -0.12 -0.09 mA - V VOVP - - - - - - ILeak - - 33 66 90 50 52 90 -0.1 - 54 100 135 90 100 135 -1.0 -100 mA mV VIN IBias VLock 3.0 - 2.5 4.8 0.75 2.8 25 1.0 3.0 V mA V ton_IN toff_IN ton_CT toff_CT - - - - - 0.5 - 1.0 10 1.0 10 2.0 ms ms ms ms Voh VIN - 1.0 VIN - 0.25 VIN - 0.1 - 10 - - - - 33 - - - 0.10 50 V VcntrlHI VcntrlLO Iih Iil 1.50 - - - - - 95 10 - 0.50 200 - V V mA mA Vth Vhyst RIN 6.65 50 70 6.85 150 150 7.08 200 - V mV kW Symbol Min Typ Max Unit
Vol ISink
V mA
RDS(on)
mW
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NUS6189MN
ELECTRICAL CHARACTERISTICS (TJ = 25C, CNTRL 1.5 V, VCC = 6.0 V, unless otherwise specified)
Characteristic Input Capacitance (VEB = -0.5 V, f = 1.0 MHz, Note 5) Output Capacitance (VCB = -3.0 V, f = 1.0 MHz, Note 5) CHARGING FET (MOSFET1) (TJ = 25C, unless otherwise specified) Voltage Drop Across FET VGS = -4.5 V, ILoad = 1.0 A VGS = -2.5 V, ILoad = 1.0 A VGS = -4.5 V, ILoad = 1.0 A, TJ = 150C (Note 5) On Resistance VGS = -4.5 V, ILoad = 1.0 A VGS = -2.5 V, ILoad = 1.0 A VGS = -4.5 V, ILoad = 1.0 A, TJ = 150C, (Note 5) Off State Leakage Current (Note 5) TJ = 125C Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge (Note 5) Threshold Gate Charge Gate-to-Source Charge Gate-to-Drain Charge Gate Resistance Forward Transconductance (VDS = -6 V, ID = 1.0 A) Gate Threshold Voltage (VGS = VDS, ID = -250 mA) Negative Threshold Temperature Coefficient 5. Guaranteed by design. 6. Pulsed Condition: Pulse Width = 300 us, Duty Cycle < 2%. VDS - - - - - - ILeak CISS COSS CRSS QG(TOT) QG(TH) QGS QGD RG gfs VGS(th) VGS(th)/TJ - - - - - - - - - - - -0.45 - 32 44 62 32 44 62 -0.1 - 1330 200 115 13 1.5 2.2 2.9 14.4 0.9 -0.67 2.7 40 50 70 40 50 70 -1.0 -10 - - - 15.7 - - - - - -1.1 - mA pF pF pF nC nC nC nC W S V mV/ C mV Symbol Cibo Cobo Min - - Typ 240 50 Max 400 100 Unit pF pF
RDS(on)
mV
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NUS6189MN
TYPICAL CHARACTERISTICS - 12V, P-CHANNEL MOSFETS (MOSFET1 - CHARGING)
6 -ID, DRAIN CURRENT (A) 5 4 3 2 1 0 TJ = 25C 0 1 2 3 4 5 6 VGS = -1.4 V -1.7 - -8.0 V -1.6 V -ID, DRAIN CURRENT (A) -1.5 V 6 5 4 3 2 1 0 0.5 1.0 1.5 2.0 TJ = 25C VDS -10 V
TJ = 100C TJ = -55C
-VDS, DRAIN-TO-SOURCE VOLTAGE (V)
-VGS, GATE-TO-SOURCE VOLTAGE (V)
Figure 3. On-Region Characteristics
RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) 0.05 VGS = 4.5 V TJ = 100C 0.04 0.05
Figure 4. Transfer Characteristics
TJ = 25C
VGS = -2.5 V
0.04
TJ = 25C 0.03 TJ = -55C 0.02
VGS = -4.5 V 0.03
1
2
3
4
5
6
0.02
1
2
3
4
5
6
-ID, DRAIN CURRENT (A)
-ID, DRAIN CURRENT (A)
Figure 5. On-Resistance vs. Drain Current
1.6 RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 1.4 1.2 1.0 0.8 0.6 -50 10,000
Figure 6. On-Resistance vs. Drain Current and Gate Voltage
VGS = 0 V TJ = 150C -IDSS, LEAKAGE (nA)
ID = -3 A VGS = -4.5 V
1,000
TJ = 100C 100
-25
0
25
50
75
100
125
150
2
4
6
8
10
12
TJ, JUNCTION TEMPERATURE (C)
-VDS, DRAIN-TO-SOURCE VOLTAGE (V)
Figure 7. On-Resistance Variation with Temperature
Figure 8. Drain-to-Source Leakage Current vs. Voltage
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NUS6189MN
TYPICAL CHARACTERISTICS - 12V, P-CHANNEL MOSFETS (MOSFET1 - CHARGING)
VDS = 0 V VGS = 0 V -VDS, DRAIN-TO-SOURCE VOLTAGE (V) -VGS, GATE-TO-SOURCE VOLTAGE (V) 2800 6 5 4 3 2 1 0 Qgs Qgd ID = -3 A TJ = 25C 0 2 4 6 8 10 12 VGS VDS QT 12 10 8 6 4 2 0 14
2400 Ciss C, CAPACITANCE (pF) 2000 1600 1200 800 400 0 -4 -2 0 2 4 6 8 Crss Coss
TJ = 25C
Ciss
10
12
-VGS -VDS GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (V)
Qg, TOTAL GATE CHARGE (nC)
Figure 9. Capacitance Variation
1,000 VDD = -12 V ID = -3.0 A VGS = -4.5 V
Figure 10. Gate-to-Source and Drain-to-Source Voltage vs. Total Charge
10 -IS, SOURCE CURRENT (A) VGS = 0 V TJ = 25C
td(off) tf tr
t, TIME (ns)
100
1 TJ = 150C TJ = -55C
10
td(on)
0.1
1
1
10 RG, GATE RESISTANCE (W)
100
0.01
0
0.2
0.4
0.6
0.8
1.0
-VSD, SOURCE-TO-DRAIN VOLTAGE (V)
Figure 11. Resistive Switching Time Variation vs. Gate Resistance
100 -ID, DRAIN CURRENT (A) Single Pulse TC = 25C
Figure 12. Diode Forward Voltage vs. Current
10
100 ms 1 ms 10 ms
1
Mounted on 2 sq. FR4 board (0.5 sq. 2 oz. Cu single sided) with MOSFET die operating.
0.1
RDS(on) Limit Thermal Limit Package Limit 0.1 1 10
dc
0.01
100
-VDS, DRAIN-TO-SOURCE VOLTAGE (V)
Figure 13. Maximum Rated Forward Biased Safe Operating Area
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NUS6189MN
TYPICAL CHARACTERISTICS - 12V, P-CHANNEL MOSFETS (MOSFET1 - CHARGING)
1 RqJA, EFFECTIVE TRANSIENT THERMAL RESPONSE D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01
0.001
Single Pulse 1E-06 1E-05 1E-04 1E-03 1E-02 t, TIME (s) 1E-01 1E+00 1E+01 1E+02 1E+03
Figure 14. FET Thermal Response
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NUS6189MN
TYPICAL CHARACTERISTICS - SINGLE PNP TRANSISTOR (BJT - CHARGING)
0.25 VCE(sat), COLLECTOR EMITTER SATURATION VOLTAGE (V) IC/IB = 10 0.2 25C 0.15 -55C 0.1 0.05 0 VCE(sat) = 150C 0.35 VCE(sat), COLLECTOR EMITTER SATURATION VOLTAGE (V) IC/IB = 100 0.3 0.25 0.2 0.15 0.1 0.05 0 0.001 0.01 0.1 1.0 10 VCE(sat) = 150C
-55C
25C
0.001
0.01
0.1
1.0
10
IC, COLLECTOR CURRENT (A)
IC, COLLECTOR CURRENT (A)
Figure 15. Collector Emitter Saturation Voltage vs. Collector Current
800 750 700 650 600 550 500 450 400 350 300 250 200 150 100 1.1 150C (5.0 V) 150C (2.0 V) VBE(sat), BASE EMITTER SATURATION VOLTAGE (V) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3
Figure 16. Collector Emitter Saturation Voltage vs. Collector Current
IC/IB = 10
hFE, DC CURRENT GAIN
-55C 25C
25C (5.0 V) 25C (2.0 V) -55C (5.0 V) -55C (2.0 V) 0.001 0.01 0.1 1.0 10
150C
0.001
0.01
0.1
1.0
10
IC, COLLECTOR CURRENT (A)
IC, COLLECTOR CURRENT (A)
Figure 17. DC Current Gain vs. Collector Current
1.0 VBE(on), BASE EMITTER TURN-ON VOLTAGE (V) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.001 0.01 0.1 1.0 10 150C VCE = -2.0 V -55C 25C VCE, COLLECTOR-EMITTER VOLTAGE (V) 1.0 0.8 0.6 0.4 0.2 0
Figure 18. Base Emitter Saturation Voltage vs. Collector Current
10 mA 100 mA VCE (V) IC = 500 mA 300 mA
0.01
0.1
1.0
10
100
IC, COLLECTOR CURRENT (A)
IB, BASE CURRENT (mA)
Figure 19. Base Emitter Turn-On Voltage vs. Collector Current
Figure 20. Saturation Region
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NUS6189MN
TYPICAL CHARACTERISTICS - SINGLE PNP TRANSISTOR (BJT - CHARGING)
350 Cibo, INPUT CAPACITANCE (pF) 325 300 275 250 225 200 175 150 125 0 1.0 2.0 3.0 4.0 5.0 6.0 Cibo (pF) Cobo, OUTPUT CAPACITANCE (pF) 170 Cobo (pF) 150 130 110 90 70 50
0
2.0
4.0
6.0
8.0
10
12
14
16
VEB, EMITTER BASE VOLTAGE (V)
VCB, COLLECTOR BASE VOLTAGE (V)
Figure 21. Input Capacitance
10
Figure 22. Output Capacitance
1 ms 1.0 IC (A) 10 ms 0.1 Thermal Limit 0.01 100 ms 1s
0.01
0.1
1.0 VCE (Vdc)
10
100
Figure 23. Safe Operating Area
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NUS6189MN
TYPICAL PERFORMANCE CURVES - OVERVOLTAGE PROTECTION IC
(TA= 25C, unless otherwise specified) 7.05 7.00 I supply (mA) 6.95 Voltage (V) 6.90 6.85 6.80 6.75 6.70 -40 -25 -10 5 20 35 50 65 80 95 0.6 0.5 -40 1.0 0.9 0.8 0.7
-25
-10
5
20
35
50
65
80
95
Ambient Temperature (C)
Temperature (C)
Figure 24. Typical Vth Threshold Variation vs. Temperature
Figure 25. Typical Supply Current vs. Temperature Icc ) Iin, VCC + 6 V
100 90 80 IDpk, AMPS (A) 70 60 50 40 30 20 10 0 10 100 1000 10000
PULSE WIDTH (ms)
Figure 26. Typical Maximum Drain Peak Current vs Pulse Width (Non-repetitive Single Pulse, VGS = 10 V, TA = 255C)
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NUS6189MN
TYPICAL PERFORMANCE CURVES - 30V, P-CHANNEL MOSFET (MOSFET2 - OVP)
(TA= 25C, unless otherwise specified)
12 -ID, DRAIN CURRENT (AMPS) 11 10 9 8 7 6 5 4 3 2 1 0
-10V
-4.5 V -4.2 V -8 V -6 V -5.5 V -5 V
RDS(on), DRAIN-TO-SOURCE RESISTANCE (W)
-4 V
0.2
TJ = 25C ID = -3.7 A
-3.8 V -3.6 V -3.4 V -3.2 V
0.1
TJ = 25C 0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2
-3 V 3.6 4
0
2
3
4
5
6
7
8
9
10
-VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
-VGS, GATE VOLTAGE (VOLTS)
Figure 27. On-Region Characteristics
100000 -IDSS, LEAKAGE CURRENT (nA) 10 -IS, SOURCE CURRENT (AMPS)
Figure 28. On-Resistance vs. Gate-to-Source Voltage
VGS = 0 V TJ = 150C
VGS = 0 V TJ = 150C
10000
1
TJ = 100C TJ = 25C TJ = -55C 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 -VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
1000 TJ = 100C
100 5 25 10 15 20 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 30
0.1 0.3
Figure 29. Drain-to-Source Leakage Current vs. Voltage
Figure 30. Diode Forward Voltage vs. Current
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NUS6189MN
PACKAGE DIMENSIONS
QFN22, 3x4, 0.5P CASE 485AT-01 ISSUE B
D A B L1
PIN 1 REFERENCE
L
L
DETAIL A
OPTIONAL CONSTRUCTIONS
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PADS AS WELL AS THE TERMINALS. MILLIMETERS DIM MIN NOM MAX A 0.80 0.90 1.00 A1 0.00 0.025 0.05 A3 0.20 REF b 0.20 0.25 0.30 D 3.00 BSC D2 1.45 1.50 1.55 D3 0.52 0.57 0.62 D4 1.02 1.07 1.12 E 4.00 BSC E2 1.05 1.10 1.15 E3 1.30 1.35 1.40 E4 1.40 1.45 1.50 e 0.50 BSC --- K 0.25 --- 0.35 L 0.30 0.325 L1 --- --- 0.15 G 1.35 1.40 1.50 G1 0.95 1.05 1.15 G2 0.855 0.885 0.915
2X
0.15 C
2X
A1
DETAIL B
0.15 C 0.10 C
25X
TOP VIEW
DETAIL B
OPTIONAL CONSTRUCTIONS
A 0.08 C A3
SEATING PLANE
NOTE 4
SIDE VIEW G1 D3
7
A1
C
DETAIL A
D4
12
22X
L 0.50 PITCH
G
E3
E4
G
E2
22X 1
b 0.10 C A B 0.05 C
NOTE 3
16X
K
18
e G2 D2 BOTTOM VIEW
22X
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
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CCC CCC EEE
1 1.47 4.30 1.47 0.52
22X
EE EE EE
EEE EEE EEE EEE
E
EXPOSED Cu MOLD CMPD
A3
SOLDERING FOOTPRINT*
3.30 1.55 0.925
PACKAGE OUTLINE
1.21
1.47 1.58
0.39 0.30
1.14
DIMENSIONS: MILLIMETERS
NUS6189MN/D

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