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Quad Lane Extender
QLx4300-S45
The QLx4300-S45 is a settable quad receive-side equalizer with extended functionality for advanced protocols operating with line rates up to 3.125Gb/s such as InfiniBand (SDR) and 10GBase-CX4. The QLx4300-S45 compensates for the frequency dependent attenuation of copper twin-axial cables, extending the signal reach up to 40m on 24AWG cable. The small form factor, highly-integrated quad design is ideal for high-density data transmission applications including active copper cable assemblies. The four equalizing filters within the QLx4300-S45 can each be set to one of 32 compensation levels, providing optimal signal fidelity for a given media and length. The compensation level for each filter can be set by either (a) three external control pins or (b) a serial bus interface. When the external control pins are used, 18 of the 32 boost levels are available for each channel. If the serial bus is used, all 32 compensation levels are available. Operating on a single 1.2V power supply, the QLx4300-S45 enables per channel throughputs of up to 3.125Gb/s while supporting the lower data rates of 2.5Gb/s and 1.5Gb/s. The QLx4300-S45 uses current mode logic (CML) inputs/outputs and is packaged in a 4mmx7mm 46 lead QFN. Individual lane impedance select support is included for module applications.
QLx4300-S45
Features
* Supports data rates up to 3.125Gb/s * Low power (78mW per channel) * Low latency (<500ps) * Four equalizers in a 4mmx7mm QFN package for straight route-through architecture and simplified routing * Each equalizer boost is independently pin selectable and programmable * Beacon signal support and line silence preservation * 1.2V supply voltage * Individual channel power-down (impedance select)
Applications
* InfiniBand (SDR) * 10GBase-CX4 * PCI Express (Gen 1) * DisplayPort * XAUI * SAS (1.0) * High-speed active cable assemblies * High-speed printed circuit board (PCB) traces
Benefits
* Thinner gauge cable * Extends cable reach greater than 3x * Improved BER
Typical Application Circuit
QLX4300-S45
QLX4300-S45
<40M 24AWG
November 19, 2009 FN6982.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
QLx4300-S45
Ordering Information
PART NUMBER (Note) QLX4300SIQT7 QLX4300SIQSR PART MARKING QLX4300SIQ QLX4300SIQ TEMP. RANGE (C) 0 to +70 0 to +70 PACKAGE (Pb-Free) 46 Ld QFN 7" Prod. Tape & Reel; Qty 1,000 46 Ld QFN 7" Sample Reel; Qty 100 PKG. DWG. # L46.4x7 L46.4x7
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pin Configuration
QLx4300-S45 (46 LD 4x7 QFN) TOP VIEW
CP1[A] CP1[B] CP1[C] CP2[B] CP4[B] CP2[A] CP2[C] 38 BGREF 37 OUT1[P] 36 OUT1[N] 35 VDD 34 OUT2[P] 33 OUT2[N] 32 VDD EXPOSED PAD (GND) 31 OUT3[P] 30 OUT3[N] 29 VDD 28 OUT4[P] 27 OUT4[N] 26 IS3 25 IS4 24 MODE 16 17 18 19 20 21 22 23 CP3[A] CP3[B] CP3[C] CP4[A] CP4[C] DI DO
46 45 44 43 42 41 40 39 DT IN1[P] IN1[N] VDD IN2[P] 1 2 3 4 5
IN2[N] 6 VDD 7 IN3[P] 8 IN3[N] 9 VDD 10 IN4[P] 11 IN4[N] 12 IS1 13 IS2 14 GND 15
2
CLK
ENB
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Pin Descrptions
PIN NAME DT PIN NUMBER 1 DESCRIPTION Detection Threshold. Reference DC current threshold for input signal power detection. Data output OUT[k] is muted when the power of the equalized version of IN[k] falls below the threshold. Tie to ground to disable electrical idle preservation and always enable the limiting amplifier. Equalizer 1 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 4GHz frequency response is recommended. Power supply. 1.2V supply voltage. The use of parallel 100pF and 10nF decoupling capacitors to ground is recommended for each of these pins for broad high-frequency noise suppression. Equalizer 2 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 4GHz frequency response is recommended. Equalizer 3 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 4GHz frequency response is recommended. Equalizer 4 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 4GHz frequency response is recommended. Impedance Select 1. CMOS logic input. When the voltage on this pin is LOW, the single-ended input impedance of In1P and In1N each go above 200k and powers down the channel. This pin should be connected to the Fundamental Reset signal in PCI ExpressTM. Otherwise, connect to VDD to hold the input impedance at 50. Impedance Select 2. CMOS logic input. When the voltage on this pin is LOW, the single-ended input impedance of In2P and In2N each go above 200k and powers down the channel. This pin should be connected to the Fundamental Reset signal in PCI ExpressTM. Otherwise, connect to VDD to hold the input impedance at 50. Ground Serial data input, CMOS logic. Input for serial data stream to program internal registers controlling the boost for all four equalizers. Synchronized with clock (CLK) on pin 46. Overrides the boost setting established on CP control pins. Internally pulled down. Serial data output, CMOS logic. Output of the internal registers controlling the boost for all four equalizers. Synchronized with clock on pin 46. Equivalent to serial data input on DI but delayed by 21 clock cycles. Control pins for setting equalizer 3. CMOS logic inputs. Pins are read as a 3-digit number to set the boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25k resistor. Control pins for setting equalizer 4. CMOS logic inputs. Pins are read as a 3-digit number to set the boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25k resistor. Boost-level control mode input, CMOS logic. Allows serial programming of internal registers through pins DI, ENB, and Clk when set HIGH. Resets all internal registers to zero and uses boost levels set by CP pins when set LOW. If serial programming is not used, this pin should be grounded. Impedance Select 4. CMOS logic input. When the voltage on this pin is LOW, the single-ended input impedance of In4P and In4N each go above 200k and powers down the channel. This pin should be connected to the Fundamental Reset signal in PCI ExpressTM. Otherwise, connect to VDD to hold the input impedance at 50. Impedance Select 3. CMOS logic input. When the voltage on this pin is LOW, the single-ended input impedance of In3P and In3N each go above 200k and powers down the channel. This pin should be connected to the Fundamental Reset signal in PCI ExpressTM. Otherwise, connect to VDD to hold the input impedance at 50. Equalizer 4 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 4GHz frequency response is recommended. Equalizer 3 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 4GHz frequency response is recommended.
IN1[P,N] VDD IN2[P,N] IN3[P,N] IN4[P,N] IS1
2, 3 4, 7, 10, 29, 32, 35 5, 6 8, 9 11, 12 13
IS2
14
GND DI
15 16
DO
17
CP3[A,B,C]
18, 19, 20
CP4[A,B,C]
21, 22, 23
MODE
24
IS4
25
IS3
26
OUT4[N,P] OUT3[N,P]
27, 28 30, 31
3
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Pin Descrptions (Continued)
PIN NAME OUT2[N,P] OUT1[N,P] BGREF CP2[C,B,A] PIN NUMBER 33, 34 36, 37 38 39, 40, 41 DESCRIPTION Equalizer 2 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 4GHz frequency response is recommended. Equalizer 1 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 4GHz frequency response is recommended. External bandgap reference resistor. Recommended value of 6.04k 1%. Control pins for setting equalizer 2. CMOS logic inputs. Pins are read as a 3-digit number to set the boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25k resistor. Control pins for setting equalizer 1. CMOS logic inputs. Pins are read as a 3-digit number to set the boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25k resistor. Serial data enable (active low), CMOS logic. Internal registers can be programmed with DI and CLK pins only when the ENB pin is `LOW'. Internally pulled down. Serial data clock, CMOS logic. Synchronous clock for serial data on DI and DO pins. Data on DI is latched on the rising clock edge. Clock speed is recommended to be between 10MHz and 20MHz. Internally pulled down. Exposed ground pad. For proper electrical and thermal performance, this pad should be connected to the PCB ground plane.
CP1[C,B,A]
42, 43, 44
ENB CLK
45 46
EXPOSED PAD
-
4
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Absolute Maximum Ratings
Supply Voltage (VDD to GND) . . . . . . . . . . . . -0.3V to 1.3V Voltage at All Input Pins . . . . . . . . . . . -0.3V to VDD + 0.3V ESD Rating at All Pins . . . . . . . . . . . . . . . . . . . . 2kV (HBM)
Thermal Information
Thermal Resistance (Typical) JA (C/W) Jc (C/W) 46 Ld QFN Package (Note 1). . . . . 32 2.3 Operating Ambient Temperature Range. . . . . . 0C to +70C Storage Ambient Temperature Range . . . . . -55C to +150C Maximum Junction Temperature. . . . . . . . . . . . . . . +125C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTE: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Operating Conditions
PARAMETER Supply Voltage Operating Ambient Temperature Bit Rate SYMBOL VDD TA NRZ data applied to any channel CONDITION MIN 1.1 0 1.5 TYP 1.2 25 MAX 1.3 70 3.125 UNITS V C Gb/s
Control Pin Characteristics Typical values are at VDD = 1.2V, TA = +25C, and VIN = 800mVP-P, unless otherwise
noted. VDD = 1.1V to 1.3V, TA = 0C to +70C. PARAMETER Input `LOW' Logic Level Input `HIGH' Logic Level Output `LOW' Logic Level Output `HIGH' Logic Level `LOW' Resistance State `MID' Resistance State `HIGH' Resistance State Input Current NOTE: 2. If four CP pins are tied together, the resistance values in this table should be divided by four. SYMBOL VIL VIH VOL VOH DI, Clk, ENB DI, Clk, ENB IS[k], DO IS[k], DO CP[k][A,B,C] CP[k][B,C] CP[k][A,B,C] Current draw on digital pin, i.e., CP[k][A,B,C], DI, Clk, ENB CONDITION MIN 0 750 0 1000 0 22.5 500 30 25 0 TYP 0 MAX 350 VDD 250 VDD 1 27.5 100 UNITS mV mV mV mV k k k A 2 2 2 NOTES
Electrical Specifications
PARAMETERS Supply Current Cable Input Amplitude Range DC Differential Input Resistance DC Single-Ended Input Resistance Input Return Loss (Differential) Input Return Loss (Common Mode)
Typical values are at VDD = 1.2V, TA = +25C, and VIN = 800mVP-P, unless otherwise noted. VDD = 1.1V to 1.3V, TA = 0C to +70C. CONDITION MIN TYP 260 Measured differentially at data source before encountering channel loss Measured on input channel IN[k] Measured on input channel IN[k]P or IN[k]N 800 80 40 10 6 1200 100 50 1600 120 60 MAX UNITS NOTES mA mVP-P dB dB 4 4 3
SYMBOL IDD VIN
SDD11 SCC11
50MHz to 3.75GHz 50MHz to 3.75GHz
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Electrical Specifications
PARAMETERS Input Return Loss (Com. to Diff. Conversion) Output Amplitude Range Typical values are at VDD = 1.2V, TA = +25C, and VIN = 800mVP-P, unless otherwise noted. VDD = 1.1V to 1.3V, TA = 0C to +70C. (Continued) CONDITION 50MHz to 3.75GHz Active data transmission mode; Measured differentially at OUT[k]P and OUT[k]N with 50 load on both output pins Line Silence mode; Measured differentially at OUT[k]P and OUT[k]N with 50 load on both output pins Differential Output Impedance Output Return Loss (Differential) Output Return Loss (Common Mode) Output Return Loss (Com. to Diff. Conversion) Output Residual Jitter SDD22 SCC22 SDC22 Measured on OUT[k] 50MHz to 3.75GHz 50MHz to 3.75GHz 50MHz to 3.75GHz 3.125Gb/s; Up to 20m 24AWG standard twin-axial cable (approx. -25dB @ 2.5GHz); 800mVP-P VIN 1600mVP-P tr, tf 20% to 80% 30 80 10 5 20 0.15 0.25 MIN 20 450 550 650 TYP MAX UNITS NOTES dB mVP-P 4
SYMBOL SDC11 VOUT
10
20
mVP-P
105
120
dB dB dB UI 4 4 4 3, 5, 6
Output Transition Time Lane-to-Lane Skew Propagation Delay Data-to-Line Silence Response Time
60
80 50
ps ps ps ns
7
From IN[k] to OUT[k] tDS Time to transition from active data to line silence (muted output) on 20m 24AWG standard twin-axial cable at 3.125Gb/s Time from last bit of ALIGN(0) for SAS OOB signaling to line silence (<20mVP-P output); Meritec 24AWG 20m; 3.125Gb/s
500 15
8, 11
14
ns
12
Line Silence-to-Data Response Time
tSD
Time to transition from line silence mode (muted output) to active data on 20m 24AWG standard twin-axial cable at 3.125Gb/s Time from first bit of ALIGN(0) for SAS OOB signaling to 450mVP-P output; Meritec 24AWG 20m; 3.125Gb/s
20
ns
8, 11
19
ns
12
Timing Difference (SAS) NOTES:
|tDS - tSD|
For SAS OOB signaling support; Meritec 24AWG 20m
5
ns
12
3. After channel loss, differential amplitudes at QLx4300-S45 inputs must meet the input voltage range specified in "Absolute Maximum Ratings" on page 5. 4. Temperature = +25C, VDD = 1.2V. 5. Output residual jitter is the difference between the total jitter at the lane extender output and the total jitter of the transmitted signal (as measured at the input to the channel). Total jitter (TJ) is DJPP + 14.1 x RJRMS.
6. Measured using a PRBS 27-1 pattern. Deterministic jitter at the input to the lane extender is due to frequency-dependent, media-induced loss only. 7. Rise and fall times measured using a 1GHz clock with a 20ps edge rate.
8. For active data mode, cable input amplitude is 400mVP-P (differential) or greater. For line silence mode, cable input amplitude is 20mVP-P (differential) or less. 9. Measured differentially across the data source.
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NOTES: (Continued) 10. During line silence, transmitter noise in excess of this voltage range may result in differential output amplitudes from the QLx4300-S45 that are greater than 20mVP-P. 11. The data pattern preceding line silence mode is comprised of the PCIe electrical idle ordered set (EIOS). The data pattern following line silence mode is comprised of the PCIe electrical idle exit sequence (EIES). 12. The data pattern preceding or following line silence mode is comprised of the SAS-2 ALIGN (0) sequence for OOB signaling at 3.125Gb/s, and amplitude of 800mVP-P.
Serial Bus Timing Characteristics
PARAMETER CLK Setup Time DI Setup Time DI Hold Time ENB `HIGH' Boost Setting Operational DO Hold Time Clock Rate SYMBOL tSCK tSDI tHDI tHEN tD tCQ fCLK CONDITION From the falling edge of ENB Prior to the rising edge of CLK From the rising edge of CLK From the falling edge of the last data bit's CLK From ENB `HIGH' From the rising edge of CLK to DO transition Reference clock for serial bus EQ programming 12 20 MIN 10 10 6 10 10 TYP MAX UNITS ns ns ns ns ns ns MHz
Typical Performance Characteristics
VDD = 1.2V, TA = +25C, unless otherwise noted. Performance was characterized using the system testbed shown in Figure 1. Unless otherwise noted, the transmitter generated a non-return-to-zero (NRZ) PRBS-7 sequence at 800mVP-P (differential) with 10ps of peak-to-peak deterministic jitter. This transmit signal was launched into twin-axial cable test channels of varying gauges and lengths. The loss characteristics of these test channels are plotted as a function of frequency in Figure 2. The received signal at the output of these test channels was then processed by the QLx4300-S45 before being passed to a receiver. Eye diagram measurements were made with 4000 waveform acquisitions and include random jitter.
Pattern Generator
SMA Adapter Card
100O Twin-Axial Cable
SMA Adapter Card
QLx4300-S45 Eval Board
Oscilloscope
FIGURE 1. DEVICE CHARACTERIZATION TEST SETUP
TEST CHANNEL LOSS CHARACTERISTICS
0 -5 -10
SDD21 (dB)
-15 -20 -25 -30 -35 -40 -45 -50 0 1 2 3 4 5 6
10m 15m 20m 25m
Frequency (GHz)
FIGURE 2. 26 AWG TWIN-AXIAL CABLE LOSS AS A FUNCTION OF FREQUENCY FOR VARIOUS TEST CHANNELS
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Typical Performance Characteristics (Continued)
0.35 0.3 0.25
Jitter (ps)
0.2 0.15 10m 0.1 0.05 0 0 5 10 15 20 25 30 35 15m 20m 25m
Boost Setting
FIGURE 2. JITTER VS BOOST SETTING FOR VARIOUS CABLE LENGTHS, PRBS-7, 0.03PS SYSTEM JITTER INCLUDED
OUTPUT EYE DIAGRAMS
60mV/div
80mV/div
64ps/div
64ps/div
FIGURE 3. RECEIVED SIGNAL AFTER 10m OF 26AWG TWIN-AXIAL CABLE, 3.125Gb/s
FIGURE 4. QLx4300-S45 OUTPUT AFTER 10m OF 26AWG TWIN-AXIAL CABLE, 3.125Gb/s
80mV/div
80mV/div
64ps/div
64ps/div
FIGURE 5. RECEIVED SIGNAL AFTER 15m OF 26AWG TWIN-AXIAL CABLE, 3.125Gb/s
FIGURE 6. QLx4300-S45 OUTPUT AFTER 15m OF 26AWG TWIN-AXIAL CABLE, 3.125Gb/s
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Typical Performance Characteristics (Continued)
70mV/div
64ps/div
80mV/div
64ps/div
FIGURE 7. RECEIVED SIGNAL AFTER 20m OF 26AWG TWIN-AXIAL CABLE, 3.125Gb/s
FIGURE 8. QLx4300-S45 OUTPUT AFTER 20m OF 26AWG TWIN-AXIAL CABLE, 3.125Gb/s
60mV/div
60mV/div
64ps/div
64ps/div
FIGURE 9. RECEIVED SIGNAL AFTER 25m OF 26AWG TWIN-AXIAL CABLE, 3.125Gb/s
FIGURE 10. QLx4300-S45 OUTPUT AFTER 25m OF 26AWG TWIN-AXIAL CABLE, 3.125Gb/s
RETURN LOSS AND CROSSTALK CHARACTERISTICS
0 -5
Channel 1 Channel 2 Channel 3
0
Channel 1
-5
SCC11 (dB)
-15 -20 -25 -30 0 0.5 1 1.5 2 2.5 3 3.5 4
SCC22 (dB)
-10
Channel 4
-10 -15 -20 -25 -30 0
Channel 2 Channel 3 Channel 4
0.5
1
1.5
2
2.5
3
3.5
4
Frequency (GHz)
FIGURE 11. INPUT COMMON-MODE RETURN LOSS
Frequency (GHz)
FIGURE 12. OUTPUT COMMON-MODE RETURN LOSS
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Typical Performance Characteristics (Continued)
0 -5 -10
0 -5 -10
Channel 1 Channel 2 Channel 3 Channel 4
SDD11 (dB)
-15 -20 -25 -30 -35 0 0.5 1 1.5 2 2.5 3 3.5 4
Channel 1 Channel 2 Channel 3 Channel 4
SDD22 (dB)
-15 -20 -25 -30 -35 0 0.5 1 1.5 2 2.5 3 3.5 4
Frequency (GHz)
FIGURE 13. INPUT DIFFERENTIAL RETURN LOSS
Frequency (GHz)
FIGURE 14. OUTPUT DIFFERENTIAL RETURN LOSS
FIGURE 15. DIFFERENTIAL CROSSTALK BETWEEN ADJACENT INPUT CHANNEL
FIGURE 16. DIFFERENTIAL CROSSTALK BETWEEN ADJACENT INPUT CHANNELS
Operation
The QLx4300-S45 is an advanced quad lane-extender for high-speed interconnects. A functional diagram of one of the four channels in the QLx4300-S45 is shown in Figure 17. In addition to a robust equalization filter to compensate for channel loss and restore signal fidelity, the QLx4300-S45 contains unique integrated features to preserve special signaling protocols typically broken by other equalizers. The signal detect function is used to mute the channel output when the equalized signal falls below the level determined by the Detection Threshold (DT) pin voltage. This function is intended to preserve periods of line silence ("quiescent state" in InfiniBand contexts). As illustrated in Figure 17, the core of each high-speed signal path in the QLx4300-S45 is a sophisticated equalizer followed by a limiting amplifier. The equalizer compensates for skin loss, dielectric loss, and impedance discontinuities in the transmission channel. Each 10
equalizer is followed by a limiting amplification stage that provides a clean output signal with full amplitude swing and fast rise-fall times for reliable signal decoding in a subsequent receiver.
IN[k] IS[k] >200k SETTABLE EQUILIZER BIT SELECT (CP[k]/DI) AMPLITUDE DETECTOR DT + MUTE ENABLED LIMITING AMPLIFIER OUT[k]
FIGURE 17. FUNCTIONAL DIAGRAM OF A SINGLE CHANNEL WITHIN THE QLx4300-S45
Individually Adjustable Equalization Boost
Each channel in the QLx4300-S45 features an independently settable equalizer for custom signal restoration. Each equalizer can be set to one of 32 levels of compensation when the serial bus is used to program
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the boost level and one of 18 compensation levels when the CP[k] pins are used to set the level. The equalizer transfer functions for a subset of these compensation levels are plotted in Figure 18. The flexibility of this adjustable compensation architecture enables signal fidelity to be optimized on a channel-by-channel basis, providing support for a wide variety of channel characteristics and data rates ranging from 2.5Gb/s to 3.125Gb/s. Because the boost level is externally set rather than internally adapted, the QLx4300-S45 provides reliable communication from the very first bit transmitted. There is no time needed for adaptation and control loop convergence. Furthermore, there are no pathological data patterns that will cause the QLx4300-S45 to move to an incorrect boost level. The "Applications Information" section beginning on page 12 details how to set the boost level by both the CP-pin voltage approach and the serial programming approach.
VDD IN[k] P 50
Buffer
50 IN[k] N
FIGURE 19. CML INPUT EQUIVALENT CIRCUIT FOR THE QLx4300-S45
VDD
52
52 OUT[k] P OUT[k] N
FIGURE 18. EQUALIZER TRANSFER FUNCTIONS FOR SETTINGS 0, 5, 10, 15, 20, 25, AND 31 IN THE QLx4300-S45
FIGURE 20. CML OUTPUT EQUIVALENT CIRCUIT FOR THE QLx4300-S45 NOTE: The load value of 52 is used to internally match SDD22 for a characteristic impedance of 50.
CML Input and Output Buffers
The input and output buffers for the high-speed data channels in the QLx4300-S45 are implemented using CML. Equivalent input and output circuits are shown in Figures 19 and 20, respectively.
Line Silence/Electrical Idle/Quiescent Mode
Line silence is commonly broken by the limiting amplification in other equalizers. This disruption can be detrimental in many systems that rely on line silence as part of the protocol. The QLx4300-S45 contains special lane management capabilities to detect and preserve periods of line silence while still providing the fidelity-enhancing benefits of limiting amplification during active data transmission. Line silence is detected by measuring the amplitude of the equalized signal and comparing that to a threshold set by the current at the DT pin. When the amplitude falls below the threshold, the output driver stages are muted and held at their nominal common mode voltage1.
1. The output common mode voltage remains constant during both active data transmission and output muting modes.
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CP1[A] CP1[B] CP1[C] CP2[B] CP4[B] CP2[A] CP2[C] 38 BGREF 37 OUT1[P] 36 OUT1[N] 35 VDD 34 OUT2[P] 33 OUT2[N] 32 VDD EXPOSED PAD (GND) 31 OUT3[P] 30 OUT3[N] 29 VDD 28 OUT4[P] 27 OUT4[N] 26 IS3 25 IS4 24 MODE 16 17 18 19 20 21 22 23 DO DI CP3[A] CP3[B] CP3[C] CP4[A] CP4[C]
Channel Power-Down
In addition to controlling the input impedance, the IS[k] pin powers down the equalizer channel when pulled low. This feature allows a system controller individually to power down unused channels and to minimize power consumption. Example: the signal to power down a channel could come from an Intelligent Platform Management controller in ATCA applications for E-Keying. The current draw for a channel is reduced from 50mA to 3.8mA when powered down.
CLK DT IN1[P] IN1[N] VDD IN2[P] 1 2 3 4 5 IN2[N] 6 VDD 7 IN3[P] 8 IN3[N] 9 VDD 10 IN4[P] 11 IN43[N] 12 IS1 13 IS2 14 GND 15 ENB
46 45 44 43 42 41 40 39
Applications Information
Several aspects of the QLx4300-S45 are capable of being dynamically managed by a system controller to provide maximum flexibility and optimum performance. These functions are controlled by interfacing to the highlighted pins in Figure 21. The specific procedures for controlling these aspects of the QLx4300-S45 are the focus of this section.
FIGURE 21. PIN DIAGRAM HIGHLIGHTING PINS USED FOR DYNAMIC CONTROL OF THE QLx4300-S45 TABLE 1. DESCRIPTIONS OF PINS THAT CAN BE USED TO SET EQUALIZATION BOOST LEVEL PIN NAME DI PIN NUMBER 16 DESCRIPTION Serial data input, CMOS logic. Input for serial data stream to program internal registers controlling the boost for all four equalizers. Synchronized with clock (CLK) on pin 46. Overrides the boost setting established on CP control pins. Internally pulled down. Serial data output, CMOS logic. Output of the internal registers controlling the boost for all four equalizers. Synchronized with clock on pin 46. Equivalent to serial data input on DI but delayed by 21 clock cycles. Control pins for setting equalizer 3. CMOS logic inputs. Pins are read as a 3-digit number to set the boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25k resistor. Control pins for setting equalizer 4. CMOS logic inputs. Pins are read as a 3-digit number to set the boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25k resistor. Boost-level control mode input, CMOS logic. Allows serial programming of internal registers through pins DI, ENB, and Clk when set "HIGH". Resets all internal registers to zero and uses boost levels set by CP pins when set LOW. If serial programming is not used, this pin should be grounded. Control pins for setting equalizer 2. CMOS logic inputs. Pins are read as a 3-digit number to set the boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25k resistor. Control pins for setting equalizer 1. CMOS logic inputs. Pins are read as a 3-digit number to set the boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25k resistor. Serial data enable (active low), CMOS logic. Internal registers can be programmed with DI and CLK pins only when the ENB pin is `LOW'. Internally pulled down. Serial data clock, CMOS logic. Synchronous clock for serial data on DI and DO pins. Data on DI is latched on the rising clock edge. Clock speed is recommended to be between 10MHz and 20MHz. Internally pulled down.
DO
17
CP3[A,B,C] CP4[A,B,C] MODE
18, 19, 20 21, 22, 23 24
CP2[C,B,A] CP1[C,B,A] ENB CLK
39, 40, 41 42, 43, 44 45 46
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QLx4300-S45
Equalization Boost Level
Channel equalization for the QLx4300-S45 can be individually set to either (a) one of 18 levels through the DC voltages on external control pins or (b) one of 32 levels via a set of registers programmed by a low speed serial bus. The pins used to control the boost level are highlighted in Figure 21. Descriptions of these pins are listed in Table 1. Please refer to "Pin Descrptions" on page 3 for descriptions of all other pins on the QLx4300-S45. The boost setting for equalizer channel k can be read as a three digit ternary number across CP[k][A,B,C]. The ternary value is established by the value of the resistor between VDD and the CP[k][A,B,C] pin. As a second option, the equalizer boost setting can be taken from a set of registers programmed through a serial bus interface (pins 16, 17, 45, and 46). Using this interface, a set of registers is programmed to store the boost level. A total of 21 registers are used. Registers 2 through 21 are parsed into four 5-bit words. Each 5-bit word determines which of 32 boost levels to use for the corresponding equalizer. Register 1 instructs the QLx4300-S45 to use registers 2 through 21 to set the boost level rather than the control pins CP[k][A,B,C]. Both options have their relative advantages. The control pin option minimizes the need for external controllers as the boost level can be set in the board design resulting in a compact layout. The register option is more flexible for cases in which the optimum boost level will not be known and can be changed by a host bus adapter with a small number of pins. It is noted that the serial bus interface can also be daisy-chained among multiple QLx4300-S45 devices to afford a compact programmable solution even when a large number of data lines need to be equalized. Upon power-up, the default value of all the registers (and register 1 in particular) is zero, and thus, the CP pins are used to set the boost level. This permits an alternate interpretation on setting the boost level. Specifically, the CP pins define the default boost level until the registers are (if ever) programmed via the serial bus.
TABLE 2. MAPPING BETWEEN CP-SETTING RESISTOR AND PROGRAMMED BOOST LEVELS RESISTANCE BETWEEN CP PIN AND VDD CP[A] Open Open Open Open Open Open Open Open Open 0 0 0 0 0 0 0 0 0 CP[B] Open Open Open 25k 25k 25k 0 0 0 Open Open Open 25k 25k 25k 0 0 0 CP[C] Open 25k 0 Open 25k 0 Open 25k 0 Open 25k 0 Open 25k 0 Open 25k 0 SERIAL BOOST LEVEL 0 2 4 6 8 10 12 14 15 16 17 19 21 23 24 26 28 31
Control Pin Boost Setting
When register 1 of the QLx4300-S45 is zero (the default state on power-up), the voltages at the CP pins are used to determine the boost level of each channel. For each of the four channels, k, the [A], [B], and [C] control pins (CP[k]) are associated with a 3-bit non binary word. While [A] can take one of two values, `LOW' or `HIGH', [B] and [C] can take one of three different values: `LOW', `MIDDLE', or `HIGH'. This is achieved by changing the value of a resistor connected between VDD and the CP pin, which is internally pulled low with a 25k resistor. Thus, a `HIGH' state is achieved by using a 0 resistor, `MIDDLE' is achieved with a 25k resistor, and `LOW' is achieved with an open resistance. Table 2 defines the mapping from the 3-bit CP word to the 18 out of 32 possible levels available via the serial interface. If all four channels are to use the same boost level, then a minimum number of board resistors can be realized by tying together like CP[k][A,B,C] pins across all channels k. For instance, all four CP[k][A] pins can be tied to the same resistor running to VDD. Consequently, only three resistors are needed to control the boost of all four channels. If the CP Pins are tied together and the 25k is used, the value changes to a 6.25k resistor because the 25k is divided by 4.
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Optimal Cable Boost Settings
The settable equalizing filter within the QLx4300-S45 enables the device to optimally compensate for frequency-dependent attenuation across a wide variety of channels, data rates, and encoding schemes. For the reference channels plotted in Figure 2, Table 3 shows the optimal boost setting when transmitting a PRBS-7 signal. The optimal boost setting is defined as the equalizing filter setting that minimizes the output residual jitter of the QLx4300-S45. The settings in Table 4 represent the optimal settings for the QLx4300-S45 across an ambient temperature range of 0C to +70C. The optimal setting at room temperature (+20C to +40C) is generally one to two settings lower than the values listed in Table 3.
TABLE 3. OPTIMAL CABLE BOOST SETTINGS CABLE Cable A Cable B Cable C APPROX. LOSS @ 1.5625GHz (dB) 17 23 28 QLx4300-S45 BOOST 12 16 23
NOTE: Optimal boost settings should be determined on an application-by-application basis to account for variations in channel type, loss characteristics, and encoding schemes. The settings in this table are presented as guidelines to be used as a starting point for application-specific optimization.
Register Description
The QLx4300-S45's internal registers are listed in Table 4. Register 1 determines whether the CP pins or register values 2 through 21 are used to set the boost level. When this register is set, the QLx4300-S45 uses registers 2-6, 7-11, 12-16, and 17-21 to set the boost level of equalizers 1, 2, 3, and 4. When register 1 is not set, the CP pins are used to determine the boost level for each equalizer channel. The use of five registers for each equalizer channel allows all 32 boost levels as candidate boost levels.
TABLE 4. DESCRIPTION OF INTERNAL SERIAL REGISTERS REGISTER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 4 3 2 EQUALIZER CHANNEL 1-4 1 DESCRIPTION CP control override - Use registers 2 through 21 (rather than CP pins) to establish the boost levels when this bit is set. Equalizer setting bit 0 (LSB). Equalizer setting bit 1. Equalizer setting bit 2. Equalizer setting bit 3. Equalizer setting bit 4 (MSB). Equalizer setting bit 0 (LSB). Equalizer setting bit 1. Equalizer setting bit 2. Equalizer setting bit 3. Equalizer setting bit 4 (MSB). Equalizer setting bit 0 (LSB). Equalizer setting bit 1. Equalizer setting bit 2. Equalizer setting bit 3. Equalizer setting bit 4 (MSB). Equalizer setting bit 0 (LSB). Equalizer setting bit 1. Equalizer setting bit 2. Equalizer setting bit 3. Equalizer setting bit 4 (MSB).
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QLx4300-S45
ENB
tSCK CLK
tHEN
tSDI tHDI DI R21 R20 R19 R1
FIGURE 22. TIMING DIAGRAM FOR PROGRAMMING THE INTERNAL REGISTERS OF THE QLx4300-S45
Serial Bus Programming
Pins 16 (DI), 45 (ENB), and 46 (CLK) are used to program the registers inside the QLx4300-S45. Figure 22 shows an exemplary timing diagram for the signals on these pins. The serial bus can be used to program a single QLx4300-S45 according to the following steps: 1. The ENB pin is pulled `LOW'. - While this pin is `LOW', the data input on DI are read into registers but not yet latched. - A setup time of tSCK is needed between ENB going `LOW' and the first rising clock edge. 2. At least 21 values are read from DI on the rising edge of the CLK signal. - If more than 21 values are passed in, then only the last 21 values are kept in a FIFO fashion. - The data on DI should start by sending the value destined for register 21 and finish by sending the value destined for register 1. - A range of clock frequencies can be used. A typical rate is 10MHz. The clock should not exceed 20MHz. - Setup (tSDI) and hold (tHDI) times are needed around the rising clock edge. 3. The ENB pin is pulled `HIGH' and the contents of the registers are latched and take effect. - After clocking in the last data bit, an additional tHEN should elapse before pulling the ENB signal `HIGH'. - After completing these steps, the new values will affect within tD.
uses a common ENB signal as the serial data is carried-over from one QLx4300-S45 to the next.
Separate ENB Signals
Multiple QLx4300-S45 devices can be programmed from a common serial data stream as shown in Figure 23. Here, each QLx4300-S45 is provided its own ENB signal, and only one of these ENB signals is pulled `LOW', and hence accepting the register data one at a time. In this situation, the programming of each equalizer follows the steps outlined in Figure 22.
DI/DO Carryover
The DO pin (pin 17) can be used to daisy-chain the serial bus among multiple QLx4300-S45 chips. The DO pin outputs the overflow data from the DI pin. Specifically, as data is pipelined into a QLx4300-S45, it proceeds according to the following flow. First, a bit goes into shadow register 1. Then, with each clock cycle, it shifts over into subsequent higher numbered registers. After shifting into register 21, it is output on the DO pin on the same clock cycle. Thus, the DO signal is equal to the DI signal, but delayed by 20 clock cycles. The timing diagram for the DO pin is shown in Figure 24 where the first 20 bits output from the DO are indefinite and subsequent bits are the data fed into the DI pin. The delay between the rising clock edge and the data transition is tCQ. A diagram for programming multiple QLx4300-S45s is shown in Figure 25. It is noted that the board layout should ensure that the additional clock delay experienced between subsequent QLx4300-S45s should be no more than the minimum value of tCQ, i.e. 12ns.
Programming Multiple QLx4300-S45 Devices
The serial bus interface provides a simple means of setting the equalizer boost levels with a minimal amount of board circuitry. Many of the serial interface signals can be shared among the QLx4300-S45 devices on a board and two options are presented in this section. The first uses common clock and serial data signals along with separate ENB signals to select which QLx4300-S45 accepts the programmed changes. The second method
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Serial Register Data
ENB CLK
QLx4300-S45 (A) DI
DO
ENB CLK
QLx4300-S45 (B) DI
DO
ENB CLK
QLx4300-S45 (C) DI
DO
ENB CLK
QLx4300-S45 (D) DI
DO
Clock
ENB (A) ENB (B) ENB (C) ENB (D)
FIGURE 23. SERIAL BUS PROGRAMMING MULTIPLE QLx4300-S45 DEVICES USING SEPARATE ENB SIGNALS
ENB 20 Clock Cycles tSCK CLK t CQ DO
FIGURE 24. TIMING DIAGRAM FOR DI/DO CARRYOVER
21st Rising Edge
First Bit from DI
Serial Register Data QLx4300-S45 (A) ENB DI
CLK DO
QLx4300-S45 (B) ENB DI
CLK DO
QLx4300-S45 (C) ENB DI
CLK DO
QLx4300-S45 (D) ENB DI
CLK DO
Clock ENB
FIGURE 25. SERIAL BUS PROGRAMMING MULTIPLE QLx4300-S45 DEVICES USING DI/DO CARRYOVER
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ENB
tSCK CLK
tHEN
tSDI tHDI DI R21 R20 R1 R21 R1 R21 R1 R21 R1
QLx4300-S45 (D)
QLx4300-S45 (C)
QLx4300-S45 (B)
QLx4300-S45 (A)
FIGURE 26. TIMING DIAGRAM FOR PROGRAMMING MULTIPLE QLx4300-S45 DEVICES USING DI/DO CARRYOVER
Detection Thereshold (DT) Pin Functionality
The QLx4300-S45 is capable of maintaining periods of line silence on any of its four channels by monitoring each channel for loss of signal (LOS) conditions and subsequently muting the outputs of a respective channel when such a condition is detected. A reference current applied to the detection threshold (DT) pin is used to set the LOS threshold of the internal signal detection circuitry. Current control on the DT pin is done via one or two external resistors. Nominally, both a pull-up and pull-down resistor are tied to the DT pin (Figure 27A), but if adequate control of the supply voltage is maintained to within 3% of 1.2V, then a simple pull down resistor is adequate (as in Figure 27B). Resistors used should be at least 1/16W, with 1% precision. The internal bias point of the DT pin, nominally 1.05V, is used in conjunction with the voltage divider (R1 and R2) shown in Figure 27A to set the reference current on the DT pin. Case 1: Channels with less than or equal to 17dB loss at 1.5625GHz: For signals transmitted on channels having less than or equal to 25dB of loss at 2.5GHz, the optimal DT reference current is 0A. This optimal reference current may be achieved by either leaving the DT pin floating, or tying the DT pin to ground (GND) with a 10M resistor. Case 2: Channels with greater 17dB loss at 1.5625GHz: For channels exhibiting more than 25dB of total loss (this includes cable or FR-4 loss) the DT pin should be configured for a reference sink current (coming out of the DT pin) of approximately 2A. A typical configuration for a 2A sink current is given in Figure 27C. If the configuration in Figure 27B is utilized, a 525k resistor is used.
FIGURE 27C. FIGURE 27.
FIGURE 27A.
FIGURE 27B.
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Typical Application Reference Designs
Figures 28 and 29 show reference design schematics for a QLx4300-S45 evaluation board with an SMA connector interface. Figure 28 shows the schematic for the case when the equalizer boost level is set via the CP pins. Figure 29 shows the schematic for the case when the level is set via the serial bus interface.
1.2V 42.2k Detection threshold reference current NC NC EQ Boost Control for Channels 1 and 2 (See pages 15-17) CP1[C] CP2[C] CP1[A] CP2[B] CP2[A] CP1[B]
6kO
47nF
100k
ENB
CLK
DT IN1[P] IN1[N] 1.2V IN2[P] IN2[N] 1.2V IN3[P] IN3[N] 1.2V IN4[P] IN4[N] IS1 IS2 Impedance Select (Channels 1 and 2) GND
45
42
46
44
41
43
40
39
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CP3[B] CP3[A] CP3[C] CP4[A] DI CP4[C] CP4[B] DO
38 37 36 35
BGREF OUT1[P] OUT1[N] 1.2V OUT2[P] OUT2[N] 1.2V OUT3[P] OUT3[N] 1.2V OUT4[P] OUT4[N] IS3 IS4 MODE
A
QLx4300-S45
34 33 32 31 30 29 28 27 26 25 24
Impedance Select (Channels 3 and 4) MODE at 1.2V: Serial Control Mode MODE at GND: Binary Control Mode
NC
NC
1.2V 100pF*
10nF
EQ Boost Control for Channels 3 and 4 (See pages 15-17) = SMA Connector
QLx4300-S45 LANE EXTENDER
Reference Control Pin Mode
Quellan, Inc.
Bypass circuit for each VDD pin: 4, 7, 10, 29, 32, 35 (*100pF capacitor should be positioned closest to the pin)
A) DC Blocking Capacitors = X7R or COG 0.1F (>4GHz bandwidth)
FIGURE 28. APPLICATION CIRCUIT FOR THE QLx4300-S45 EVALUATION BOARD USING THE CONTROL PINS FOR SETTING THE EQUALIZER COMPENSATION LEVEL
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Typical Application Reference Designs (Continued)
Figures 28 and 29 show reference design schematics for a QLx4300-S45 evaluation board with an SMA connector interface. Figure 28 shows the schematic for the case when the equalizer boost level is set via the CP pins. Figure 29 shows the schematic for the case when the level is set via the serial bus interface.
1.2V Serial Clock In 42.2k Enable Active Low
Detection threshold reference current
NC CP1[C] CP2[C] CP1[A] CP1[B] CP2[A] CP2[B]
6kO
47nF
100k
46
45
ENB
CLK
44
43
42
41
40
DT IN1[P] IN1[N] 1.2V IN2[P] IN2[N] 1.2V IN3[P] IN3[N] 1.2V IN4[P] IN4[N] IS1 IS2 Impedance Select (Channels 1 and 2) GND
39
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CP3[C] CP4[A] CP3[B] CP4[C] CP3[A] CP4[B] DI DO
38 37 36 35
BGREF OUT1[P] OUT1[N] 1.2V OUT2[P] OUT2[N] 1.2V OUT3[P] OUT3[N] 1.2V OUT4[P] OUT4[N] IS3 IS4 MODE
A
QLx4300-S45
34 33 32 31 30 29 28 27 26 25 24
Impedance Select (Channels 3 and 4) MODE at 1.2V: Serial Control Mode MODE at GND: Binary Control Mode
Serial Data In
Serial Data Out
1.2V 100pF*
NC
10nF
QLx4300-S45 LANE EXTENDER
Reference Serial Control Mode
Quellan, Inc.
= SMA Connector A) DC Blocking Capacitors = X7R or COG 0.1F (>4GHz bandwidth)
Bypass circuit for each VDD pin: 4, 7, 10, 29, 32, 35 (*100pF capacitor should be positioned closest to the pin)
FIGURE 29. APPLICATION CIRCUIT FOR THE QLx4300-S45 EVALUATION BOARD USING THE SERIAL BUS INTERFACE FOR SETTING THE EQUALIZER COMPENSATION LEVEL
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About Q:ACTIVE(R)
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For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 20
FN6982.1 November 19, 2009
QLx4300-S45
Package Outline Drawing
L46.4x7
46 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE (TQFN) Rev 0, 9/09
2.80 4.00 A B 6 PIN 1 INDEX AREA 38 39 42X 0.40 46 6 PIN 1 INDEX AREA 1
7.00
5.60
5.50 0.1 Exp. DAP
24 (4X) 0.05 TOP VIEW SIDE VIEW 46X 0.20 4 0.10 M C A B 46X 0.40 23 2.50 0.1 Exp. DAP BOTTOM VIEW SEE DETAIL "X" 16
15
0.70 0.05
0.10 C SEATING PLANE 0.05 C SIDE VIEW
C
C
0.152 REF
5
0 . 00 MIN. 0 . 05 MAX. DETAIL "X" ( 3.80 ) ( 2.50)
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. Unless otherwise specified, tolerance : Decimal 0.05 Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. (46X 0.20) 6. Tiebar shown (if present) is a non-functional feature. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. ( 46 X 0.60) TYPICAL RECOMMENDED LAND PATTERN
2. ( 6.80 ) ( 5.50 ) ( 42X 0.40) 3. 4.
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