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Introduction

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Circuit Description and Results
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Figure 1. #

> OUT2(s ) = OUT1(s ) (1 * s * RC) (1 + 1.4 * RC * s ) (1 + s * RC) (1 + 0.25 * RC * s )
XRDAN27

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XRDAN27
PSPICE CIRCUIT FILE

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# '3 ,2
2
1 2
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1 2
STS
H (s ) = FS = 1 TS
1*
e* STS
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71 @ 1
7 * '1 @ 1
6

A
R 10
R 50
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RC =
0.25 FS
Figure 3. Compensating for Zero Order Hold Amplitude Attenuation

XRDAN27
8
OUT2
5
Group Delay OUT1
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B
OUT1
OUT2 ? 7 * ; 7 *
Amplitude
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-:; ,& OUT1
B,& OUT2
9& Frequency
B9&
9&
B9&
Figure 4. Comparison of Hold Response before and after Compensation
B
XRDAN27
8
Group Delay
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Hold only
7
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OUT1 8; OUT2 Lead without Equilization
Amplitude
Lead
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9& 9& OUT1 OUT2
59& LEAD
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9&
Figure 5. Comparison of Hold Response before and after Compensation
5

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