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ZADCS146/ZADCS147
12-Bit, 200ksps, 8-Channel, Serial Output ADC
Datasheet
Features
* * * * * * * * * * Single Supply Operation: + 2.7V ... + 5.25V 8-Channel Single-Ended or 4-Channel Differential Inputs Up to 200ksps Conversion Rate 1 LSB INL and DNL No Missing Codes True fully differential Operation Software-Configurable Unipolar or Bipolar output coding Internal 3.2MHz oscillator for independent operation from external clock Internal 2.5V Reference Low Power < 1.2mA (200ksps, 5V supply) < 0.5A (power-down mode) SPITM / QSPITM / MICROWIRETM - compatible 4-Wire Serial Interface 20-Pin SSOP Alternate Source for MAX146 / MAX147
Description
ZADCS146 and ZADCS147 are low power, 12-bit, successive approximation analog-to-digital (A/D) converters with up to 200ksps conversion rate, 8-channel input multiplexer, high-bandwidth track/hold and synchronous serial interface. The ADC operates from a single + 2.7V to + 5.25V supply. Its analog inputs are software configurable for unipolar/bipolar and single-ended/differential operation. The 4-wire serial interface connects directly to SPITM/ (QSPITM and MICROWIRETM) devices without external logic. Both devices can use either the external serial-interface clock or an internal clock to perform successiveapproximation analog-to-digital conversions. The internal clock can be used to run independent conversions on more than one device in parallel. The ZADC146 is equipped with a highly accurate internal 2.5V reference with an additional external 1.5% voltage adjustment range. ZADCS146 / ZADCS147 provide a hard-wired shut-down pin (nSHDN) pin and software-selectable power-down modes that can be programmed to automatically shut down the IC at the end of a conversion. Accessing the serial interface automatically powers up the IC. A quick turn-on time allows the device to be shut down between all conversions.
* * *
Applications
* * * * Data Acquisition Industrial Process Control Portable Data Logging Battery-Powered Systems
Starterkit available
Functional Block Diagram
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM
8-Channel Analog Input Multiplexer
ININ+
SAR
Comparator DAC with inherent T&H
+ -
Serial Interface and Control State Machine
nCS SCLK DIN DOUT SSTRB nSHDN
x 2.000 + 1.25V Reference
REFADJ VREF Available in ZADCS146 only
Internal 3.2 MHz Oscillator
VDD DGND AGND
Copyright (c) 2008, ZMD AG, Rev. 1.1 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.
1/19
Datasheet ZADCS146 / ZADCS147
Table of Contents
1
Page
GENERAL DEVICE SPECIFICATION ....................................................................................................... 3 1.1 ABSOLUTE MAXIMUM RATINGS (NON OPERATING) .................................................................................... 3 1.2 PACKAGE PIN ASSIGNMENT.................................................................................................................... 4 1.3 ELECTRICAL CHARACTERISTICS .............................................................................................................. 5 1.3.1 General Parameters ................................................................................................................... 5 1.3.2 ZADCS146 Specific Parameters ................................................................................................ 6 1.3.3 ZADCS147 Specific Parameters ................................................................................................ 7 1.3.4 ZADCS146 / ZADCS147 Digital Pin Parameters ........................................................................ 7 1.4 TYPICAL OPERATING CHARACTERISTICS .................................................................................................. 8
2
DETAILED DESCRIPTION ...................................................................................................................... 10 2.1 2.2 2.3 2.4 2.5 GENERAL OPERATION.......................................................................................................................... 10 ANALOG INPUT.................................................................................................................................... 10 INTERNAL & EXTERNAL REFERENCE...................................................................................................... 12 DIGITAL INTERFACE ............................................................................................................................. 12 POWER DISSIPATION ........................................................................................................................... 16
3 4 5 6 7
LAYOUT .................................................................................................................................................. 16 PACKAGE DRAWING ............................................................................................................................. 18 ORDERING INFORMATION.................................................................................................................... 19 ZMD DISTRIBUTION PARTNER ............................................................................................................. 19 ZMD CONTACT....................................................................................................................................... 19
Important Notice:
The information furnished herein by ZMD is believed to be correct and accurate as of the publication date. However, ZMD shall not be liable to any party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business, or indirect, special, incidental, or consequential damages of any kind in connection with or arising out of the furnishing, performance, or use of the technical data. No obligation or liability to any third party shall arise from ZMD's rendering technical or other services. Products sold by ZMD are covered exclusively by the ZMD's standard warranty, patent indemnification, and other provisions appearing in ZMD's standard "Terms & Conditions". ZMD makes no warranty (express, statutory, implied and/or by description), including without limitation any warranties of merchantability and/or fitness for a particular purpose, regarding the information set forth in the materials pertaining to ZMD products, or regarding the freedom of any products described in such materials from patent and/or other infringement. ZMD reserves the right to discontinue production and change specifications and prices, make corrections, modifications, enhancements, improvements and other changes of its products and services at any time without notice. ZMD products are intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without additional mutually agreed-upon processing by ZMD for such applications. ZMD assumes no liability for application assistance or customer product design. Customers are responsible for their products and applications using ZMD components. SPI and QSPI are registered trademarks of Motorola, Inc. MICROWIRE is a registered trademark of National Semiconductor Corp. Please notice, that values specified as typical may differ from product to product. The values listed under min or max are guaranteed by design or test.
Copyright (c) 2008, ZMD AG, Rev. 1.1 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.
2/19
Datasheet ZADCS146 / ZADCS147
1 General Device Specification
1.1 Absolute Maximum Ratings (Non Operating)
Table 1: Absolute Maximum Ratings
Symbol VDD-GND VAGND-DGND Parameter VDD to AGND, DGND AGND to DGND CH0 - CH7, COM to AGND, DGND VREF, VREFADJ to AGND Digital Inputs to DGND Digital Outputs to DGND Digital Output Sink Current Iin VHBM qJCT qOP qSTG qlead H Ptot Rthj Input current into any pin except supply pins (Latch-Up) Electrostatic discharge - Human Body Model (HBM) Maximum Junction Temperature Operating Temperature Range ZADCS146VIS20 / ZADCS147IS20 Storage temperature Lead Temperature 100%Sn Humidity non-condensing Total power dissipation Thermal resistance of Package SSOP20 / 5.3mm
1 2
Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -100 2000
Max 6 0.3 VDD+0.3 VDD+0.3 6 VDD+0.3 25 100 +150
Unit V V V V V V mA mA V C C C C
Note
1
-25 -65
+85 +150
JEDEC-J-STD-20C 260 250 100
2
mW K/W
HBM: C = 100pF charged to VHBM with resistor R = 1.5kW in series, valid for all pins Level 4 according to JEDEC-020A is guaranteed
Copyright (c) 2008, ZMD AG, Rev. 1.1 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.
3/19
Datasheet ZADCS146 / ZADCS147
1.2
Package Pin Assignment
Table 2: Pin list
Package pin number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM nSHDN VREF REFADJ AGND DGND DOUT SSTRB DIN nCS SCLK VDD OUT OUT IN IN IN Direction IN IN IN IN IN IN IN IN IN IN I/O I/O Type Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog SUPPLY SUPPLY CMOS Digital CMOS Digital CMOS Digital CMOS Digital CMOS Digital SUPPLY Description Analog Input Channel 0 Analog Input Channel 1 Analog Input Channel 2 Analog Input Channel 3 Analog Input Channel 4 Analog Input Channel 5 Analog Input Channel 6 Analog Input Channel 7 Negative input reference (IN-) for analog inputs in SingleEnded Mode Active Low Shutdown Reference Buffer Output / External Reference Input Input to Reference Buffer Amplifier / Not connected at ZADCS147 Analog Ground Digital Ground Serial Data Output Serial Strobe Output Serial Data Input Active Low Chip Select Serial Clock Input Positive Supply Voltage
CH0 CH1
VDD SCLK
ZADCS 146 / ZADCS 147
CH2 CH3 CH4 CH5 CH6 CH7 COM nSHDN
nCS DIN SSTRB DOUT DGND AGND REFADJ / n.c. for ZADCS147 VREF
Figure 1: Package Pin Assignment for ZADCS146 & ZADCS147
Copyright (c) 2008, ZMD AG, Rev. 1.1 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.
4/19
Datasheet ZADCS146 / ZADCS147
1.3
Electrical Characteristics
1.3.1 General Parameters
qOP = qOPmin ... qOPmax)
(VDD = +2.7V to + 5.25V; fSCLK = 3.2MHz (50% duty cycle); 16 clocks/conversion cycle (200 ksps); VREF = 2.500V applied to VREF pin;
Parameter DC Accuracy
Resolution Relative Accuracy No Missing Codes Differential Nonlinearity Offset Error Gain Error Gain Temperature Coefficient Signal-to-Noise + Distortion Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Small-Signal Bandwidth
Symbol Conditions
Min
Typ
12
Max
Unit
Bits
ZADCS146 / ZADCS147 NMC ZADCS146 / ZADCS147 0.5 0.5 0.25 SINAD THD SFDR -3dB roll off Ext. Clock = 3.2MHz, 2.5 clocks/ acquisition Ext. Clock = 3.2MHz, 12 clocks/ conversion Int. Clock = 3.2MHz +/- 12% tolerance 3.30 30 < 50 0.1 2.81 3.2 Up to the 5 harmonic 74
th
1.0 12 1.0 3.0 4.0
LSB Bits LSB LSB LSB ppm/C dB
Dynamic Specifications (10kHz sine-wave input, 0V to 2.500Vpp, 200ksps, 3.2MHz external clock)
68 73 -88 80 3.8 -75 dB dB MHz
Conversion Rate
Sampling Time (= Track/Hold Acquisition Time) Conversion Time Aperture Delay Aperture Jitter External Clock Frequency Internal Clock Frequency tACQ tCONV 0.781 3.75 4.20 s s s ns ps 3.2 3.58 MHz MHz
Analog Inputs
Input Voltage Range, SingleEnded and Differential Input Capacitance Unipolar, COM = 0V Bipolar, COM = VREF/2 0 to VREF VREF / 2 16 V pF
Copyright (c) 2008, ZMD AG, Rev. 1.1 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.
5/19
Datasheet ZADCS146 / ZADCS147
1.3.2 ZADCS146 Specific Parameters
(VDD = +2.7V to + 5.25V; fSCLK = 3.2MHz (50% duty cycle); 16 clocks/conversion cycle (200 ksps); qOP = qOPmin ... qOPmax)
Parameter Internal Reference at VREF
VREF Output Voltage VREF Short-Circuit Current VREF Temperature Coefficient Load Regulation Capacitive Bypass at VREF Capacitive Bypass at REFADJ REFADJ Adjustment Range
Symbol Conditions
Min
Typ
Max
Unit
TA = + 25C
2.480
2.500
2.520 30
V mA ppm/C mV F F
30 0 to 0.2mA output load 4.7 0.047 1.5 0.35
50
%
External Reference at VREF (internal buffer disabled by V(REFADJ) = VDD)
VREF Input Voltage Range VREF Input Current VREF Input Resistance Shutdown VREF Input Current REFADJ Buffer Disable Threshold VDD0.5 VREF = 2.5V 11.5 1.0 180 14 0.1 VDD + V 50mV 215 A kW A V
External Reference at VREF_ADJ
Reference Buffer Gain VREF_ADJ Input Current Full Power Down VREFADJ Input Current Full Power-Down mode 2.00 80 0.1 A A
Power Requirements
Positive Supply Voltage VDD Operating Mode ext. VREF Positive Supply Current IDD VDD=3.6V Operating Mode int. VREF Fast Power-Down int. VREF Full Power-Down Operating Mode ext. VREF Positive Supply Current IDD VDD=5.25V Operating Mode int. VREF Fast Power-Down Full Power-Down 2.7 0.85 1.3 250 0.5 1.00 1.40 250 0.5 5.25 1.0 1.4 300 4.0 1.3 1.6 300 4.0 V mA mA A mA mA A
Copyright (c) 2008, ZMD AG, Rev. 1.1 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.
6/19
Datasheet ZADCS146 / ZADCS147
1.3.3 ZADCS147 Specific Parameters
(VDD = +2.7V to + 5.25V; fSCLK = 3.2MHz (50% duty cycle); 16 clocks/conversion cycle (200 ksps); qOP = qOPmin ... qOPmax)
Parameter External Reference at VREF
VREF Input Voltage Range VREF Input Current VREF Input Resistance Shutdown VREF Input Current Capacitive Bypass at VREF
Symbol Conditions
Min
Typ
Max
Unit
1.0 VREF = 2.5V 11.5 180 14
VDD + V 50mV 215 A kW 0.1 A F
4.7
Power Requirements
Positive Supply Voltage Positive Supply Current VDD IDD VDD = 3.6V VDD 5.25V Operating Mode Full Power-Down 2.7 0.85 0.5 1.00 0.5 5.25 1.0 4.0 1.3 4.0 V A
Positive Supply Current
IDD
= Operating Mode Full Power-Down
A
1.3.4 ZADCS146 / ZADCS147 Digital Pin Parameters
(VDD = +2.7V to + 5.25V; fSCLK = 3.2MHz (50% duty cycle); 16 clocks/conversion cycle (200 ksps); qOP = qOPmin ... qOPmax)
Parameter
Symbol Conditions
Min
Typ
Max
Unit
Digital Inputs (DIN, SCLK, CS, nSHDN)
Logic High Level VIH VIL VHyst IIN IIN_nSHDN CIN VIN = 0V or VDD VIN = 0V 5 VDD = 2.7V VDD = 5.25V VDD = 2.7V VDD = 5.25V 0.7 0.1 1.0 - 5.0 1.9 3.3 0.7 1.4 V V V V V A A pF
Logic Low Level Hysteresis Input Leakage Input Low Leakage @ nSHDN Input Capacitance
Digital Outptus (DOUT, SSTRB)
Output High Current IOH IOL ILeak COUT VOH= VDD - 0.5V VOL= 0.4V nCS = VDD nCS = VDD VDD = 2.7V VDD = 5.25V VDD = 2.7V VDD = 5.25V 3.5 5.5 4 6.4 0.1 5 8.5 10.8 11.5 15.3 1.0 mA mA mA mA A pF
Output Low Current Three-State Leakage Current
Three-State Output Capacitance
Copyright (c) 2008, ZMD AG, Rev. 1.1 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.
7/19
Datasheet ZADCS146 / ZADCS147
1.4
Typical Operating Characteristics
Integral Nonlinearity vs. Code Differential Nonlinearity vs. Code
1 0.8 0.6 0.4 DNL (LSB) 0 512 1024 1536 2048 Code 2560 3072 3584 4096 INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1
1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 512 1024 1536 2048 Code 2560 3072 3584 4096
Offset Error vs. VDD 0 -0.5 Offset Error (LSB) -1 -1.5 -2 -2.5 -3 2.7 3.4 4.1 VDD (V) 4.8 5.5 Offset Error (LSB) -1.5 -1.6 -1.7 -1.8 -1.9 -2 -2.1 -2.2 -50 -25
Offset Error vs. Temperatur
0
25
50
75
100
Temperature (C)
Gain Error vs. VDD 0 -0.05 -0.1 Gain Error (LSB) -0.15 -0.2 -0.25 -0.3 -0.35 -0.4 -0.45 2.7 3.4 4.1 VDD (V) 4.8 5.5
Gain Error (LSB) 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -50 -25
Gain Error vs. Temperatur
0
25
50
75
100
Temperature (C)
Copyright (c) 2008, ZMD AG, Rev. 1.1 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.
8/19
Datasheet ZADCS146 / ZADCS147
(VDD = +5.0V; fSample = 200kHz, fCLK = 16* fSample = 3.2MHz; VREF = 2.500V applied to VREF pin; qOP = +25C)
Frequency Spectrum fIN = 1kHz, 4096 Point FFT
20 20
Frequency Spectrum fIN = 10kHz, 4096 Point FFT
0 -20
0 -20
Amplitude (dB)
-40 -60 -80 -100 -120 -140 0 10 20 30 40 50 60 70 80 90 100
Amplitude (dB)
-40 -60 -80 -100
-120
-140 0 10 20 30 40 50 60 70 80 90 100
Frequency (kHz)
Frequency (kHz)
IDD vs. VDD 1500 1350 1200 1050
IDDactive (converting)
IDDstatic vs. Temperature ZADCS146 with internal reference at VDD = 3.3V 700
650 IDD (A)
IDD (A)
900 750 600 450 300 150 0 2.7 3.4 4.1 VDD (V) 4.8 5.5
External VREF Internal VREF IDDstatic
600
550
500 -40 -20 0 20 40 60 80 100 Temperatur (C)
IDDactive (converting) vs. Temperature ZADCS146 with internal reference at VDD = 3.3V 1050 2.501
VREF vs. Temperature
2.500 1000 IDD (A)
Reference Voltage (v)
2.499
2.498
950
2.497
900 -40 -20 0 20 40 60 80 100 Temperatur (C)
2.496 -25 0 25 Tem perature (C) 50 75
Copyright (c) 2008, ZMD AG, Rev. 1.1 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.
9/19
Datasheet ZADCS146 / ZADCS147
2 DETAILED DESCRIPTION
2.1 General Operation
The ZADCS146 / ZADCS147 are classic successive approximation register (SAR) type converters. The architecture is based on a capacitive charge redistribution DAC merged with a resistor string DAC building a hybrid converter with excellent monotonicity and DNL properties. The Sample & Hold function is inherent to the capacitive DAC. This avoids additional active components in the signal path that could distort the input signal or introduce errors. Both devices ZADCS146 / ZADCS147 build on the same converter core and differ only in the availability of an internal reference voltage generator. ZADCS146 is equipped with a highly accurate internal 1.25V bandgap reference which is available at the VREFADJ pin. The bandgap voltage is further amplified by an internal buffer amplifier to 2.50V that is available at pin VREF. ZADCS147 comes without the internal reference and the internal buffer amplifier. It requires an external reference supplied at VREF, with the benefit of considerably lower power consumption. A basic application schematic of ZADC146 is shown in Figure 2, for ZADC147 in Figure 3. ZADCS146 can also be operated with an external reference, if VREFADJ is tied to VDD. Table 3: Channel selection in Single Ended Mode (SGL/DIF = HIGH)
A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 IN+ IN+ IN+ IN+ IN+ IN+ IN+ IN+ ININININININININ-
2.2
Analog Input
The analog input to the converter is fully differential. Both converter input signals IN+ and IN- (see Functional Block diagram at front page) get sampled during the acquisition period enabling the converter to be used in fully differential applications where both signals can vary over time. The ZADCS146 / ZADCS147 converters do not require that the negative input signal be kept constant within 0.5LSB during the entire conversion as is commonly required by converters featuring pseudo differential operation only. The input signals can be applied single ended, referenced to the COM pin, or differential, using four pairs of the eight input channels. The desired configuration is selectable for every conversion via the Control-Byte received on DIN pin of the digital interface (see further description below) A block diagram of the input multiplexer is shown in Figure 4. Table 3 and Table 4 show the relationship of the Control-Byte bits A2, A1, A0 and SGL/DIF to the configuration of the analog multiplexer. Both input signals IN+ and IN- are generally allowed to swing between -0.2V and VDD+0.2V. However, depending on the selected conversion mode - uniploar or bipolar - certain input voltage relations can limit the output code range of the converter. In unipolar mode the voltage at IN+ must exceed the Table 4: Channel selection in Differential Mode (SGL/DIF = LOW)
A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 0 1 0 1 0 1 0 1 ININ+ ININ+ ININ+ ININ+ IN+ ININ+ ININ+ ININ+ IN-
Figure 2: Basic application schematic for ZADCS146
Single-ended or differential analog inputs, 0V ... +2.5V +2.7V to 5.25V 0.1F
C
Figure 3: Basic application schematic for ZADCS147
+2.7V to 5.25V Single-ended or differential analog inputs, 0V ... +2.5V
ZADCS147
1 CH0 VDD 20 SCLK 19 nCS 18 DIN 17 SSTRB 16 DOUT 15 DGND 14 AGND 13 n.c. 12 VREF 11 MISO SCK I/O MOSI
10F
0.1F
C
10F
ZADCS146
1 CH0 2 CH1 3 CH2 4 CH3 5 CH4 6 CH5 7 CH6 8 CH7 9 COM 10 nSHDN VDD 20 SCLK 19 nCS 18 DIN 17 SSTRB 16 DOUT 15 DGND 14 AGND 13 VREFADJ 12 VREF 11
SCK I/O MOSI
2 CH1 3 CH2 4 CH3 5 CH4
MISO
6 CH5 7 CH6
47nF
8 CH7 9 COM 10 nSHDN
4.7F
4.7F
Copyright (c) 2008, ZMD AG, Rev. 1.1 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.
10/19
Datasheet ZADCS146 / ZADCS147
Figure 4: Block diagram of input multiplexer
Shown configuration A2 ... A0 = 0x000 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
Figure 5: Input voltage range in unipolar mode
VIN+ 1.5*VREF 0xFFF VREF Code Range
IN+ Converter IN-
0.5*VREF 0x000 0V VDD-VREF VIN-
Figure 6: Input voltage range for fully differential signals in bipolar mode
VCM VREF 3/4 VREF VCM COM See Table 3 & Table 4 for Coding Schemes SGL/DIF = HIGH 0V -VREF/2 0V +VREF/2 VDIFF 1/4 VREF Range
voltage at IN- to obtain codes unequal to 0x000. The entire 12 bit transfer characteristic is then covered by IN+ if IN+ ranges from IN- to (IN- +Vref). Any voltage on IN+ > (IN- + Vref) results in code 0xFFF. Code 0xFFF is not reached, if (IN- +Vref) > VDD + 0.2V because the input voltage is clamped at VDD + 0.2V by ESD protection devices. The voltage at IN- can range from -0.2V ... 1/2 VREF without limiting the Code Range, assuming the fore mentioned VDD condition is true. See also Figure 5 for input voltage ranges in unipolar conversion mode. In bipolar mode, IN+ can range from (IN- - Vref/2) to (IN- + Vref/2) keeping the converter out of code saturation. For instance, if IN- is set to a constant DC voltage of Vref/2, then IN+ can vary from 0V to Vref to cover the entire code range. Lower or higher voltages of IN+ keep the output code at the minimum or maximum code value. Figure 6 shows the input voltage ranges in bipolar mode when IN- is set to a constant DC voltage. As explained before, ZADCS146 / ZADCS147 can also be used to convert fully differential input signals that change around a common mode input voltage. The bipolar mode is best used for such purposes since it allows the input signals to be positive or negative in relation to each other. The common mode level of a differential input signal is calculated VCM = (V(IN+)+ V(IN-)) / 2. To avoid code clipping or over steering of the converter, the common mode level can change from 1/4 Vref ... 3/4 Vref. Within this range
the peak to peak amplitude of the differential input signal can be Vref/2. The average input current on the analog inputs depends on the conversion rate. The signal source must be capable of charging the internal sampling capacitors (typically 16pF on each input of the converter: IN+ and IN-) within the acquisition time tACQ to the required accuracy. The equivalent input circuit in sampling mode is shown in Figure 7. The following equation provides a rough hand calculation for a source impedance RS that is required to settle out a DC input signal referenced to AGND with 12 bit accuracy in a given acquisition time
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM Channel Multiplexer
CHOLD+ IN+ CIN
4pF 16pF AGND
RSW
3k
CHOLDINCIN
4pF 16pF AGND
RSW
3k
VDC
Figure 7: Equivalent input circuit during sampling
Copyright (c) 2008, ZMD AG, Rev. 1.1 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.
11/19
Datasheet ZADCS146 / ZADCS147
RS t ACQ - R SW 9 CIN This reduces power consumption of the ZADCS146 and allows the supply of an external reference at VREF. ZADCS147 does not contain the internal bandgap or the VREF buffer. An external reference must be supplied all the time at VREF. The value of the reference voltage at VREF sets the input range of the converter and the analog voltage weight of each digital code. The size of the LSB (least significant bit) is equal to the value of VREF (reference to AGND) divided by 4096. For example at a reference voltage of 2.500V, the voltage level of a LSB is equal to 610V. It is important to know that certain inherent errors in the A/D converter, like offset or gain error, will appear to increase at lower reference voltages while the actual performance of the device does not change. For instance a static offset error of 1.22mV is equal to 2 LSB at 2.5V reference, while it is equivalent to 5.0 LSB for a reference voltage of 1.0V Likewise, the uncertainty of the digitized output code will increase with lower LSB size (lower VREF). Once the size of an LSB is below the internal noise level, the output code will start to vary around a mean value for constant DC input voltages. Such noise can be reduced by averaging consecutive conversions or applying a digital filter. The average current consumption at VREF depends on the value of VREF and the sampling frequency. Two effects contribute to the current at VREF, a resistive connection from VREF to AGND and charge currents that result from the switching and recharging of the capacitor array (CDAC) during sampling and conversion. For an external reference of 2.5V the input current at VREF is approximately 100A.
For example, if fSCLK = 3.2MHz, the acquisition time is tACQ = 781.25ns. Thus the output impedance of the signal source RS must be less than
RS 781.25ns - 3k = 1.34k 9 20pF
If the output impedance of the source is higher than the calculated maximum RS the acquisition time must be extended by reducing fSCLK to ensure 12 bit accuracy. Another option is to add a capacitor of >20 nF to the individual input. Although this limits the bandwidth of the input signal because an RC low pass filter is build together with the source impedance, it may be useful for certain applications. The small-signal bandwidth of the input tracking circuitry is 3.8 MHz. Hence it is possible to digitize high-speed transient events and periodic signals with frequencies exceeding the ADC's sampling rate. This allows the application of certain under-sampling techniques like down conversion of modulated high frequency signals. Be aware that under-sampling techniques still require a bandwidth limitation of the input signal to less than the Nyquist frequency of the converter to avoid aliasing effects. Also, the output impedance of the input source must be very low to achieve the mentioned small signal bandwidth in the overall system.
2.3
Internal & External Reference
ZADCS146 is equipped with a highly accurate internal 2.5V reference voltage source. The voltage is generated from a trimmed 1.25V bandgap with an internal buffer that is set to a gain of 2.00. The bandgap voltage is supplied at VREFADJ with an output impedance of 20k. An external capacitor of 47nF at VREFADJ is useful to further decrease noise on the internal reference. The VREFADJ pin also provides an opportunity to externally adjust the bandgap voltage in a limited range (see Figure 8) as well as the possibility to overdrive the internal bandgap with an external 1.25V reference. Figure 8: Reference Adjust Circuit
VDD = +2.7V ... +5.25V
2.4
Digital Interface
ZADCS146 510k VREFADJ 47nF
The internal bandgap reference and the VREF buffer can be shut down completely by setting VREFADJ to VDD.
ZADCS146 and ZADCS147 are both controlled by a 4-wire serial interface that is compatible to SPITM, QSPITM and MICROWIRETM devices without external logic. Any conversion is started by sending a control byte into DIN while nCS is low. A typical sequence is shown in Figure 9. The control byte defines the input channel(s), unipolar or bipolar operation and output coding, single-ended or differential input configuration, external or internal conversion clock and the kind of power down that is activated after the completion of a conversion. A detailed description of the control bits can be obtained from Table 5. As it can also be seen in Figure 9 the acquisition of the input signal occurs at the end of the control byte for 2.5 clock cycles. Outside this range, the Track & Hold is in hold mode. The conversion process is started, with the falling clock edge (SCLK) of the eighth bit in the control byte. It takes twelve clock cycles to complete the conversion and one additional cycle to shift out the last bit of the conversion result. During the remaining three clock cycles the output is filled with zeros in 24-Clock Conversion Mode. Depending on what clock mode was selected, either the external SPI clock or an internal clock is used to drive the successive approximation. Figure 10 shows the Timing for Internal Clock Mode.
Copyright (c) 2008, ZMD AG, Rev. 1.1 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.
12/19
Datasheet ZADCS146 / ZADCS147
Figure 9: 24-Clock External Clock Mode Timing (SPITM, QSPITM and MICROWIRETM compatible, fSCLK 3.2MHz)
nCS
tACQ
SCLK DIN SSTRB DOUT
1
8
1
8
1
8
S (Start)
A2
A1
A0 BIP DIF PD1 PD0 Acquire Conversion Idle
UNI/ SGL/
Idle
B11 B10 B9 (MSB)
B8
B7
B6
B5
B4
B3
B2
B1
B0 (LSB)
Zero filled
Figure 10: Internal Clock Mode Timing with interleaved Control Byte transmission
nCS SCLK DIN
1 8 1 8 1 8
S (Start)
A2
A1
A0 BIP DIF PD1 PD0 Acquire Conversion Result Output
UNI/ SGL/
S
A2
A1
A0 BIP DIF PD1 PD0 Acquire
UNI/ SGL/
Idle
SSTRB
tCONV
DOUT
B11 B10 B9 (MSB)
B8
B8
B6
B5
B4
B3
B2
B1
B0 (LSB)
Zero filled
Table 5: Control Byte Format BIT 7 (MSB) 6 5 4 3 Name START A2 A1 A0 UNI/BIP Description The Start Bit is defined by the first logic `1' after nCS goes low. Channel Select Bits. Along with SGL/DIF these bits control the setting of the input multiplexer. For further details on the decoding see also Table 3 and Table 4. Output Code Select Bit. The value of the bit determines conversion mode and output code format. `1' = unipolar - straight binary coding `0' = bipolar - two's complement coding Single-Ended / Differential Select Bit. Along with the Channel Select Bits A2 .. A0 this bit controls the setting of the input multiplexer `1' = single ended - all channels CH0 ... CH7 measured referenced to COM `0' = differential - the voltage between two channels is measured Power Down and Clock Mode Select Bits PD1 PD0 Mode 0 0 Full Power-Down 0 1 Fast Power-Down 1 0 Internal clock mode 1 1 External clock mode
2
SGL/DIF
1 0 (LSB)
PD1 PD0
Copyright (c) 2008, ZMD AG, Rev. 1.1 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.
13/19
Datasheet ZADCS146 / ZADCS147
Figure 11: 16-Clock External Clock Mode Conversion
nCS SCLK DIN SSTRB DOUT
B11 B10 B9 (MSB) B8 B7 B6 B5 B4 B3 B2 B1 B0 (LSB) Zero filled B11 B10 1 8 1 8 1 8 1
S (Start)
A2
A1
A0 BIP DIF PD1 PD0 Acquire Conversion
UNI/ SGL/
S
A2
A1
A0 BIP DIF PD1 PD0 Idle Acquire
UNI/ SGL/
Idle
Figure 12: 15-Clock External Clock Mode Conversion
nCS SCLK DIN SSTRB DOUT
B11 B10 B9 (MSB) B8 B7 B6 B5 B4 B3 B2 B1 B0 (LSB) Zero filled B11 B10 B9 B8 B7 B6 B5 B4 1 8 15 1 15 1
S (Start)
A2
A1
A0 BIP DIF PD1 PD0 Acquire Conversion
UNI/ SGL/
S
A2
A1
A0 BIP DIF PD1 PD0 Acquire Conversion
UNI/ SGL/
S
A2
Idle
Internal Clock Mode
In Internal Clock Mode, the conversion starts at the falling clock edge of the eighth control bit just as in External Clock Mode. However, there are no further clock pulses required at SCLK to complete the conversion. The conversion clock is generated by an internal oscillator that runs at approximately 3.2MHz. While the conversion is running, the SSTRB signal is driven LOW. As soon as the conversion is complete, SSTRB is switched to HIGH, signaling that the conversion result can be read out on the serial interface. To shorten cycle times ZADCS146 and ZADCS147 allow interleaving of the read out process with the transmission of a new control byte. Thus it is possible to read the conversion result and to start a new conversion with just two consecutive byte transfers, instead of thee bytes that would have to be send without the interleaving function. While the IC is performing a conversion in Internal Clock Mode, the Chip Select signal (nCS) may be tied HIGH allowing other devices to communicate on the bus. The output driver at DOUT is switched into a high impedance state while nCS is HIGH. The conversion time tCONV may vary in the specified limits depending on the actual VDD and temperature values.
16-Clocks per Conversion
Interleaving of the data read out process and transmission of a new Control Byte is also supported for External Clock Mode operation. Figure 11 shows the transmission timing for conversion runs using 16 clock cycles per run. In fact, the specified converter sampling rate of 200ksps will be reached in this mode, provided the clock frequency is set to 3.2MHz.
15-Clocks per Conversion
ZADS146 and ZADCS147 do also support a 15 clock cycle conversion mode (see Figure 12). This is the fastest conversion mode possible. Usually micro controllers do not support this kind of 15 bit serial communication transfers. However, specifically designed digital state machines implemented in Field Programmable Gate Arrays (FPGA) or Application Specific Integrated Circuits (ASIC) may use this operation mode. Applications that utilize the 15 clock cycle conversion mode gain an increase in sampling rate to 213.3ksps keeping the clock frequency unchanged at 3.2MHz.
Digital Timing
In general the clock frequency at SCLK may vary from 0.1MHz to 3.2MHz. Considering all telegram pauses or other interruptions of a continuous clock at SCLK, each conversion must be completed within 1.2ms from the
Copyright (c) 2008, ZMD AG, Rev. 1.1 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.
14/19
Datasheet ZADCS146 / ZADCS147
Table 6: ZADCS146 / ZADCS147 Timing Characterisitics (VDD = +2.7V to + 5.25V; qOP = qOPmin ... qOPmax)
Parameter
SCLK Periode SCLK Pulse Width High SCLK Pulse Width Low DIN to SCLK Setup DIN to SCLK Hold nCS Fall to SCLK Setup SCLK Fall to DOUT & SSTRB Hold SCLK Fall to DOUT & SSTRB Valid nCS Rise to DOUT & SSTRB Disable nCS Fall to DOUT & SSTRB Enable nCS Pulse Width High
Symbol Conditions
tSCLK tSCLKhigh tSCLKlow tDinSetup tDinHold tnCSSetup tOutHold tOutValid tOutDisable tOutEnable tnCSHigh CLoad = 20pF CLoad = 20pF CLoad = 20pF CLoad = 20pF
Min
312.50 156.25 156.25 30 10 30 10
Typ
Max
Unit
ns ns ns ns ns ns ns
40 10 60 60 100
ns ns ns ns
Figure 13: Detailed Timing Diagram
nCS
tnCSSetup tSCLKhigh tSCLK tSCLKlow tOutValid
SCLK
tDINsetup tDINhold
DIN
tOutEnable tnCSHigh tOutDisable
SSTRB
tOutEnable
tOutHold
DOUT
falling clock edge of the eighth bit in the Control Byte. Otherwise the signal that was captured during sample/hold may drop to noticeable affect the conversion result. Further detailed timing information on the digital interface is provided in Table 6 and Figure 13.
voltage difference of VREF (Full Scale = FS). The first code transition (0x000 a 0x001) occurs at a voltage equivalent to 1/2 LSB, the last (0xFFE a 0xFFF) at VREF - 1.5 LSB. See also Figure 14 for details. In bipolar mode a two's complement coding is applied. Code transitions occur again halfway between successive integer LSB values. The transfer function is shown in Figure 15.
Output Code Format
ZADCS146 and ZADCS147 both support unipolar and bipolar operation modes. The digital output code is straight binary in unipolar mode. It ranges from 0x000 for an input voltage difference of 0V to 0xFFF for an input
Copyright (c) 2008, ZMD AG, Rev. 1.1 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.
15/19
Datasheet ZADCS146 / ZADCS147
Figure 14: Unipolar Transfer Function
Output Code
11 ... 111 11 ... 110 11 ... 101
Figure 15: Bipolar Transfer Function
Output Code ZS = V(IN-) + FS = 1/2VREF +V(IN-) - FS = -1/2VREF +V(IN-) VREF 1LSB = 4096
01 ... 111 01 ... 110
ZS = V(IN-) FS = VREF +V(IN-) VREF 1LSB = 4096
00 ... 011 00 ... 001 00 ... 000 11 ... 111 11 ... 110 11 ... 101
00 ... 010 00 ... 001 00 ... 000 01 (ZS) 2 3 FS 10 ... 001 10 ... 000 -FS ZS +FS
+FS-3/2 LSB
Input Voltage (LSB)
FS-3/2 LSB
Input Voltage (LSB)
2.5
Power Dissipation
Hardware Power Down
The third power down mode is called Hardware PowerDown. It is initiated by pulling the nSHDN pin LOW. If this condition is true, the device will immediately shut down all circuitry just as in Full Power Down-Mode. The IC wakes up if nSHDN is tied HIGH. There is no internal pull-up that would allow nSHDN to float during normal operation. This ensures the lowest possible power consumption in power down mode.
ZADCS146 and ZADCS147 offer three different ways to save operating current between conversions. Two different software controlled power down modes can be activated to automatically shut-down the device after completion of a conversion. They differ in the amount of circuitry that is powered down.
Software Power Down
Full Power Down Mode shuts down the entire analog part of the IC, reducing the static IDD of the device to less than 0.5A if no external clock is provided at SCLK. Fast Power Down mode is only useful with ZADCS146 if the internal voltage reference is used. During Fast PowerDown the bandgap and the VREFADJ output buffer are kept alive while all other internal analog circuitry is shut down. The benefit of Fast Power Down mode is a shorter turn on time of the reference compared to Full Power Down Mode. This is basically due to the fact that the low pass which is formed at the VREFADJ output by the internal 20k resistor and the external buffer capacitor of 47nF is not discharged in Fast Power Down Mode. The settling time of the low pass at VREFADJ is about 9 ms to reach 12 bit accuracy. The Fast Power Down mode omits this settling and reduces the turn on time to about 200s. To wake up the IC out of either software power down mode, it is sufficient to send a Start Bit while nCS is LOW. Since micro controllers can commonly transfer full bytes per transaction only, a dummy conversion is usually carried out to wake the device. In all application cases where an external reference voltage is supplied (ZADCS147 and ZADCS146 with VREFADJ tied to VDD) there is no turn on time to be considered. The first conversion is already valid. Fast PowerDown and Full Power-Down Mode do not show any difference in this configuration.
General Power Considerations
Even without activating any power down mode, ZADCS146 and ZADCS147 reduce their power consumption between conversions automatically. The comparator, which contributes a considerable amount to the overall current consumption of the device is shut off as soon as a conversion is ended. It gets turned on at the start of the next acquisition period. This explains the difference between the IDDstatic and IDDactive measurements shown in chapter 1.4 Typical Operating Characteristics. The average current consumption of the device depends very much on the sampling frequency and the type of protocol used to communicate with the device. In order to achieve the lowest power consumption at low sampling frequencies, it is suggested to keep the conversion clock frequency at the maximum level of 3.2MHz and to power down the device between consecutive conversions. Figure 16 shows the characteristic current consumption of ZADCS146 and ZADCS147 with external reference supply versus Sampling Rate
3 Layout
To achieve optimum conversion performance care must be taken in design and layout of the application board. It is highly recommended to use printed circuit boards instead of wire wrap designs and to establish a single point star connection ground system towards AGND (see Figure 17).
Copyright (c) 2008, ZMD AG, Rev. 1.1 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.
16/19
Datasheet ZADCS146 / ZADCS147
Figure 16: Average Supply Current versus Sampling Rate
Current consumption vs. Sample Rate External Clock Mode, External VREF, fSCLK = 3.2MHz 1000 Average Supply Current (A)
Figure 17: Optimal Power-Supply Grounding System
Optional R = 10 VDD VDD1
(+2.7 ... +5.25V)
ZADCS146 ZADCS147
100
AGND COM
10
DGND
1 1 10 100 1000 Sample Rate (ksps)
Other Digital Circuitry
DGND DVDD
GND VDD2
For optimal noise performance the star point should be located very close to the AGND pin of the converter. The ground return to the power supply should be as short as possible and low impedance. All other analog ground points of external circuitry that is related to the A/D converter as well as the DGND pin of the device should be connected to this ground point too. Any other digital ground system should be kept apart as far as possible and connect on the power supply point only. Analog and digital signal domains should also be separated as well as possible and analog input signals should be shielded by AGND ground planes from electromagnetic interferences. Four-layer PCB boards that allow smaller vertical distances between the ground plane and the shielded signals do generally show a better performance than two-layer boards. The sampling phase is the most critical portion of the overall conversion timing for signal distortion. If possible, the switching of any high power devices or nearby digital logic should be avoided during the sampling phase of the converter.
The fully differential internal architecture of ZADCS146 and ZADCS147 ensures very good suppression of power supply noise. Nevertheless, the SAR architecture is generally sensitive to glitches or sudden changes of the power supply that occur shortly before the latching of the comparator output. It is therefore recommended to bypass the power supply connection very close to the device with capacitors of 0.1F (ceramic) and >1F (electrolytic). In case of a noisy supply, an additional series resistor of 5 to 10 ohms can be used to low-pass filter the supply voltage. The reference voltage should always be bypassed with capacitors of 0.1F (ceramic) and 4.7F (electrolytic) as close as possible to the VREF pin. If VREF is provided by an external source, any series resistance in the VREF supply path can cause a gain error of the converter. During conversion, a DC current of about 100A is drawn through the VREF pin that could cause a noticeable voltage drop across the resistance.
Copyright (c) 2008, ZMD AG, Rev. 1.1 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.
Power Supplies
17/19
Datasheet ZADCS146 / ZADCS147
4 Package Drawing
The IC is packaged in a 20 pin SSOP-package that has the dimensions as shown in Figure 18 and Table 7. Figure 18: Package Outline Dimensions
Table 7: Package Dimensions (mm) Symbol Nominal Maximum Minimum A 1.86 1.99 1.73 A1 0.13 0.21 0.05 A2 1.73 1.78 1.68 bP 0.30 0.38 0.25 c 0.15 0.20 0.09 D 7.20 7.33 7.07 E 5.30 5.38 5.20 0.65 enom HE 7.80 7.90 7.65 0.63 0.74 0.25 LP Z k Q 4 8 0
Copyright (c) 2008, ZMD AG, Rev. 1.1 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.
18/19
Datasheet ZADCS146 / ZADCS147
5 Ordering Information
Temperature range [C] Sample Rate [ksps] Internal Vref Resolution [Bit] Channels [number] Pins [number] QC 100 Qualified Order Code Package [Type]
ZADCS146VIS20T ZADCS147IS20T
12 12
8 8
200 200
-25C to +85C -25C to +85C
---
u --
1 LSB 1 LSB
1 LSB 1 LSB
20 20
SSOP Tube SSOP Tube
6 ZMD Distribution Partner
ZMD ADC products as well as the ZADCS146/ZADCS147 Starterkit can be purchased from RUTRONIK Elektronische Bauelemente GmbH. RUTRONIK Elektronische Bauelemente GmbH
Industriestrasse 2 78228 Ispringen, Germany Phone: +49 7231 801-0 Fax: +49 7231 82282 E-mail: rutronik@rutronik.com Internet: www.rutronik.com
7 ZMD Contact
ZMD AG, Headquarters
Grenzstrae 28 D-01109 Dresden Phone: Fax: +49 351 88227 -ADC (-232) +49 351 882278 -ADC (-232)
E-mail: SARah@zmd.de Internet: www.zmd.biz/ADC
ZMD America Inc., New York
201 Old Country Road, Suite 204 Melville, NY 11747
ZMD Far East, Hsinchu City
1F, No14, Lane 268 Sec. 1 Guangfu Rd. Hsinchu City 300, Taiwan
ZMD AG, Tokyo
212-0061 7-6-10-103 Hanahata, Adachi Tokyo, Japan Phone: Fax: +81 3 6805 0669 +81 2 6805 0669
Phone.: Fax:
+1 631 549 2666 +1 631 549 2882
Phone: Fax:
+886 03 563 1388 +886 03 563 6385
For the most current revision of this document and for additional product information please visit www.zmd.biz/ADC.
Copyright (c) 2008, ZMD AG, Rev. 1.1 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.
19/19
packing
DNL
INL

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