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PROTECTION PRODUCTS Description
RailClamps are surge rated diode arrays designed to protect high speed data interfaces. The SR series has been specifically designed to protect sensitive components which are connected to data and transmission lines from overvoltage caused by electrostatic discharge (ESD), electrical fast transients (EFT), and tertiary lightning. The unique design of the SR series devices incorporates four surge rated, low capacitance steering diodes, and a TVS diode in a single package. The TVS diode is constructed using Semtech's proprietary low voltage EPD technology for superior electrical characteristics at 2.8 volts. During transient conditions, the steering diodes direct the transient to either the positive side of the power supply line or to ground. The internal TVS diode prevents over-voltage on the power line, protecting any downstream components. The low capacitance array configuration allows the user to protect two high-speed data or transmission lines. The low inductance construction minimizes voltage overshoot during high current surges.
RailClamp Low Capacitance TVS Diode Array
Features
ESD protection to IEC 61000-4-2 (ESD) 15kV (air), 8kV (contact) IEC 61000-4-4 (EFT) 40A (5/50ns) IEC 61000-4-5 (Lightning) 12A (8/20s) Array of surge rated diodes with internal EPD TVS diode Protects two I/O lines Low capacitance (<10pF) for high-speed interfaces Low leakage current (< 1A) Low operating voltage: 2.8V Solid-state technology
SR2.8
Mechanical Characteristics
JEDEC SOT-143 package Molding compound flammability rating: UL 94V-0 Marking : R2.8 Packaging : Tape and Reel
Applications
Firewire Sensitive Analog Inputs Video Line Protection Portable Electronics Microcontroller Input Protection WAN/LAN Equipment
Circuit Diagram
Pin 4
Schematic & PIN Configuration
4 1
Pin 2
Pin 3
2
3
Pin 1
SOT-143 (Top View)
Revision 01/17/08 1 www.semtech.com
SR2.8
PROTECTION PRODUCTS Absolute Maximum Rating
R ating Peak Pulse Power (tp = 8/20s) Peak Pulse Current (tp = 8/20s) Peak Forward Voltage (IF = 1A, tp=8/20s) Lead Soldering Temperature Operating Temperature Storage Temperature Symbol Pp k IP P VFP TL TJ TSTG Value 200 14 1.5 260 (10 sec.) -55 to +125 -55 to +150 Units Watts A V C C C
Electrical Characteristics
SR 2.8 Parameter Reverse Stand-Off Voltage Punch-Through Voltage Snap-Back Voltage Reverse Leakage Current Clamping Voltage Clamping Voltage Junction Capacitance Symbol VRWM V PT VSB IR VC VC Cj IPT = 2A ISB = 50mA VRWM = 2.8V, T=25C IPP = 1A, tp = 8/20s IPP = 5A, tp = 8/20s Between I/O pins and Ground VR = 0V, f = 1MHz Between I/O pins VR = 0V, f = 1MHz 6 3.0 2.8 1 5.0 8.5 10 Conditions Minimum Typical Maximum 2.8 Units V V V A V V pF
3
pF
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SR2.8
PROTECTION PRODUCTS Typical Characteristics
Non-Repetitive Peak Pulse Power vs. Pulse Time
10 Peak Pulse Power - Ppk (kW)
Power Derating Curve
110 100 % of Rated Power or PP I 90 80 70 60 50 40 30 20 10 0
1
0.1
0.01 0.1 1 10 Pulse Duration - tp (s) 100 1000
0
25
50
75
100
125
150
Ambient Temperature - TA (oC)
Pulse Waveform
110 100 90 80 Percent of IPP 70 60 50 40 30 20 10 0 0 5 10 15 T im e (s) 20 25 30 td = I PP /2 e -t W aveform Parameters: tr = 8s td = 20s
Clamping Voltage vs. Peak Pulse Current
20 18 Clamping Voltage - V C (V) 16 14 12 10 8 6 4 2 0 0 5 10 Peak Pulse Current - IPP (A) 15 20 Waveform Parameters: tr = 8s td = 20s
Forward Voltage vs. Forward Current
10 9 Forward Voltage - VF (V) 8 7 6 5 4 3 2 1 0 0 5 10 15 20 25 30 35 40 45 50 Forward Current - IF (A) Waveform Parameters: tr = 8s td = 20s
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SR2.8
PROTECTION PRODUCTS Applications Information
Device Connection Options for Protection of Tw o High-Speed Data Lines The SR2.8 TVS is designed to protect two data lines from transient over-voltages by clamping them to a fixed reference. When the voltage on the protected line exceeds the reference voltage (plus diode VF) the steering diodes are forward biased, conducting the transient current away from the sensitive circuitry. Data lines are connected at pins 2 and 3. The negative reference (REF1) is connected at pin 1. This pin should be connected directly to a ground plane on the board for best results. The path length is kept as short as possible to minimize parasitic inductance. The positive reference (REF2) is connected at pin 4. The options for connecting the positive reference are as follows: Note that pins 4 is connected internally to the cathode of the low voltage TVS. It is not recommended that this pin be directly connected to a DC source greater than the snap-back votlage (VSB) as the device can latch on as described below. EPD TVS Characteristics These devices are constructed using Semtech's proprietary EPD technology. By utilizing the EPD technology, the SR2.8 can effectively operate at 2.8V while maintaining excellent electrical characteristics. The EPD TVS employs a complex nppn structure in contrast to the pn structure normally found in traditional silicon-avalanche TVS diodes. Since the EPD TVS devices use a 4-layer structure, they exhibit a slightly different IV characteristic curve when compared to conventional devices. During normal operation, the device represents a high-impedance to the circuit up to the device working voltage (VRWM). During an ESD event, the device will begin to conduct and will enter a low impedance state when the punch through voltage (VPT) is exceeded. Unlike a conventional device, the low voltage TVS will exhibit a slight negative resistance characteristic as it conducts current. This characteristic aids in lowering the clamping voltage of the device, but must be considered in applications where DC voltages are present. When the TVS is conducting current, it will exhibit a slight "snap-back" or negative resistance
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IPT VBRR IR VRWM V V VC SB PT
Pro Internal Data Line Pr o t ection Using Int ernal T V S Diode as Reference
IPP
ISB
IBRR
Figure 1 - EPD TVS IV Characteristic Curve characteristics due to its structure. This point is defined on the curve by the snap-back voltage (VSB) and snap-back current (ISB). To return to a nonconducting state, the current through the device must fall below the ISB (approximately <50mA) and the voltage must fall below the VSB (normally 2.8 volts for a 3.3V device). If a 3.3V TVS is connected to 3.3V DC source, it will never fall below the snap-back voltage of 2.8V and will therefore stay in a conducting state.
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SR2.8
PROTECTION PRODUCTS Applications Information (continued)
Board Layout Considerations for ESD Protection Board layout plays an important role in the suppression of extremely fast rise-time ESD transients. Recall that the voltage developed across an inductive load is proportional to the time PIN Descriptions rate of change of current through the load (V = L di/dt). The total clamping voltage seen by the protected load will be the sum of the TVS clamping voltage and the voltage due to the parasitic inductance (VC(TOT) = VC + L di/dt) . Parasitic inductance in the protection path can result in significant voltage overshoot, reducing the effectiveness of the suppression circuit. An ESD induced transient for example reaches a peak in approximately 1ns. For a 30A pulse (per IEC 61000-4-2 Level 4), 1nH of series inductance will increase the effective clamping voltage by 30V (V = 1x10-9 (30/1x10-9)). For maximum effectiveness, the following board layout guidelines are recommended: Minimize the path length between the SR3.3 and the protected line. Place the SR2.8 near the connector to restrict transient coupling in nearby traces. Minimize the path length (inductance) between the RJ45 connector and the SR2.8.
Matte Tin Lead Finish Matte tin has become the industry standard lead-free replacement for SnPb lead finishes. A matte tin finish is composed of 100% tin solder with large grains. Since the solder volume on the leads is small compared to the solder paste volume that is placed on the land pattern of the PCB, the reflow profile will be determined by the requirements of the solder paste. Therefore, these devices are compatible with both lead-free and SnPb assembly techniques. In addition, unlike other lead-free compositions, matte tin does not have any added alloys that can cause degradation of the solder joint.
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SR2.8
PROTECTION PRODUCTS Outline Drawing - SOT-143
D e e/2 4 3
B A H
DIM SEATING PLANE
C
GAUGE PLANE 0.25 L L1 DETAIL A
0
c
DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX
.031 .000 .029 .011 .029 .003 .110 .082 .047 1.22 .048 0.80 0.15 .006 0.013 .042 0.75 0.90 1.07 .020 0.30 0.51 .037 0.76 0.94 .008 0.08 0.20 .114 .120 2.80 2.90 3.04 .093 .104 2.10 2.37 2.64 .051 .055 1.20 1.30 1.40 .075 1.92 BSC .008 0.20 BSC .015 .020 .024 0.40 0.50 0.60 (.021) (0.54) 4 4 0 8 0 8 .006 0.15 .008 0.20 .004 0.10 .035 -
E1
E
1 e1
2 bxN bbb CAB SIDE VIEW SEE DETAIL A
A A1 A2 b b1 c D E E1 e e1 L L1 N 0 aaa bbb ccc
A2
A
4X
ccc C
SEATING PLANE b1 aaa CAB A1
C
NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A- AND -BTO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD TO-253, VARIATION D.
Land Pattern - SOT-143
X1 X1
Y
DIM
Z C G E1 E2
C E1 E2 G X1 X2 Y Z
DIMENSIONS INCHES MILLIMETERS
(.087) .076 .068 .031 .039 .047 .055 .141 (2.20) 1.92 1.72 0.80 1.00 1.20 1.40 3.60
Y
X2
X1
NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 2. REFERENCE IPC-SM-782A.
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SR2.8
PROTECTION PRODUCTS Marking Codes
Part Number SR2.8 Marking Code R2.8
Ordering Information
Par t Number SR2.8.TC SR2.8.TCT Lead Finish SnPb Pb Free Qty per Reel 3,000 3,000 R eel Size 7 Inch 7 Inch
Contact Information
Semtech Corporation Protection Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
2008 Semtech Corp. 7 www.semtech.com

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