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L6390
High-voltage high and low side driver
Features

High voltage rail up to 600 V dV/dt immunity 50 V/nsec in full temperature range Driver current capability: - 290 mA source, - 430 mA sink Switching times 75/35 nsec rise/fall with 1 nF load 3.3 V, 5 V TTL/CMOS inputs with hysteresis Integrated bootstrap diode Operational amplifier for advanced current sensing Comparator for fault protections Smart shut down function Adjustable dead-time Interlocking function Compact and simplified layout Bill of material reduction Effective fault protection Flexible, easy and fast design
SO-16
DIP-16

Description
The L6390 is a high-voltage device manufactured with the BCD "OFF-LINE" technology. It is a monolithic half-bridge gate driver for N-channel Power MOSFET or IGBT. The high side (floating) section is designed to stand a voltage rail up to 600 V. The logic inputs are CMOS/TTL compatible down to 3.3 V for easy interfacing microcontroller/DSP. The IC embeds an operational amplifier suitable for advanced current sensing in applications such as field oriented motor control. An integrated comparator is available for protections against over-current, over-temperature, etc.
Applications
Motor driver for home appliances, factory automation, industrial drives. HID ballasts, power supply units.
Table 1.
Device summary
Order codes L6390 L6390D L6390D013TR Package DIP-16 SO-16 SO-16 Packaging Tube Tube Tape and reel
July 2008
Rev 3
1/22
www.st.com 22
Contents
L6390
Contents
1 2 3 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.1 4.2 4.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1 5.2 AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6 7 8 9
Waveforms definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Smart shut down function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
9.1 CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
10 11
Package mecanichal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2/22
L6390
Block diagram
1
Block diagram
Figure 1. Block diagram
BOOTSTRAP DRIVER VCC 4 from LVG UV DETECTION 3 HIN FLOATING STRUCTURE 16 BOOT
UV DETECTION HVG DRIVER LEVEL SHIFTER S R 15 HVG
5V
LOGIC SHOOT THROUGH PREVENTION
14 OUT VCC LVG DRIVER LVG 11 5V COMPARATOR + + VREF 10 CP+
LIN
1
SD/OD
2 SMART SD
SD LATCH
GND
8
DT
5
DEAD TIME VCC OPAMP + 6 9 OP+ OP-
OPOUT
7
3/22
Pin connection
L6390
2
Pin connection
Figure 2. Pin connection (top view)
LIN SD/OD HIN VCC DT OPOPOUT GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 BOOT HVG OUT NC NC LVG CP+ OP+
Table 2.
Pin n # 1 2 3 4 5 6 7 8 9 10 11 12, 13 14 15 16
Pin description
Pin name LIN SD/OD (1) HIN VCC DT OPOPOUT GND OP+ CP+ LVG
(1)
Type I I/O I P I I O P I I O
Function Low side driver logic input (active low) Shut down logic input (active low)/open drain (comparator output) High side driver logic input (active high) Lower section supply voltage Dead time setting Opamp inverting input Opamp output Ground Opamp non inverting input Comparator input Low side driver output Not connected
NC OUT HVG
(1)
P O P
High side (Floating) common voltage High side driver output Bootstrap supply voltage
BOOT
1. The circuit provides less than 1 V on the LVG and HVG pins (@ Isink = 10 mA), with VCC > 3 V. This allows omitting the "bleeder" resistor connected between the gate and the source of the external MOSFET normally used to hold the pin low; the gate driver assures low impedance also in SD condition.
4/22
L6390
Truth table
3
Truth table
Table 3. Truth table
Input SD L H H H H LIN X H L L H HIN X L H L H LVG L L L H L Output HVG L L L L H
Note:
X: don't care
5/22
Electrical data
L6390
4
4.1
Electrical data
Absolute maximum ratings
Table 4.
Symbol Vcc Vout Vboot Vhvg Vlvg Vop+ VopVcp+ Vi Vod dVout/dt Ptot TJ Tstg Supply voltage Output voltage Bootstrap voltage High side gate output voltage Low side gate output voltage OPAMP non-inverting input OPAMP inverting input Comparator input voltage Logic input voltage Open drain voltage Allowed output slew rate Total power dissipation (TA = 25 C) Junction temperature Storage temperature -50
Absolute maximum rating
Value Parameter Min - 0.3 Vboot - 21 - 0.3 Vout - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 Max 21 Vboot + 0.3 620 Vboot + 0.3 Vcc + 0.3 Vcc + 0.3 Vcc + 0.3 Vcc + 0.3 15 15 50 800 150 150 V V V V V V V V V V V/ns mW C C Unit
4.2
Thermal data
Table 5.
Symbol Rth(JA)
Thermal data
Parameter Thermal resistance junction to ambient SO-16 155 DIP-16 100 Unit C/W
6/22
L6390
Electrical data
4.3
Recommended operating conditions
Table 6.
Symbol Vcc VBO
(1)
Recommended operating conditions
Pin 4 16-14 14 Parameter Supply voltage Floating supply voltage DC output voltage Switching frequency Junction temperature HVG, LVG load CL = 1 nF -40 Test condition Min 12.5 12.4 -9
(2)
Max 20 20 580 800 125
Unit V V V kHz C
Vout fsw TJ
1. VBO = Vboot - Vout 2. LVG off. Vcc=12.5 V Logic is operational if Vboot > 5 V Refer to AN2378 for more details
7/22
Electrical characteristics
L6390
5
5.1
Electrical characteristics
AC operation
Table 7.
Symbol ton toff
AC operation electrical characteristics (VCC = 15 V; TJ = +25 C)
Pin Parameter Test condition Min Typ 125 125 Max 200 200 Unit ns ns
tsd
High/low side driver turn1 vs 11 on propagation delay Vout = 0 V 3 vs 15 High/low side driver turn- Vboot = Vcc CL = 1 nF off propagation delay Vi = 0 to 3.3 V Shut down to high/low 2 vs See Figure 3. side driver propagation 11, 15 delay Comparator triggering to Measured applying a high/low side driver turn- voltage step from 0 V to off propagation delay 3.3 V to pin CP+. Delay matching, HS and LS turn-on/off Rdt = 0, CL = 1 nF, CDT = 100 nF Rdt = 37 k CL = 1 nF, , CDT = 100 nF , Rdt = 136 k CL = 1 nF, CDT = 100 nF , Rdt = 260 k CL = 1 nF, CDT = 100 nF Rdt = 0, CL = 1 nF, CDT = 100 nF , Rdt = 37 k CL = 1 nF, CDT = 100 nF , Rdt = 136 k CL = 1 nF, CDT = 100 nF Rdt = 260 k CL = 1 nF, , CDT = 100 nF 0.1 0.48 1.35 2.6
125
200
ns
tisd
200
250
ns
MT
40 0.18 0.6 1.6 3.0 0.25 0.72 1.85 3.4 60 100 240 350 75 35 120 70
ns s s s s ns ns ns ns ns ns
dt
5
Dead time setting range
MDT
Matching dead time
tr tf
Rise time 11, 15 Fall time
CL = 1 nF CL = 1 nF
8/22
L6390 Figure 3. Timing
Electrical characteristics
LIN
50%
50%
tr
90% 90%
tf
LVG
ton
10%
10%
toff
HIN
50%
50%
tr
90% 90%
tf
HVG
ton
10%
10%
toff
SD
50%
50%
tr
90% 10% 90%
tf
LVG/HVG
ton
10%
toff
9/22
Electrical characteristics
L6390
5.2
Table 8.
Symbol
DC operation
DC operation electrical characteristics (VCC = 15 V; TJ = + 25 C)
Pin Parameter Test condition Min Typ Max Unit
Low supply voltage section Vcc_hys Vcc_thON Vcc_thOFF Vcc UV hysteresis Vcc UV turn ON threshold Vcc UV turn OFF threshold Vcc = 10 V SD = 5 V; LIN = 5 V; HIN = GND; RDT = 0 ; CP+=OP+=GND; OP-=5 V Vcc = 15 V SD = 5 V; LIN = 5 V; HIN = GND; RDT = 0 ; CP+=OP+=GND; OP-=5 V 500 1200 11.5 10 1500 12 10.5 1800 12.5 11 mV V V
Iqccu
4
Undervoltage quiescent supply current
120
150
A
Iqcc
Quiescent current
720
1000
A
Vref
Internal reference voltage
(1)
540
580
mV
Bootstrapped supply voltage section VBO_hys VBO_thON VBO_thOFF VBO UV hysteresis
1200 10.6 9.1
1500 11.5 10
1800 12.4 10.9
mV V V
VBO UV turn ON threshold VBO UV turn OFF threshold VBO = 9 V SD = 5 V; LIN and Undervoltage VBO quiescent HIN = 5 V; current RDT = 0 ; CP+=OP+=GND; OP-=5 V VBO = 15 V SD = 5 V; LIN and HIN = 5 V; RDT = 0 ; CP+=OP+=GND; OP-=5 V
IQBOU
16
70
110
A
IQBO
VBO quiescent current
150
210
A
ILK RDS(on)
High voltage leakage current Vhvg = Vout = Vboot = 600 V Bootstrap driver on resistance (2) LVG ON 120
10
A
Driving buffers section Iso Isi High/low side source short circuit current High/low side sink short circuit current VIN = Vih (tp<10 s) VIN = Vil (tp<10 s) 200 250 290 430 mA mA
11, 15
10/22
L6390 Table 8.
Symbol Logic inputs Vil Vih IHINh 3 IHINl ILINl 1 ILINh ISDh 2 ISDl
1. VBO = Vboot - Vout 2. RDSON is tested in the following way: RDSON = [(VCC - VCBOOT1) - (VCC - VCBOOT2)] / [I1(VCC,VCBOOT1) - I2(VCC,VCBOOT2)] where I1 is pin 16 current when VCBOOT = VCBOOT1, I2 when VCBOOT = VCBOOT2.
Electrical characteristics DC operation electrical characteristics (VCC = 15 V; TJ = + 25 C) (continued)
Pin Parameter Test condition Min Typ Max Unit
Low logic level voltage 1, 2, 3 High logic level voltage HIN logic "1" input bias current HIN logic "0" input bias current LIN logic "0" input bias current LIN logic "1" input bias current SD logic "1" input bias current SD logic "0" input bias current HIN = 15 V HIN = 0 V LIN = 0 V LIN = 15 V SD = 15 V SD = 0 V 40 6 2.25 175
0.8
V V
260 1 20 1 100 1
A A A A A A
11/22
Electrical characteristics
L6390
Table 9.
Symbol Iib
OPAMP characteristics (VCC = 15 V, TJ = +25 C)
Pin Parameter Input bias current 6, 9
(1)
Test condition
Min
Typ 100
Max 200
Unit nA V
Vicm VOL VOH 7 Io
Input common mode voltage range Low level output voltage High level output voltage Vid = 1 V, RL = 10 k to VCC Vid = 1 V, RL = 10 k to GND Source, Vid = 1; Vo = 0 V Sink, Vid = 1; Vo = VCC Slew rate Gain bandwidth product Large signal voltage gain Supply voltage rejection ratio Common mode rejection ratio Vi = 1 / 4 V; RL = 2 k; CL = 100 pF; unity gain Vo = 7.5 V; RL = 2 k
0 75 14.7 16 50 2.5 30 80 3.8 12 75 60 85 70 70
mV V mA mA V/s MHz dB dB dB
Output short circuit current
SR GBWP Avd SVR CMRR
1. The direction of input current is out of the IC.
Table 10.
Symbol Iio Vol td_comp SR
Sense comparator characteristics (VCC = 15 V, TJ = +25 C)
Pin 10 2 Parameter Input bias current Open drain low level output voltage Comparator delay 2 Slew rate Test conditions VCP+ = 1 V Iod = - 3 mA SD/OD pulled to 5 V through 100 k resistor CL = 180 pF; Rpu = 5 k 90 60 Min Typ Max 1 0.5 130 Unit A V ns V/sec
12/22
L6390
Waveforms definitions
6
Waveforms definitions
Figure 4. Dead time and interlocking waveforms definitions
LIN
LVG HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE)
INTE R
INTE R
CONTROL SIGNAL EDGES OVERLAPPED: INTERLOCKING + DEAD TIME
HIN
LOC KING
LOC KING
DT gate driver outputs OFF (HALF-BRIDGE TRI-STATE)
LIN
CONTROL SIGNALS EDGES SYNCHRONOUS (*): DEAD TIME
HIN LVG DT HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) DT
LIN
CONTROL SIGNALS EDGES NOT OVERLAPPED, BUT INSIDE THE DEAD TIME: DEAD TIME
HIN LVG DT HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) DT
LIN
CONTROL SIGNALS EDGES NOT OVERLAPPED, OUTSIDE THE DEAD TIME: DIRECT DRIVING
HIN LVG DT HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) DT
(*) HIN and LIN can be connected togheter and driven by just one control signal
13/22
Smart shut down function
L6390
7
Smart shut down function
L6390 integrates a comparator committed to the fault sensing function. The comparator has an internal voltage reference Vref connected to the inverting input, while the non-inverting input is available on pin 10. The comparator input can be connected to an external shunt resistor in order to implement a simple over-current detection function. The output signal of the comparator is fed to an integrated MOSFET with the open drain output available on pin 2, shared with the SD input. When the comparator triggers, the device is set in shut down state and both its outputs are set to low level leaving the half-bridge in tri-state. Figure 5. Smart shut down timing waveforms
comp Vref
CP+
PROTECTION
HIN/LIN
HVG/LVG
SD/OD
upper threshold lower threshold
1 open drain gate (internal)
2
real disable time Fast shut down: the driver outputs are set in SD state immediately after the comparator triggering even if the SD signal has not yet reach the lower input threshold
TIME CONSTANTS
1
= (RON_OD // RSD)
CSD
CSD 2 = RSD
SHUT DOWN CIRCUIT
VBIAS
RSD
FROM/TO CONTROLLER
SD/OD
SMART SD LOGIC
CSD
RON_OD
14/22
L6390
Smart shut down function In common over-current protection architectures the comparator output is usually connected to the SD input and an RC network is connected to this SD/OD line in order to provide a mono-stable circuit, which implements a protection time that follows the fault condition. Differently from the common fault detection systems, L6390 Smart shut down architecture allows to immediately turn-off the outputs gate driver in case of fault, by minimizing the propagation delay between the fault detection event and the actual outputs switch-off. In fact the time delay between the fault and the outputs turn off is no more dependent on the RC value of the external network connected to the pin.In the Smart shut down circuitry, the fault signal has a preferential path which directly switch off the outputs after the comparator triggering. At the same time the internal logic turns on the open drain output and holds it on until the SD voltage goes below the SD logic input lower threshold. The Smart shut down system provides the possibility to increase the time constant of the external RC network (that is the disable time after the fault event) up to very large values without increasing the delay time of the protection. Any external signal provided to the SD pin is not latched and can be used as control signal in order to perform, for instance, PWM chopping through this pin. In fact when a PWM signal is applied to the SD input and the logic inputs of the gate driver are stable, the outputs switch from the low level to the state defined by the logic inputs and vice versa.
15/22
Typical application diagram
L6390
8
Typical application diagram
Figure 6. Application diagram
BOOTSTRAP DRIVER VCC VCC + from LVG UV DETECTION FROM CONTROLLER HIN 3 4
FLOATING STRUCTURE
16
BO OT
UV DETECTION HVG DRIVER LEVEL SHIFTER S R 15 HVG
H.V.
Cboot
5V
LOGIC SHOOT THROUGH PREVENTION
14 VCC
OUT TO LOAD
FROM CONTROLLER VBIAS FROM/TO CONTROLLER
LIN
1 LVG DRIVER 11 5V COMPARATOR + + VREF VBIAS 10 CP+ LVG
SD/OD
2
SD LATCH SMART SD
GND
8
DT
5
DEAD TIME VCC OPAMP + 9 OP+ OP6
OPOUT
7
TO ADC
16/22
L6390
Bootstrap driver
9
Bootstrap driver
A bootstrap circuitry is needed to supply the high voltage section. This function is normally accomplished by a high voltage fast recovery diode (Figure 7.a). In the L6390 a patented integrated structure replaces the external diode. It is realized by a high voltage DMOS, driven synchronously with the low side driver (LVG), with diode in series, as shown in Figure 7.b. An internal charge pump (Figure 7.b) provides the DMOS driving voltage.
9.1
CBOOT selection and charging
To choose the proper CBOOT value the external MOS can be seen as an equivalent capacitor. This capacitor CEXT is related to the MOS total gate charge: Equation 1
Q gate C EXT = ------------V gate
The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss. It has to be: Equation 2 CBOOT >>> CEXT
e.g.: if Qgate is 30 nC and Vgate is 10 V, CEXT is 3 nF. With CBOOT = 100 nF the drop would be 300 mV. If HVG has to be supplied for a long time, the CBOOT selection has to take into account also the leakage and quiescent losses. e.g.: HVG steady state consumption is lower than 200 A, so if HVG TON is 5 ms, CBOOT has to supply 1 C to CEXT. This charge on a 1 F capacitor means a voltage drop of 1V. The internal bootstrap driver gives a great advantage: the external fast recovery diode can be avoided (it usually has great leakage current). This structure can work only if VOUT is close to GND (or lower) and in the meanwhile the LVG is on. The charging time (Tcharge) of the CBOOT is the time in which both conditions are fulfilled and it has to be long enough to charge the capacitor. The bootstrap driver introduces a voltage drop due to the DMOS RDSON (typical value: 120 ). At low frequency this drop can be neglected. Anyway increasing the frequency it must be taken in to account. The following equation is useful to compute the drop on the bootstrap DMOS:
17/22
Bootstrap driver Equation 3
L6390
Q gate V drop = I ch arg e R dson V drop = ------------------ R dson T ch arg e
where Qgate is the gate charge of the external power MOS, Rdson is the on resistance of the bootstrap DMOS and Tcharge is the charging time of the bootstrap capacitor. For example: using a power MOS with a total gate charge of 30nC the drop on the bootstrap DMOS is about 1V, if the Tcharge is 5s. In fact: Equation 4
30nC V drop = -------------- 120 0.7V 5s
Vdrop has to be taken into account when the voltage drop on CBOOT is calculated: if this drop is too high, or the circuit topology doesn't allow a sufficient charging time, an external diode can be used. Figure 7. Bootstrap driver
DBOOT
VCC
BOOT H.V. HVG OUT TO LOAD LVG
VCC
BOOT H.V. HVG OUT TO LOAD LVG
CBOOT
CBOOT
a
b
D99IN1067
18/22
L6390
Package mechanical data
10
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com Figure 8. DIP-16 mechanical data and package dimensions
DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 mm TYP. MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 inch TYP. MAX.
OUTLINE AND MECHANICAL DATA
DIP16
0.050
19/22
Package mechanical data Figure 9.
DIM. MIN. A a1 a2 b b1 C c1 D(1) E e e3 F(1) G L M S
REF. 0.35 MIN.
L6390
SO-16 narrow mechanical data and package dimensions
mm TYP. MAX. 1.75 0.1 0.25 0.004 DIMENSIONS mm1.6
TYP. MAX. MIN. 0.46 0.014
1.75 0.2 1.65 0.013 45 0.46(typ.)
inch MIN. TYP. MAX. 0.069 0.009
inch 0.063 TYP. 0.018 MAX.
0.068 0.008
OUTLINE AND MECHANICAL DATA
PACKAGE AND PACKING INFORMATION
0.19
a1 a2 b b1 C 0.1
A
0.25 0.5
0.35 0.19 0.5
0.007
0.004
0.010 0.020
0.064 0.018
9.8
10
0.25
0.386
0.007 0.019
0.394 0.244
0.010
16-LEAD SMALL OUTLINE PACKAGE
Weight: not available
5.8 c1
D E e 9.8 1.27 5.8
6.2 45 (typ.) 0.228
10 6.2 1.27 8.894.0 3.8 4.6 0.5 0.385 0.050 0.228
0.393 0.244
8.89
0.350
0.050
3.8 e3
F 4.60 G L
0.150
0.350 0.157 0.157 0.208 0.208
0.149 5.30 4.0 0.181 5.3 0.181
0.4
1.27
1.27
0.150
0.019
0.050
0.050
M S
0.620.62
8 (max.) 8 (max.)
0.024 0.024
SO-16
SO16 (Narrow)
(1) "D" and "F" do not include mold flash or protrusions - Mold flash or protrusions shall not exceed 0.15mm (.006inc.)
0016020 D
20/22
L6390
Revision history
11
Revision history
Table 11.
Date 29-Feb-2008 09-Jul-2008 17-Jul-2008
Document revision history
Revision 1 2 3 First release Updated: Cover page, Table 2 on page 4, Table 3 on page 5, Section 4 on page 6, Section 5 on page 8, Section 9.1 on page 17 Updated test condition values on Table 8 and Table 9 Changes
21/22
L6390
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