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CY2291
Three-PLL General Purpose EPROM Programmable Clock Generator
Features

Benefits

Three integrated phase-locked loops EPROM programmability Factory-programmable (CY2291) or field-programmable (CY2291F) device options Low-skew, low-jitter, high-accuracy outputs Power-management options (Shutdown, OE, Suspend) Frequency select option Smooth slewing on CPUCLK Configurable 3.3V or 5V operation 20-pin SOIC Package Input Frequency Range 10 MHz-25 MHz (external crystal) 1 MHz-30 MHz (reference clock) 10 MHz-25 MHz (external crystal) 1 MHz-30 MHz (reference clock) 10 MHz-25 MHz (external crystal) 1 MHz-30 MHz (reference clock) 10 MHz-25 MHz (external crystal) 1 MHz-30 MHz (reference clock)
Generates up to three custom frequencies from external sources Easy customization and fast turnaround Programming support available for all opportunities Meets critical industry standard timing requirements Supports low-power applications Eight user-selectable frequencies on CPU PLL Allows downstream PLLs to stay locked on CPUCLK output Enables application compatibility Industry-standard packaging saves on board space Specifics Factory Programmable Commercial Temperature Factory Programmable Industrial Temperature Field Programmable Commercial Temperature Field Programmable Industrial Temperature
Part Number Outputs CY2291 CY2291I CY2291F CY2291FI 8 8 8 8
Output Frequency Range 76.923 kHz-100 MHz (5V) 76.923 kHz-80 MHz (3.3V) 76.923 kHz-90 MHz (5V) 76.923 kHz-66.6 MHz (3.3V) 76.923 kHz-90 MHz (5V) 76.923 kHz-66.6 MHz (3.3V) 76.923 kHz-80 MHz (5V) 76.923 kHz-60.0 MHz (3.3V)
Logic Block Diagram
32XIN 32XOUT XTALIN OSC. XTALOUT S0 S1 S2/SUSPEND UPLL (10 BIT) /1,2,4,8 /1,2,3,4,5,6 /8,10,12,13 /20,24,26,40 /48,52,96,104 /2,3,4 CLKA CLKB CPLL (8 BIT) /1,2,4 XBUF CPUCLK OSC. 32K
MUX
CLKC CLKD
SPLL (8 BIT)
CLKF CONFIG EPROM
SHUTDOWN/ OE
Cypress Semiconductor Corporation Document #: 38-07189 Rev. *C
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised September 16, 2008
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CY2291
Pinouts
Figure 1. CY2291- 20-pin SOIC
32XOUT 32K CLKC VDD GND XTALIN XTALOUT XBUF CLKD CPUCLK 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 32XIN VBATT SHUTDOWN/OE S2/SUSPEND VDD S1 S0 CLKF CLKA CLKB
Pin Definitions Name 32XOUT 32K CLKC VDD GND XTALIN[1] XTALOUT[1, 2] XBUF CLKD CPUCLK CLKB CLKA CLKF S0 S1 S2/SUSPEND SHUTDOWN/OE VBATT 32XIN Pin Number 1 2 3 4, 16 5 6 7 8 9 10 11 12 13 14 15 17 18 19 20 32.768-kHz crystal feedback. 32.768-kHz output (always active if VBATT is present). Configurable clock output C. Voltage supply. Ground. Reference crystal input or external reference clock input. Reference crystal feedback. Buffered reference clock output. Configurable clock output D. CPU frequency clock output. Configurable clock output B. Configurable clock output A. Configurable clock output F. CPU clock select input, bit 0. CPU clock select input, bit 1. CPU clock select input, bit 2. Optionally enables suspend feature when LOW.[3] Places outputs in three-state[4] condition and shuts down chip when LOW. Optionally, only places outputs in three-state[4] condition and does not shut down chip when LOW. Battery supply for 32.768-kHz circuit. 32.768-kHz crystal input. Description
Notes 1. For best accuracy, use a parallel-resonant crystal, CLOAD 17 pF or 18 pF. 2. Float XTALOUT pin if XTALIN is driven by reference clock (as opposed to crystal). 3. Please refer to application note "Understanding the CY2291, CY2292 and CY2295" for more information. 4. The CY2291 has weak pull downs on all outputs (except 32K). Hence, when a three-state condition is forced on the outputs, the output pins are pulled LOW.
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CY2291
Operation
The CY2291 is a third-generation family of clock generators. The CY2291 is upwardly compatible with the industry standard ICD2023 and ICD2028 and continues their tradition by providing a high level of customizable features to meet the diverse clock generation needs of modern motherboards and other synchronous systems. All parts provide a highly configurable set of clocks for PC motherboard applications. Each of the four configurable clock outputs (CLKA-CLKD) can be assigned 1 of 30 frequencies in any combination. Multiple outputs configured for the same or related[3] frequencies have low (<500 ps) skew, in effect providing on-chip buffering for heavily loaded signals. The CY2291 can be configured for either 5V or 3.3V operation. The internal ROM tables use EPROM technology, allowing full customization of output frequencies. The reference oscillator has been designed for 10 MHz to 25 MHz crystals, providing additional flexibility. No external components are required with this crystal. Alternatively, an external reference clock of frequency between 1 MHz and 30 MHz can be used. Customers using the 32-kHz oscillator must connect a 10-MW resistor in parallel with the 32-kHz crystal.
combination. The only limitation is that if a PLL is shut off, all outputs derived from it must also be shut off. Suspending a PLL shuts off all associated logic, while suspending an output simply forces a three-state condition.[3] The CPUCLK can slew (transition) smoothly between 8 MHz and the maximum output frequency (100 MHz at 5V/80 MHz at 3.3V for Commercial Temp. parts or 90 MHz at 5V/66.6 MHz at 3.3V for Industrial Temp. and for field-programmed parts). This feature is extremely useful in "Green" PC and laptop applications, where reducing the frequency of operation can result in considerable power savings. This feature meets all 486 and Pentium(R) processor slewing requirements.
CyClocks Software
CyClocksTM is an easy-to-use application that allows you to configure any one of the EPROM programmable clocks offered by Cypress. You may specify the input frequency, PLL and output frequencies, and different functional options. Please note the output frequency ranges in this data sheet when specifying them in CyClocks to ensure that you stay within the limits. CyClocks also has a power calculation feature that allows you to see the power consumption of your specific configuration. CyClocks is a sub-application within the CyberClocksTM software. You can download a copy of CyberClocks for free on Cypress's web site at www.cypress.com.
Output Configuration
The CY2291 has five independent frequency sources on-chip. These are the 32-kHz oscillator, the reference oscillator, and three Phase-Locked Loops (PLLs). Each PLL has a specific function. The System PLL (SPLL) drives the CLKF output and provides fixed output frequencies on the configurable outputs. The SPLL offers the most output frequency divider options. The CPU PLL (CPLL) is controlled by the select inputs (S0-S2) to provide eight user-selectable frequencies with smooth slewing between frequencies. The Utility PLL (UPLL) provides the most accurate clock. It is often used for miscellaneous frequencies not provided by the other frequency sources. All configurations are EPROM programmable, providing short sample and production lead times. Please refer to the application note "Understanding the CY2291, CY2292, and CY2295" for information on configuring the part.
Cypress FTG Programmer
The Cypress Frequency Timing Generator (FTG) Programmers is a portable programmer designed to custom program our family of EPROM Field Programmable Clock Devices. The FTG programmers connect to a PC serial port and allow users of CyClocks software to quickly and easily program any of the CY2291F, CY2292F, CY2071AF, and CY2907F devices. The ordering code for the Cypress FTG Programmer is CY3670.
Custom Configuration Request Procedure
The CY229x are EPROM-programmable devices that may be configured in the factory or in the field by a Cypress Field Application Engineer (FAE). The output frequencies requested are matched as closely as the internal PLL divider and multiplier options allow. All custom requests must be submitted to your local Cypress FAE or sales representative. The method to use to request custom configurations is: Use CyClocksTM software. This software automatically calculates the output frequencies that can be generated by the CY229x devices and provides a print-out of final pinout which can be submitted (in electronic or print format) to your local FAE or sales representative. The CyClocks software is available free of charge from the Cypress web site (http://www.cypress.com) or from your local sales representative. Once the custom request has been processed you receive a part number with a 3-digit extension (for example, CY2292SC-128) specific to the frequencies and pinout of your device. This is the part number used for samples requests and production orders.
Power Saving Features
The SHUTDOWN/OE input three-states the outputs when pulled LOW (the 32-kHz clock output is not affected). If system shutdown is enabled, a LOW on this pin also shuts off the PLLs, counters, the reference oscillator, and all other active components. The resulting current on the VDD pins are less than 50 A (for Commercial Temp. or 100 A for Industrial Temp.) plus 15 A max. for the 32-kHz subsystem and is typically 10 A. After leaving shutdown mode, the PLLs have to re-lock. All outputs except 32K have a weak pull down so that the outputs do not float when three-stated.[4] The S2/SUSPEND input can be configured to shut down a customizable set of outputs and/or PLLs, when LOW. All PLLs and any of the outputs except 32K can be shut off in nearly any
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CY2291
Maximum Ratings
(Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.) Supply Voltage...............................................-0.5V to + 7.0V DC Input Voltage ...........................................-0.5V to + 7.0V Storage Temperature ................................. -65C to +150C Max. Soldering Temperature (10 sec) ......................... 260C Junction Temperature .................................................. 150C Package Power Dissipation...................................... 750 mW Static Discharge Voltage............................................. 2000V (per MIL-STD-883, Method 3015)
Operating Conditions[5]
Parameter VDD VDD VBATT TA CLOAD CLOAD fREF tPU Description Supply Voltage, 5.0V operation Supply Voltage, 3.3V operation Battery Backup Voltage Commercial Operating Temperature, Ambient Industrial Operating Temperature, Ambient Max. Load Capacitance 5.0V Operation Max. Load Capacitance 3.3V Operation External Reference Crystal External Reference Clock[6, 7, 8] All All All CY2291/CY2291F CY2291I/CY2291FI All All All All 10.0 1 0.05 Part Numbers Min. 4.5 3.0 2.0 0 -40 Max. 5.5 3.6 5.5 +70 +85 25 15 25.0 30 50 Unit V V V C C pF pF MHz MHz ms
Power up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic)
Electrical Characteristics, Commercial 5.0V
Parameter VOH VOL VOH-32 VOL-32 VIH VIL IIH IIL IOZ IDD IDDS IBATT Description HIGH-Level Output Voltage IOH = 4.0 mA LOW-Level Output Voltage 32.768-kHz HIGH-Level Output Voltage 32.768-kHz LOW-Level Output Voltage LOW-Level Input Voltage[9] IOL = 4.0 mA IOH = 0.5 mA IOL = 0.5 mA 2.0 0.8 <1 <1 75 10 5 10 10 250 100 50 15 VBATT 0.5 0.4 Conditions Min. 2.4 0.4 Typ. Max. Unit V V V V V V A A A mA A A
HIGH-Level Input Voltage[9] Except crystal pins Except crystal pins VIN = VDD - 0.5V VIN = +0.5V Three-state outputs VDD = VDD Max., 5V operation Shutdown active, excluding VBATT CY2291/CY2291F Input HIGH Current Input LOW Current Output Leakage Current VDD Supply Current Commercial[10] VDD Power Supply Current in Shutdown Mode[10]
VBATT Power Supply Current VBATT = 3.0V
Notes 5. Electrical parameters are guaranteed by design with these operating conditions, unless otherwise noted. 6. External input reference clock must have a duty cycle between 40% and 60%, measured at VDD/2. 7. Please refer to application note "Crystal Oscillator Topics" for information on AC-coupling the external input reference clock. 8. The oscillator circuit is optimized for a crystal reference and for external reference clocks up to 20 MHz. For external reference clocks above 20 MHz, it is recommended that a 150 pull up resistor to VDD be connected to the Xout pin. 9. Xtal inputs have CMOS thresholds. 10. Load = Max., VIN = 0V or VDD, Typical (-104) configuration, CPUCLK = 66 MHz. Other configurations vary. Power can be approximated by the following formula (multiply by 0.65 for 3V operation): IDD=10+0.06*(FCPLL+FUPLL+2*FSPLL)+0.27*(FCLKA+FCLKB+FCLKC+FCLKD+FCPUCLK+FCLKF+FXBUF).
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CY2291
Electrical Characteristics, Commercial 3.3V
Parameter VOH VOL VOH-32 VOL-32 VIH VIL IIH IIL IOZ IDD IDDS IBATT Description HIGH-Level Output Voltage IOH = 4.0 mA LOW-Level Output Voltage 32.768-kHz HIGH-Level Output Voltage 32.768-kHz LOW-Level Output Voltage LOW-Level Input Voltage Input HIGH Current Input LOW Current Output Leakage Current VDD Supply Current[10] Commercial VDD Power Supply Current in Shutdown Mode[10]
[9]
Conditions IOL = 4.0 mA IOH = 0.5 mA IOL = 0.5 mA
Min. 2.4
Typ.
Max. 0.4
Unit V V V
VBATT 0.5 0.4 2.0 0.8 <1 <1 50 10 5 10 10 250 65 50 15
V V V A A A mA A A
HIGH-Level Input Voltage[9] Except crystal pins Except crystal pins VIN = VDD-0.5V VIN = +0.5V Three-state outputs VDD = VDD Max., 3.3V operation Shutdown active, excluding VBATT CY2291/CY2291F
VBATT Power Supply Current VBATT = 3.0V
Electrical Characteristics, Industrial 5.0V
Parameter VOH VOL VOH-32 VOL-32 VIH VIL IIH IIL IOZ IDD IDDS IBATT Description HIGH-Level Output Voltage IOH = 4.0 mA LOW-Level Output Voltage 32.768-kHz HIGH-Level Output Voltage 32.768-kHz LOW-Level Output Voltage LOW-Level Input Voltage[9] IOL = 4.0 mA IOH = 0.5 mA IOL = 0.5 mA 2.0 0.8 <1 <1 75 10 5 10 10 250 110 100 15 VBATT 0.5 0.4 Conditions Min. 2.4 0.4 Typ. Max. Unit V V V V V V A A A mA A A
HIGH-Level Input Voltage[9] Except crystal pins Except crystal pins VIN = VDD-0.5V VIN = +0.5V Three-state outputs VDD = VDD Max., 5V operation Shutdown active, excluding VBATT CY2291I/CY2291FI Input HIGH Current Input LOW Current Output Leakage Current VDD Supply Industrial Current[10]
VDD Power Supply Current in Shutdown Mode[10]
VBATT Power Supply Current VBATT = 3.0V
Electrical Characteristics, Industrial 3.3V
Parameter VOH VOL VOH-32 VOL-32 Description HIGH-Level Output Voltage IOH = 4.0 mA LOW-Level Output Voltage 32.768-kHz HIGH-Level Output Voltage 32.768-kHz LOW-Level Output Voltage IOL = 4.0 mA IOH = 0.5 mA IOL = 0.5 mA VBATT 0.5 0.4 Conditions Min. 2.4 0.4 Typ. Max. Unit V V V V
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CY2291
Electrical Characteristics, Industrial 3.3V (continued)
Parameter VIH VIL IIH IIL IOZ IDD IDDS IBATT Description HIGH-Level Input Voltage LOW-Level Input Voltage Input HIGH Current Input LOW Current Output Leakage Current VDD Supply Current Industrial
[10] [9] [9]
Conditions Except crystal pins Except crystal pins VIN = VDD-0.5V VIN = +0.5V Three-state outputs VDD = VDD max., 3.3V operation Shutdown active, excluding VBATT CY2291I/CY2291FI
Min. 2.0
Typ.
Max. 0.8
Unit V V A A A mA A A
<1 <1 50 10 5
10 10 250 70 100 15
VDD Power Supply Current in Shutdown Mode[10]
VBATT Power Supply Current VBATT = 3.0V
Switching Characteristics, Commercial 5.0V
Parameter t1 Name Output Period Description Clock output range, 5V operation CY2291 CY2291F Output Duty Cycle[11] Duty cycle for outputs, defined as t2 / t1[12] fOUT > 66 MHZ Duty cycle for outputs, defined as t2 / t1[12] fOUT < 66 MHZ t3 t4 t5 t6 t7 t8 t9A t9B t9C t9D t10A Rise Time Fall Time Output clock rise time[13] Output clock fall time[13] Min. 10 (100 MHz) 11.1 (90 MHz) 40% 45% 50% 50% 3 2.5 10 10 < 0.25 1.0 < 0.5 < 0.7 < 400 < 250 < 25 Typ. Max. 13000 (76.923 kHz) 13000 (76.923 kHz) 60% 55% 5 4 15 15 0.5 20.0 1 1 500 350 50 ns ns ns ns ns MHz/m s % ns ps ps ms Unit ns ns
Output Disable Time for output to enter three-state mode after Time SHUTDOWN/OE goes LOW Output Enable Time Skew CPUCLK Slew Clock Jitter[14] Clock Jitter[14] Clock Jitter[14] Clock Jitter[14] Lock Time for CPLL Time for output to leave three-state mode after SHUTDOWN/OE goes HIGH Skew delay between any identical or related outputs[3,
12, 15]
Frequency transition rate Peak-to-peak period jitter (t9A Max. - t9A min.),% of clock period (fOUT < 4 MHz) Peak-to-peak period jitter (t9B Max. - t9B min.) (4 MHz < fOUT < 16 MHz) Peak-to-peak period jitter (16 MHz < fOUT < 50 MHz) Peak-to-peak period jitter (fOUT > 50 MHz) Lock Time from Power Up
Notes 11. XBUF duty cycle depends on XTALIN duty cycle. 12. Measured at 1.4V. 13. Measured between 0.4V and 2.4V. 14. Jitter varies with configuration. All standard configurations sample tested at the factory conform to this limit. For more information on jitter, please refer to the application note: "Jitter in PLL-Based Systems." 15. CLKF is not guaranteed to be in phase with CLKA-D, even if it is referenced off the same PLL.
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CY2291
Switching Characteristics, Commercial 5.0V (continued)
Parameter t10B Name Description Min. Typ. < 0.25 CY2291 CY2291F 8 8 Max. 1 100 90 Unit ms MHz MHz Lock Time for Lock Time from Power Up UPLL and SPLL Slew Limits CPU PLL Slew Limits
Switching Characteristics, Commercial 3.3V
Parameter t1 Name Output Period Description Clock output range, 3.3V operation CY2291 CY2291F Output Duty Cycle[11] Duty cycle for outputs, defined as t2 / t1[12] fOUT > 66 MHZ Duty cycle for outputs, defined as t2 / t1[12] fOUT < 66 MHZ t3 t4 t5 t6 t7 t8 t9A t9B t9C t9D t10A t10B Rise Time Fall Time Output clock rise time[13] Output clock fall time[13] Min. 12.5 (80 MHz) 15 (66.6 MHz) 40% 45% 50% 50% 3 2.5 10 10 < 0.25 1.0 <0.5 <0.7 <400 <250 <25 <0.25 CY2291 CY2291F 8 8 Typ. Max. 13000 (76.923 kHz) 13000 (76.923 kHz) 60% 55% 5 4 15 15 0.5 20.0 1 1 500 350 50 1 80 66.6 ns ns ns ns ns MHz/m s % ns ps ps ms ms MHz MHz Unit ns ns
Output Disable Time for output to enter three-state mode after Time SHUTDOWN/OE goes LOW Output Enable Time Skew CPUCLK Slew Clock Jitter[14] Clock Jitter[14] Clock Jitter[14] Clock Jitter[14] Lock Time for CPLL Time for output to leave three-state mode after SHUTDOWN/OE goes HIGH Skew delay between any identical or related outputs[3,
12, 15]
Frequency transition rate Peak-to-peak period jitter (t9A Max. - t9A min.),% of clock period (fOUT < 4 MHz) Peak-to-peak period jitter (t9B Max. - t9B min.) (4 MHz < fOUT < 16 MHz) Peak-to-peak period jitter (16 MHz < fOUT < 50 MHz) Peak-to-peak period jitter (fOUT > 50 MHz) Lock Time from Power Up
Lock Time for Lock Time from Power Up UPLL and SPLL Slew Limits CPU PLL Slew Limits
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CY2291
Switching Characteristics, Industrial 5.0V
Parameter t1 Name Output Period Clock output range, 5V operation Description CY2291I CY2291FI Output Duty Cycle[11] Duty cycle for outputs, defined as t2 / t1[12] fOUT > 66 MHZ Duty cycle for outputs, defined as t2 / t1[12] fOUT < 66 MHZ t3 t4 t5 t6 t7 t8 t9A t9B t9C t9D t10A t10B Rise Time Fall Time Output clock rise time[13] Output clock fall time[13] Min. 11.1 (90 MHz) 12.5 (80 MHz) 40% 45% 50% 50% 3 2.5 10 10 < 0.25 1.0 <0.5 <0.7 <400 <250 <25 <0.25 CY2291I CY2291FI 8 8 Typ. Max. 13000 (76.923 kHz) 13000 (76.923 kHz) 60% 55% 5 4 15 15 0.5 20.0 1 1 500 350 50 1 90 80 ns ns ns ns ns MHz/m s % ns ps ps ms ms MHz MHz Unit ns ns
Output Disable Time for output to enter three-state mode after Time SHUTDOWN/OE goes LOW Output Enable Time Skew CPUCLK Slew Clock Jitter[14] Clock Jitter[14] Clock Jitter[14] Clock Jitter[14] Lock Time for CPLL Time for output to leave three-state mode after SHUTDOWN/OE goes HIGH Skew delay between any identical or related outputs[3,
12, 15]
Frequency transition rate Peak-to-peak period jitter (t9A Max. - t9A min.),% of clock period (fOUT < 4 MHz) Peak-to-peak period jitter (t9B Max. - t9B min.) (4 MHz < fOUT < 16 MHz) Peak-to-peak period jitter (16 MHz < fOUT < 50 MHz) Peak-to-peak period jitter (fOUT > 50 MHz) Lock Time from Power Up
Lock Time for Lock Time from Power Up UPLL and SPLL Slew Limits CPU PLL Slew Limits
Switching Characteristics, Industrial 3.3V
Parameter t1 Name Output Period Description Clock output range, 3.3V operation CY2291I CY2291FI Output Duty Cycle[11] Duty cycle for outputs, defined as t2 / t1[12] fOUT > 66 MHZ Duty cycle for outputs, defined as t2 / t1[12] fOUT < 66 MHZ t3 t4 t5 Rise Time Fall Time Output clock rise time[13] Output clock fall time[13] Min. 15 (66.6 MHz) 16.66 (60 MHz) 40% 45% 50% 50% 3 2.5 10 Typ. Max. 13000 (76.923 kHz) 13000 (76.923 kHz) 60% 55% 5 4 15 ns ns ns Unit ns ns
Output Disable Time for output to enter three-state mode after Time SHUTDOWN/OE goes LOW
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CY2291
Switching Characteristics, Industrial 3.3V (continued)
Parameter t6 t7 t8 t9A t9B t9C t9D t10A t10B Name Output Enable Time Skew CPUCLK Slew Clock Jitter[14] Clock Jitter[14] Clock Jitter[14] Clock Jitter[14] Lock Time for CPLL Description Time for output to leave three-state mode after SHUTDOWN/OE goes HIGH Skew delay between any identical or related outputs[3,
12, 15]
Min.
Typ. 10 < 0.25
Max. 15 0.5 20.0
Unit ns ns MHz/ms % ns ps ps ms ms MHz MHz
Frequency transition rate Peak-to-peak period jitter (t9A Max. - t9A min.),% of clock period (fOUT < 4 MHz) Peak-to-peak period jitter (t9B Max. - t9B min.) (4 MHz < fOUT < 16 MHz) Peak-to-peak period jitter (16 MHz < fOUT < 50 MHz) Peak-to-peak period jitter (fOUT > 50 MHz) Lock Time from Power Up
1.0 < 0.5 < 0.7 < 400 < 250 < 25 < 0.25 CY2291I CY2291FI 8 8
1 1 500 350 50 1 66.6 60
Lock Time for Lock Time from Power Up UPLL and SPLL Slew Limits CPU PLL Slew Limits
Switching Waveforms
Figure 2. All Outputs, Duty Cycle and Rise/Fall Time
t1 t2 OUTPUT t3 t4
Figure 3. Output Three-State Timing [4]
OE t5 ALL THREE-STATE OUTPUTS t6
Figure 4. CLK Outputs Jitter and Skew
t9A CLK OUTPUT t7 RELATED CLK
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CY2291
Switching Waveforms
Figure 5. CPU Frequency Change
SELECT
OLD SELECT Fold
NEW SELECT STABLE t8 & t10 Fnew
CPU
Test Circuit VDD 0.1 F OUTPUTS CLK out CLOAD
VDD 0.1 F GND Ordering Information
Ordering Code CY2291FI Pb-Free CY2291SXC-XXX CY2291SXC-XXXT CY2291SXL-XXX CY2291SXL-XXXT CY2291FX CY2291FXT 20-Pin SOIC 20-Pin SOIC - Tape and Reel 20-Pin SOIC 20-Pin SOIC - Tape and Reel 20-Pin SOIC 20-Pin SOIC - Tape and Reel Commercial Commercial Commercial Commercial Commercial Commercial 5.0V 5.0V 3.3V 3.3V 3.3V or 5.0V 3.3V or 5.0V
[16]
Package Type 20-Pin SOIC
Operating Range Industrial
Operating Voltage 3.3V or 5.0V
Package Characteristics
Package 20-pin SOIC JA (C/W) 125 JC (C/W) 25 Transistor Count 9271
Note 16. Not recommended for new designs.
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CY2291
Package Diagram
Figure 6. 20-Pin (300 MIL) SOIC Package Outline
51-85024 *C
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CY2291
Document History Page
Document Title: CY2291 Three-PLL General Purpose EPROM Programmable Clock Generator Document Number: 38-07189 REV. ** *A *B *C ECN 110321 121836 276756 2565316 Orig. of Change SZV RBI RGL AESA/KVM Submission Date 10/28/01 12/14/02 10/18/04 09/16/08 Description of Change Change from Spec number: 38-00410 to 38-07189 Power up requirements added to Operating Conditions Information Added Lead Free Devices Updated template. Added Note "Not recommended for new designs." Removed part number CY2291F, CY2291FT, CY2291SC-XXX, CY2291SC-XXXT, CY2291SI-XXX, CY2291SI-XXXT, CY2291SL-XXX, CY2291SL-XXXT, CY2291FIT, CY2291SXI-XXX, CY2291SXI-XXXT, CY2291FXI and CY2291FXIT. Changed CyClocks reference to include CyberClocks. Changed Lead-Free to Pb-Free. Updated Package diagram 51-85024 *B to 51-85024 *C.
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(c) Cypress Semiconductor Corporation, 2001-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-07189 Rev. *C
Revised September 16, 2008
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Pentium is a registered trademark of Intel Corporation. CyClocks is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are trademarks of their respective holders.
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Price & Availability of CY2291FX

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