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| TSM4420 Pin assignment: 1. Source 2. Source 3. Source 4. Gate 5, 6, 7, 8. Drain Preliminary N-Channel Enhancement Mode MOSFET VDS = 25V ID = 13.5A RDS (on), Vgs @ 10V, Ids @ 13.5A = 8.5m RDS (on), Vgs @ 4.5V, Ids @ 11A = 11m Features Advanced trench process technology High Density Cell Design for Ultra Low On-Resistance Fully Characterized Avalanche Voltage and Current Block Diagram Ordering Information Part No. TSM4420CS Packing Package SOP-8 Tape & Reel (2,500pcs / Reel) Absolute Maximum Rating (TA = 25 oC unless otherwise noted) Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Current Maximum Power Dissipation Operating Junction Temperature Operating Junction and Storage Temperature Range TA = 25 C TA = 70 C o o Symbol VDS VGS ID IDM PD TJ TJ, TSTG Limit 25 20 13.5 50 2 1.3 +150 -55 to +150 Unit V V A W o o C C Thermal Performance Parameter Junction-to-case Thermal Resistance Junction to Ambient Thermal Resistance (PCB mounted) Note: 1. Maximum DC current limited by the package 2 2. 1-in 2oz Cu PCB board Symbol Rjc Rja Limit 2.2 50 Unit o C/W TSM4420 1-3 2005/08 rev. B Electrical Characteristics TJ = 25 C, unless otherwise noted o Parameter Static Drain-Source Breakdown Voltage Drain-Source On-State Resistance Gate Threshold Voltage Zero Gate Voltage Drain Current Gate Body Leakage Forward Transconductance Conditions Symbol Min Typ Max Unit VGS = 0V, ID = 250uA VGS = 4.5V, ID = 11A VGS = 10V, ID = 13.5A VDS = VGS, ID = 250uA VDS = 24V, VGS = 0V VGS = 20V, VDS = 0V VDS =10V, ID = 35A BVDSS RDS(ON) RDS(ON) VGS(TH) IDSS IGSS gfs 25 --1.0 ---- -9 7 ---50 -11 8.5 3.0 1.0 100 -- V m m V uA nA S Dynamic Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time VDD = 15V, RL = 15, ID = 1A, V GEN = 10V, RG = 24 VDS = 15V, ID = 13.5A, VGS = 5V Qg Qgs Qgd td(on) tr td(off) tf --------6.6 4.0 15 11 40 12 25 --25 18 60 20 nS nC Source-Drain Diode Max. Diode Forward Current Diode Forward Voltage IS = 20A, VGS = 0V Note: 1. pulse test: pulse width <=300uS, duty cycle <=2% 2. Negligible, Dominated by circuit inductance. IS VSD ---0.75 50 1.1 A V TSM4420 2-3 2005/08 rev. B SOP-8 Mechanical Drawing SOP-8 DIMENSION DIM A B C D F G K M P R 0 MILLIMETERS MIN 4.80 3.80 1.35 0.35 0.40 0.10 o INCHES MIN 0.189 0.150 0.054 0.014 0.016 0.004 0 o MAX 5.00 4.00 1.75 0.49 1.25 0.25 7 o MAX 0.196 0.157 0.068 0.019 0.049 0.009 7 o 1.27 (typ) 0.05 (typ) 5.80 0.25 6.20 0.50 0.229 0.010 0.244 0.019 TSM4420 3-3 2005/08 rev. B |
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