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| CY2HH8110 1.5V 1:10 HSTL Fanout Buffer Features * * * * * * * * * * DC to 150-MHz operation 1.5V power supply One single-ended HSTL input Ten single-ended Class II HSTL outputs Less than 1.9% Duty Cycle distortion Balanced 16-mA output drive Output Enable/Disable Low output-output skew Operating temperature range: 0C to +85C 32-pin TQFP package Description The CY2HH8110 is a low-voltage HSTL fanout buffer designed for data communications, clock management, and specialty memory applications. The class II HSTL outputs are balanced Push-Pull in design capable of delivering 16 mA into 10 pF load. This class allows both source series termination and symmetrically double parallel termination. The CY2HH8110 low-output duty cycle distortion makes it suitable for Double Data Rate (DDR) applications. Block Diagram Pin Configuration GND GND VDD GND GND Q4 Q5 VDD VDD Q6 Q7 G ND VDD Q1 Q2 Q1 Q2 IN Q9 Q 10 OE VDD GND VDD OE GND IN VDD G ND 32 31 30 29 28 27 26 25 24 1 23 2 22 3 21 4 CY2HH8110 20 5 19 6 7 18 8 17 9 10 11 12 13 14 15 16 Q3 GND GND Q10 VDD VDD Q9 Q8 GND Cypress Semiconductor Corporation Document #: 38-07556 Rev ** * 3901 North First Street * San Jose, CA 95134 * 408-943-2600 Revised August 1, 2003 CY2HH8110 Pin Description[1] Pin 6 IN 30, 27, 26, 23, 22, 19, 18, Q(1:10) 15, 14, 11 4 OE Name I O I, PD I/O Type HSTL HSTL LVCMOS Description HSTL reference clock input HSTL clock outputs Output enable/disable input. When held LOW, outputs are enabled. When set HIGH, all outputs are disabled LOW. 1.5V power supply[2] Common ground 1, 3, 7, 12, 13, 20, 21, 28, VDD 29 2, 5, 8, 9, 10, 16, 17, 24, 25, 31, 32 GND Supply Supply VDD Ground Notes: 1. PD = Internal pull down. 2. A 0.1-uF bypass capacitor should be placed as close as possible to each positive power pin (< 0.2"). If these bypass capacitors are not close to the pins their high frequency filtering characteristics will be cancelled by the lead inductance of the trace. Document #: 38-07556 Rev ** Page 2 of 7 CY2HH8110 Absolute Maximum Conditions Parameter VDD VDD VIN VOUT VTT LU RPS TS TA TJ OJC OJA ESDH FIT Description DC Supply Voltage DC Operating Voltage DC Input Voltage DC Output Voltage Output termination Voltage Latch Up Immunity Power Supply Ripple Temperature, Storage Temperature, Operating Ambient Temperature, Junction Dissipation, Junction to Case Dissipation, Junction to Ambient ESD Protection (Human Body Model) Failure in Time Manufacturing test Functional Ripple Frequency < 100 kHz Non-functional Functional Functional Functional Functional 1600 10 -65 0 200 150 +150 +85 +150 42 105 Functional Relative to VSS, with or VDD applied Relative to VSS Condition Min. -0.5 1.35 -0.5 -0.5 Max. 2.5 1.65 VDD + 0.5 VDD + 0.5 VDD / 2 Unit V V V V V mA mVp-p C C C C/W C/W V ppm Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. DC Electrical Specifications (VDD = 1.5V 8%, TA = 0C to +85C) Parameter VIL VIH VIL VIH VOL VOH IIL IIH IDDQ IDD CIN COUT ZOUT Description Input Voltage, Low Input Voltage, High Input Voltage, Low Input Voltage, High Output Voltage, Low[3] Output Voltage, High[3] Input Current, Low[4] Input Current, High[4] Quiescent Supply Current Dynamic Supply Current Input Pin Capacitance Output Pin Capacitance Output Impedance IOL = 16 mA IOH = -16 mA VIL = VSS VIH = VDD VIN = 0V, outputs disabled Outputs loaded @ 62.5 MHz OE# input Condition HSTL input, VREF = 0.75V Min. -0.30 0.85 -0.30 0.7 * VDD -0.3 1.0 - - - - - - - Typ. - - - - - - - - - 215 - 4.5 25 Max. 0.65 1.80 0.3 * VDD VDD + 0.3 0.4 VDD + 0.3 -10 100 1 250 6 6 - Unit V V V V V V A A mA mA pF pF AC Electrical Specifications (VDD = 1.5V 8%, TA = 0C to +85C) [5] Parameter fin VIL(AC) VIH(AC) tr , tf DC Description Input Frequency AC Input HIGH Voltage AC Input LOW Voltage Output rise/fall time[6] Output duty cycle VREF =VDD/2, Internal Voltage Reference 20% to 80% Fout < 100 MHz Fout > 100 MHz Condition Min. - 0.95 - 0.3 48 45 Typ. - - - - - - 0.55 1.5 52 55 Max. 150 Unit MHz V V ns % Notes: 3. Driving 50 series terminated or symmetrically double parallel terminated transmission line to a termination voltage of VTT. 4. Inputs have pull-down resistors that affect the input current. 5. AC characteristics apply for series or parallel output termination to VTT. Parameters are guaranteed by characterization and are not 100% tested. 6. tr/tf times are faster with parallel terminated loads. Document #: 38-07556 Rev ** Page 3 of 7 CY2HH8110 AC Electrical Specifications (VDD = 1.5V 8%, TA = 0C to +85C) (continued)[5] Parameter tjit_DCD Description Output Duty Cycle Distortion Condition Measure Jitter delay between input and output at VDD/2 @ fREF = 62.5 MHz DCD @ fREF = 62.5 MHz tsk(O) tsk(pp) tPLH tPHL tQoff tQon tJIT(CC) Output-to-Output Skew Part-to-Part Skew Propagation Delay, Low to High Propagation Delay, High to Low Output Disable Time Output Enable Time Cycle-to-Cycle Jitter, Deterministic jitter Min. - Typ. - Max. |300| Unit ps - - - - - - - - - - - - - - - 10 |1.9| 200 2 7 7 7 7 50 % ps ns ns ns ns ns ps Parameter Measurement Information Output tjit_D(cc) Figure 1. Cycle-to-Cycle Jitter Input 80% 20% Output 80% 20% tPLH & tPHL Figure 2. Propagation Delay from Input Reference to Output n O u tp u t n O u tp u t m ts k (0 ) Figure 3. Output to Output Skew OE Qn tQ o n tQ o ff Figure 4. Output Enable/Disable Time Document #: 38-07556 Rev ** Page 4 of 7 CY2HH8110 VTT = VDDQ / 2 RT = 50 ohm RT 50 ohm RT Cload = 10pf Figure 5. An Example HSTL Symmetrically Double Parallel Terminated Output Load | and CLASS II HSTL AC Test Load [7,8] 25 ohm C lo a d = 1 0 p F 50 ohm Figure 6. An Example HSTL Source Series Terminated Output Load[7,8] Ordering Information Part Number CY2HH8110AC CY2HH8110ACT Notes: 7. HSTL to HSTL input. 8. Cload includes probe and test board capacitance. Package Type 32-pin TQFP 32-pin TQFP - Tape and Reel Product Flow Commercial, 0C to +85C Document #: 38-07556 Rev ** Page 5 of 7 CY2HH8110 Package Drawing and Dimensions 32-Lead Thin Plastic Quad Flatpack 7 x 7 x 1.0mm A32 51-85063-*B All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07556 Rev ** Page 6 of 7 (c) Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY2HH8110 Document History Page Document Title:CY2HH8110 1.5V 1:10 HSTL Fanout Buffer Document Number: 38-07556 REV. ** ECN No. 128398 Issue Date 08/04/03 Orig. of Change RGL New Data Sheet Description of Change Document #: 38-07556 Rev ** Page 7 of 7 |
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