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Agamem Mircoelectronics Inc.
AA88368AP
10-BIT DAC
PRELIMINARY
FEATURES 14 bits serial data input (3 wire serial data transfer method, DI, CLK, LD) R-2R resistor ladder used for D/A conversion 10 channels with 10 bits resolution monotonic D/A converter 10channel buffer operational amplifiers operating in the full voltage range from VCC to GND Max. +/- 3.5 LSBs Integral Non-Linearity Max +/- 1 LSB Differential Non-Linearity Max. 10 MHz Serial data input Serial I/O for cascade application Max. 2.0 mA analog output drive/sink current Two separate power supply/ground lines for system and analog power supply Single +5 V system power supply Silicon-gate CMOS process DESCRIPTION The AA88368AP is an 10-bit resolution digital to analog converter (DAC), designed for interface with 10 bits micro-controller. The AA88368AP has 10 channels with operational amplifier output buffers. Digital data are input serially in max. 10MHz by individual channel units. The latched digital data are converted into analog DC voltages by the D/A converter in 20 s settling time. AA88368AP is a single 5V power DAC. Output could be full swing as the analog power is equal to the system power. The AA88368AP has 10 operational amplifier output buffers for each one of 10 channels. These operational amplifier output buffers are used to provide high current drive/sink capability. The AA88368AP is suitable for electronic volumes and replacement for potentiometers for adjustment, in addition to normal D/A converter applications. AA88368AP is a 20 pins SSOP package. Its operation temperature range is specified over -10 to 75 . Figure 2 shows its pin assignment.
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Agamem Mircoelectronics Inc.
AA88368AP
10-BIT DAC
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS (Ta=25 Parameter Supply voltage Upper reference voltage of D/A converter Input voltage Output voltage Power dissipation Operating temperature Storage temperature )
Symbol VCC VDD VIN VOUT PD TOPR TSTG
Limits -0.3 ~ +6.0 -0.3 ~ +6.0 -0.3 ~ +6.0 -0.3 ~ +6.0 400 -25 ~ +85 -55 ~ +125 )
Unit V V V V mW
RECOMMENDED OPERATING CONSITIONS (Ta=25 Parameter Supply voltage Symbol VCC Min. 4.5 Typ. Max. 5.5
Unit V
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Agamem Mircoelectronics Inc.
AA88368AP
10-BIT DAC
PRELIMINARY
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Agamem Mircoelectronics Inc.
AA88368AP
10-BIT DAC
PRELIMINARY
PIN DESCRIPTION Pin No. Pin name Analog / Digital I / O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VSS Ao3 Ao4 Ao5 Reverse Reset Ao6 Ao7 Ao8 VDD VCC Ao9 Ao10 D0 LD Analog Analog Analog Analog Digital Digital Analog Analog Analog Analog Analog Analog Digital Digital -
Function
D/A converter lower reference voltage input terminal
O 10bit D/A converter output terminal (CH3) O 10bit D/A converter output terminal (CH4) O 10bit D/A converter output terminal (CH5) I I
It is inverted about the data designation 10bit LSB and MSB. The analog output of all channels is fixed for "L".
O 10bit D/A converter output terminal (CH6) O 10bit D/A converter output terminal (CH7) O 10bit D/A converter output terminal (CH8) D/A converter upper reference voltage input terminal Power supply terminal
O 10bit D/A converter output terminal (CH9) O 10bit D/A converter output terminal (CH10) O I Terminal to output LSB data of 14-bit shift register When H-level signal is input to this terminal, the value stored in 14-bit shift register is loaded in decoder and D/A converter output register.
16 17 18 19 20
CLK DI Ao1 Ao2 GND
Digital Digital Analog Analog -
I I
Shift clock input terminal. Input signal at DI pin is input to 14-bit shift register of shift clock pulse. Serial data input terminal to 14-bit long serial data
O 10bit D/A converter output terminal (CH1) O 10bit D/A converter output terminal (CH2) GND terminal
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Agamem Mircoelectronics Inc.
AA88368AP
10-BIT DAC
PRELIMINARY
* : VDD VSS used for the analog block except operational amplifier block
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2006/7/5
Agamem Mircoelectronics Inc.
AA88368AP
10-BIT DAC
PRELIMINARY
AA88368
AA88368
AA88368
* : Analog power (VDD, VSS) can be different each other depend on application consideration
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2006/7/5
Agamem Mircoelectronics Inc.
AA88368AP
10-BIT DAC
PRELIMINARY
FUNCTIONAL DESCRIPTION
DEVICE CONFIGURATION
As illustrated in Figure 3 Block Diagram, AA88368AP is composed by digital block and analog block. The digital block consists of a Shift Register, a Address decoder and 8 Data Latches. The analog block consists of 10 R-2R D/A converters and 10 Operational Amplifier Buffers. For stability consideration, the power supply and ground lines are separate between the digital block and the operational amplifier buffers, and R-2R D/A converters.
LOCK DESCRIPTIONB
SHIEFT RGISTER The AA88368AP has a 14 bits shift register to store 14 bits anytime. At the rising edge of CLK signal, the external digital data will be shifted into the LSB of the Shift-Register. And the original contents in the Shift Register will also shift right. The 14th bit(MSB) will also output to DO for cascade application for this device. Figure 4 shows the configuration. ADRESS DECODER and DATA LATCH When the LD pin is on high then the 14 bits stored in the shift register will be latched. The 4 upper bits (addr-bit) will send to address decoder to select one of the ten Data Latches. The 10 lower bits(data-bit) will be written into the indicated Data-Latch as the internal digital data. R-2R D/A CONVERTER The internal digital data from the Data Latch will be transferred into a analog DC voltage with 8-bit resolution by R-2R D/A converter in a max.20us settling time. OPERATIONAL AMPLIFIER BUFFER Each channel has a corresponding operational amplifier output buffer. It's used to get a complete monotonic analog DC output and provide a high current drive /sink capability up to 2mA. It could operate in the full range from VCC to GND as the analog power is equal to the system power.
DEVICE OPERATION
Figure 5 shows the input/output timing. A 14-bit address/data is serially input into the shift register through the DI pin synchronously at the rising edge of the CLK signal. The format of the shift register is shown in the Figure 6.The lower 10 bits (D0 ~ D9) are data bits to be converted, and the upper 4 bits(D10 ~ D13) are address bits to select a channel to be written. As the LD pin is on high, the address decoder load the upper 4 bits to select a Data-Latch, and write the 10 data bits into it. Figure 7 shows the Data-Latch address map, and Table2 shows the address decoding. 8 data bits written into individual Data-Latch are converted into analog DC voltage through R-2R resistor ladder, dividing the supply voltage |VDD-VSS| in 10-bit resolution. Output buffers at individual D/A converter outputs can rise up 7 2006/7/5
Agamem Mircoelectronics Inc.
AA88368AP
10-BIT DAC
PRELIMINARY
the drive/sink ability to 2mA. Figure 8 shows a configuration of the R-2R resistor ladder D/A converter following with an operational amplifier. Table 3 is the mapping table of internal digital data and the corresponding output analog DC voltage.
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Agamem Mircoelectronics Inc.
AA88368AP
10-BIT DAC
PRELIMINARY
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Agamem Mircoelectronics Inc.
AA88368AP
10-BIT DAC
PRELIMINARY
CIRCUIT OPERATIONS D10 D11 D12 D13 DAC selection O O O O O O O O I I I I I I I I O O O O I I I I O O O O I I I I O O I I O O I I O O I I O O I I O Don't care I AO1 selection O AO2 selection I AO3 selection O AO4 selection I AO5 selection O AO6 selection I AO7 selection O AO8 selection I AO9 selection O AO10 selection I Don't care O Don't care I Don't care O Don't care I Command for test MSB first) D/A output VrefL
Reverse = open or VCC short setting (data D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 000000000 000000000 000000001 000000001 0
1 (VrefH-VrefL) / 1024*1+VrefL 0 (VrefH-VrefL) / 1024*2+VrefL 1 (VrefH-VrefL) / 1024*3+VrefL
111111111 111111111
0 (VrefH-VrefL) / 1024*1022+VrefL 1 (VrefH-VrefL) / 1024*1023+VrefL
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Agamem Mircoelectronics Inc.
AA88368AP
10-BIT DAC
PRELIMINARY
Reverse = L setting (data LSB first) D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 000000000 100000000 010000000 110000000 0 D/A output VrefL
0 (VrefH-VrefL) / 1024*1+VrefL 0 (VrefH-VrefL) / 1024*2+VrefL 0 (VrefH-VrefL) / 1024*3+VrefL
011111111 111111111
0 (VrefH-VrefL) / 1024*1022+VrefL 1 (VrefH-VrefL) / 1024*1023+VrefL
ELECTRICAL CHARACTERISTICS
Digital characteristics (unless otherwise noted, VCC=5V, VrefH=5V, VrefL=0V, Ta=25 ) Parameter Power supply current Input leak current Input voltage "L" Input voltage "H" Output voltage "L" Output voltage "H" Symbol Min Typ Max Unit ICC IILK VIL VIH VOL VOH -5 2 0 4.6 5 0.8 0.4 5 ua Vin=0~VCC V V V IOL=2.5ma V IOH=2.5ma Conditions
- 0.85 2.8 ma CLK=10MHz operated, VCC=5V, IAO=0us
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Agamem Mircoelectronics Inc.
AA88368AP
10-BIT DAC
PRELIMINARY
ANALOG CHARACTERISTICS (unless otherwise noted, VCC=5V, VrefH=5V, VrefL=0V, Ta=25 )
Parameter Consumption current D/A converter Upper reference voltage D/A converter Lower reference voltage Buffer amplifier Output voltage range Buffer amplifier Output drive range Differential non-linearity error Accuracy Non-linearity error Zero code error Full scale error Buffer amplifier Output impedance Pull-up I/O internal R value Symbol Min Typ Max Unit IrefH VrefH VrefL Vo 3 0 0.1 0.2 Io SDL SL SZERO SFULL RO RUP -2 -1 -3.5 -25 -25 12.5 4.5 5 25 7.5 5 1.5 4.9 4.75 2 1 3.5 25 25 15 mV Ohm Vin: 0V resistance value alters by the applied voltage mA V V V V mA condition Conditions VrefH=5V, VrefL=0V Data maximun current Reference voltage can not always be set to any value in this range, because it is restricted the buffer amplifier output voltage range Io = + / - 100uA Io = +/- 1ma Upper satuation voltage = 0.35V Lower satuation voltage = 0.23V VerfL=0.7V,
LSB VrefH=4.796V, load (Io=0mA)
Vcc=5.5V (2mV/LSB) Without
37.5 Kohm
NOTES: Integral Non-Linearity : The difference between the digital data converted output values and a reference straight line drawn through the first and the last output values Differential Non-Linearity : The difference from the ideal increment value when the digital data is increased by 1 bit.
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Agamem Mircoelectronics Inc.
AA88368AP
10-BIT DAC
PRELIMINARY
AC CHARACTERISTICS (unless otherwise noted, VCC=5V, VrefH=5V, VrefL=0V, Ta=25C)
Parameter Reset "L" pulse width Clock "L" pulse width Clock "H" pulse width Clock rise time Clock fall time Data setup time Data hold time LD setup time LD hold time LD "H" pulse duration Data output delay time D/A output settling time
Symbol Min Typ Max Unit TRTL 50 7 50 50 200 20 CL=100pf ns TCKL 50 TCKH 50 TCR TCF -
Condition
TDCH 20 TCHD 40 TCHL 50 TLDC 50 TLDH 50 TDO TLDO -
CL<1000pf, VO: 0.5V~4.5V, the time us until the becomes the final value of 1/2LSB
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Agamem Mircoelectronics Inc.
AA88368AP
10-BIT DAC
PRELIMINARY
OPERATION NOTES
* There are 3 different type of power supply terminal and 1 type of GND terminal in this IC. Each of these terminals requires the constant power supply for operating. * Pile up ripple and noise to these power supply terminals, it can`t keep the accuracy of the D/A converter. Therefore external bypass capacitor recommend to set as close as possible to the terminals between VDD and GND in order to stabilizes the D/A converter. * The capacitor between output and GND recommend to set under 100pF including parasitic capacitor in order to reduces jitter from layout of the output line and noise. * LSB-first or MSB-first decoding are selected by REVERSE terminal. Therefore, REVERSE terminal should be set as --open" or --VDD short" at LSB-first mode, --GND short" at MSB-first mode. * RESET terminal uses the I/O-cell of the internal pull-up resistance, adding a capacitor between this terminal and GND, this IC will have equivalent function as power-on-reset, by making a time-delay. When a reset signal is inputted from the controller, it is possible that the output of all channels are fixed on Low-level in the --L" section on the pulse.
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Agamem Mircoelectronics Inc.
AA88368AP
10-BIT DAC
PRELIMINARY
TSSOP 20L PACKAGE DIMENSION
NOTE: 1. 2. 3. 4. PACKAGE BODY SIZES EXCLUDE MOLD FLASH PROTRUSIONS OR GATE BURRS TOLERANCE +-0.1mm UNLESS OTHERWISE SPECIFIED COPLANARITY: 0.1mm CONTROLLOMG DIMENSION IS MILLIMETER. CONVERTED INCH DIMENSIONS ARE NOT NECESSARILY EXACT. 5. FOLLOWED FROM JEDEC MO-153
SYMBOLS A A1 A2 b C D E E1 e L y
DIMENSIONS IN MILLIMETERS DIMENSIONS IN INCHES MIN 0.05 0.80 0.19 0.09 6.40 6.20 4.30 0.45 0 NOM 1.00 6.50 6.40 4.40 0.65 0.60 15
MAX 1.20 0.15 1.05 0.30 0.20 6.60 6.60 4.50 0.75 0.10 8
MIN 0.002 0.031 0.007 0.004 0.252 0.244 0.169 0.018 0
NOM 0.039 0.256 0.252 0.173 0.026 0.024 -
MAX 0.048 0.006 0.041 0.012 0.008 0.260 0.260 0.177 0.030 0.004 8
2006/7/5

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