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Integrated Circuit Systems, Inc.
ICS873990
LOW VOLTAGE, LVCMOS/ CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
FEATURES
* 14 differential LVPECL outputs * Selectable crystal oscillator interface or TEST_CLK inputs * TEST_CLK accepts the following input levels: LVCMOS, LVTTL * Output frequency: 400MHz (maximum) * Crystal input frequency range: 10MHz to 25MHz * VCO range: 200MHz to 800MHz * Output skew: 250ps (maximum) * Cycle-to-cyle jitter: 50ps (typical) * LVPECL mode operating voltage supply range: VCC = 3.135V to 3.465V, VEE = 0V * ECL mode operating voltage supply range: VCC = 0V, VEE = -3.465V to -3.135V * 0C to 70C ambient operating temperature * Industrial temperature available upon request * Lead-Free package fully RoHS compliant
GENERAL DESCRIPTION
The ICS873990 is a low voltage, low skew, 3.3V LVPECL/ECL Clock Generator and a member HiPerClockSTM of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS873990 has two selectable clock inputs. The XTAL1 and XTAL2 are used to interface to a crystal and the TEST_CLK pin can accept a LVCMOS or LVTTL input. This device has a fully integrated PLL along with frequency configurable outputs. An external feedback input and output regenerates clocks with "zero delay".
ICS
The four independent banks of outputs each have their own output dividers, which allow the device to generate a multitude of different bank frequency ratios and output-to-input frequency ratios. The output frequency range is 25MHz to 400MHz and the input frequency range is 6.25MHz to 125MHz. The PLL_SEL input can be used to bypass the PLL for test and system debug purposes. In bypass mode, the input clock is routed around the PLL and into the internal output dividers. The ICS873990 also has a SYNC output which can be used for system synchronization purposes. It monitors Bank A and Bank C outputs for coincident rising edges and signals a pulse per the timing diagrams in this data sheet. This feature is used primarily in applications where Bank A and Bank C are running at different frequencies, and is particularly useful when they are running at non-integer multiples of each other. Example Applications: 1. Line Card Multiplier: Multiply 19.44MHz from a back-plane to 77.76MHz on the line card ASIC and Serdes. 2. Zero Delay Buffer: Fan out up to thirteen 100MHz copies from a reference clock to multiple processing units on an embedded system.
PIN ASSIGNMENT
FSEL0 FSEL1 FSEL2
nQB3 QB3 VCCO nQA0 QA0 nQA1 QA1 nQA2 QA2 nQA3 QA3 SYNC_SEL VCO_SEL
39 38 37 36 35 34 33 32 31 30 29 28 27 26 40 41 42 43 44 45 46 47 48 49 50 51 52 1
VEE
FSEL3
nQB2
nQB1
nQB0
nQC2
VCCO
QC2
QB2
QB1
QB0
QC1 nQC1 QC0 nQC0 VCCO QD1 nQD1 QD0 nQD0 VCCO QFB nQFB VCCA
25 24 23 22 21
ICS873990
20 19 18 17 16 15
23
PLL_EN MR
4
REF_SEL
5
FSEL_FB2
6
FSEL_FB1
14 7 8 9 10 11 12 13
FSEL_FB0 XTAL_IN XTAL_OUT TEST_CLK EXT_FB VCC nEXT_FB
52-Lead LQFP 10mm x 10mm x 1.4mm package body Y package Top View
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REV. B
JUNE 13, 2005
Integrated Circuit Systems, Inc.
ICS873990
LOW VOLTAGE, LVCMOS/ CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
BLOCK DIAGRAM
VCO_SEL Pulldown PLL_EN Pulldown REF_SEL Pulldown TEST_CLK Pulldown XTAL_IN XTAL_OUT QA0 nQA0 QA1
XTAL OSC
nQA1
PHASE DETECTOR LPF
VCO
QA2 nQA2 QA3 nQA3 QB0
EXT_FB nEXT_FB MR Pulldown
nQB0 QB1 nQB1
FREQUENCY GENERATOR
FSEL_0:3 Pulldown
QB2 nQB2 QB3 nQB3 QC0
SYNC
FSEL_FB0:2 Pulldown
nQC0 QC1 nQC1 QC2 nQC2 QD0
SYNC_SEL Pulldown
nQD0 QD1 nQD1 QFB nQFB
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Integrated Circuit Systems, Inc.
ICS873990
LOW VOLTAGE, LVCMOS/ CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
Type Power Input Description
TABLE 1. PIN DESCRIPTIONS
Number 1 2 Name VEE MR Negative supply pin. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs (Qx) to go low and the inver ted outputs Pulldown (nQx) to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. PLL enable pin. When logic LOW, PLL is enabled. When logic HIGH, Pulldown PLL is in bypass mode. LVCMOS/LVTTL interface levels. Selects between the different reference inputs as the PLL reference Pulldown source. When logic LOW, selects cr ystal inputs. When logic HIGH, selects TEST_CLK. LVCMOS/LVTTL interface levels. Pulldown Feedback frequency select pins. LVCMOS/LVTTL interface levels. Pulldown LVCMOS/LVTTL test clock input. Cr ystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Core supply pin. Pulldown External feedback input. Pullup/ External feedback input. V /2 default when left floating. CC Pulldown Analog supply pin. Differential feedback output pair. LVPECL interface levels. Output supply pins. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Sync output select pin. When LOW, the SYNC output follows the Pulldown timing diagram (page 5). When HIGH, QD output follows QC output. Pulldown Selects VCO range. LVCMOS/LVTTL interface levels.
3 4 5 6 7 8 9, 10 11 12 13 14 15, 16 17, 22, 30, 42 18, 19 20, 21 23, 24 25, 26 27 33 36 39 28, 29 31, 32 34, 35 37, 38 40, 41 43, 44 45, 46 47, 48 49, 50 51 52
PLL_EN REF_SEL FSEL_FB2 FSEL_FB1 FSEL_FB0 TEST_CLK XTAL_IN, XTAL_OUT VCC EXT_FB nEXT_FB VCCA nQFB, QFB VCCO nQD0, QD0 nQD1, QD1 nQC0, QC0 nQC1, QC1 FSEL3 FSEL2 FSEL1 FSEL0 nQC2, QC2 nQB0, QB0 nQB1, QB1 nQB2, QB2 nQB3, QB3 nQA0, QA0 nQA1, QA1 nQA2, QA2 nQA3, QA3 SYNC_SEL VCO_SEL
Input Input
Input Input Input Power Input Input Power Output Power Output Output Output Output Input Output Output Output Output Output Output Output Output Output Input Input
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
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Integrated Circuit Systems, Inc.
ICS873990
LOW VOLTAGE, LVCMOS/ CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLDOWN RPULLup Parameter Input Capacitance Input Pulldown Resistor Input Pullup Resistor
TABLE 3A. SELECT PIN FUNCTION TABLE
Inputs FSEL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FSEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FSEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FSEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 QAx /2 /2 /2 /2 /2 /2 /2 /2 /2 /2 /4 /4 /4 /6 /6 /8 Outputs QBx /2 /2 /4 /2 /6 /4 /4 /6 /2 /8 /4 /6 /6 /6 /8 /8 QCx /2 /4 /4 /6 /6 /6 /8 /8 /8 /8 /6 /6 /8 /8 /8 /8
TABLE 3B. FEEDBACK CONTROL FUNCTION TABLE
Inputs FSEL_FB2 0 0 0 0 1 1 1 1 FSEL_FB1 0 0 1 1 0 0 1 1 FSEL_FB0 0 1 0 1 0 1 0 1 Outputs QFB /2 /4 /6 /8 /8 /16 /24 /32
TABLE 3C. INPUT CONTROL FUNCTION TABLE
Control Input Pin PLL_EN VCO_SEL REF_SEL MR SYNC_SEL Logic 0 Enables PLL fVCO Selects XTAL --Selects outputs Logic 1 Bypasses PLL fVCO/2 Selects TEST_CLK Resets outputs Match QC Outputs
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REV. B
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Integrated Circuit Systems, Inc.
ICS873990
LOW VOLTAGE, LVCMOS/ CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
1:1 Mode
QA QC SYNC (QD)
2:1 Mode
QA QC SYNC (QD)
3:1 Mode
QA QC SYNC (QD)
3:2 Mode
QA QC SYNC (QD)
4:3 Mode
QA QC SYNC (QD)
FIGURE 1. TIMING DIAGRAMS
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Integrated Circuit Systems, Inc.
ICS873990
LOW VOLTAGE, LVCMOS/ CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
4.6V -0.5V to VCC + 0.5 V 50mA 100mA 42.3C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maxi-mum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, VEE = 0V, TA = 0C TO 70C
Symbol VCC VCCA VCCO ICC ICCA ICCO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 3.465 3.465 150 15 95 V mA mA mA Units V
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, VEE = 0V, TA = 0C TO 70C
Symbol VIH Parameter Input High Voltage REF_SEL, SYNC_SEL, FSEL_FB0:FB2, PLL_EN, FSEL0:3, MR, VCO_SEL TEST_CLK REF_SEL, SYNC_SEL, FSEL_FB0:FB2, PLL_EN, FSEL0:3, MR, VCO_SEL TEST_CLK VCC = VIN = 3.465V VIN = 0V, VCC = 3.465V -5 Test Conditions Minimum 2 2 -0.3 -0.3 Typical Maximum VCC + 0.3 VCC + 0.3 0.8 1.3 15 0 Units V V V V A A
VIL IIH IIL
Input Low Voltage
Input High Current Input Low Current
TABLE 4B. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, VEE = 0V, TA = 0C TO 70C
Symbol VOH VOL VSWING Parameter Output High Voltage, NOTE 1 Output Low Voltage, NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCC - 1.4 VCC - 2.0 0.6 Typical Maximum VCC - 0.9 VCC - 1.7 1.0 Units V V V
NOTE 1: Outputs terminated with 50 to VCCO - 2V.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level
873990AY
Test Conditions
Minimum 10
Typical Maximum 25 50 7 1
Units MHz pF mW
REV. B JUNE 13, 2005
Fundamental
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ICS873990
LOW VOLTAGE, LVCMOS/ CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
Test Conditions TEST_CLK Feedback / 6 Feedback / 8 66.66 50 25 16.66 12.5 50 33.33 25 12.5 8.33 6.25 25 Minimum Typical Maximum 3 133.33 100 50 33.33 25 100 66.66 50 25 16.66 12.5 75 Units ns MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz %
TABLE 6. PLL INPUT REFERENCE CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol t R / tR Parameter Input Rise/Fall Time
Reference Frequency VCO_SEL = 0
Feedback / 16 Feedback / 24 Feedback / 32
fREF Reference Frequency VCO_SEL = 1
Feedback / 4 Feedback / 6 Feedback / 8 Feedback / 16 Feedback / 24 Feedback / 32
fREFDC
Reference Input Duty Cycle
NOTE: These parameters are guaranteed by design, but not tested in production.
TABLE 7. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0C TO 70C
Symbol fMAX t(O) Parameter Output Frequency Static Phase Offset; TEST_CLK NOTE 1, 5 Output Skew; NOTE 2, 3 Multiple Frequency Skew; NOTE 3, 6 Cycle-to-Cycle Jitter; NOTE 3 PLL VCO Lock Range; NOTE 4 PLL Lock Time Output Rise/Fall Time 20% to 80% 0.2 VCO_SEL = 0 VCO_SEL = 1 400 200 50 800 400 10 1 Test Conditions Minimum Typical Maximum 400 -240 120 0 250 350 Units MHz ps ps ps ps MHz MHz ms ns %
tsk(o) t sk(w) tjit(cc)
f VCO t LOCK tR / tF
odc Output Duty Cycle 45 55 All parameters measured at fMAX unless noted otherwise. NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. NOTE 2:Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: When VCO_SEL = 0, the PLL will be unstable with feedback configurations of /2, /4 and some /6. When VCO_SEL = 1, the PLL will be unstable with a feedback configuration of /2. NOTE 5: Static phase offset is specified for an input frequency of 50MHz with feedback in /8. NOTE 6: Defined as skew across banks of outputs switching in the same direction operating at different frequencies with the same supply voltages and equal load conditions. Measured at VCCO/2.
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Integrated Circuit Systems, Inc.
ICS873990
LOW VOLTAGE, LVCMOS/ CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
2V
VCC , VCCA, VCCO
Qx
SCOPE
nQx Qx nQy
LVPECL
VEE
nQx
Qy
tsk(o)
-1.3V -0.165V
OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
nQFB, nQAx:nQDx QFB, QAx:QDx
VOH
TEST_CLK nQFB, nQAx:nQDx QFB, QAx:QDx
VOL VOH VOL
tcycle
n
t(O)
tjit(cc) = tcycle n -tcycle n+1
1000 Cycles
STATIC PHASE OFFSET
CYCLE-TO-CYCLE JITTER
nQFB, nQAx:nQDx QFB, QAx:QDx
nQxx Qxx nQyy Qyy
tsk()
t PW
t
PERIOD
odc =
t PW t PERIOD
MULTIPLE FREQUENCY SKEW
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
80% Clock Outputs
80% VSW I N G
20% tR tF
20%
OUTPUT RISE/FALL TIME
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tcycle n+1
x 100%
REV. B
JUNE 13, 2005
Integrated Circuit Systems, Inc.
ICS873990
LOW VOLTAGE, LVCMOS/ CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS873990 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin.
3.3V VCC .01F VCCA .01F 10F 10
FIGURE 2. POWER SUPPLY FILTERING
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50 FOUT FIN
125 Zo = 50 FOUT
125
Zo = 50 50 1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FIN
Zo = 50 84 84
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
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ICS873990
LOW VOLTAGE, LVCMOS/ CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
allel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts.
CRYSTAL INPUT INTERFACE
The ICS873990 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 4 below were determined using a 25MHz, 18pF par-
XTAL_OUT C1 22p X1 18pF Parallel Crystal XTAL_IN C2 22p
Figure 4. CRYSTAL INPUt INTERFACE
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ICS873990
LOW VOLTAGE, LVCMOS/ CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS873990. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS873990 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 165mA = 571.7mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 14 * 30mW = 420mW
Total Power_MAX (3.465V, with all outputs switching) = 571.7mW + 420mW = 991.7mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 47.1C/W per Table 8 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.992W * 47.1C/W = 116.7C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 8. THERMAL RESISTANCE JA
FOR
52-PIN LQFP, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 58.0C/W 42.3C/W
200
47.1C/W 36.4C/W
500
42.0C/W 34.0C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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3. Calculations and Equations.
ICS873990
LOW VOLTAGE, LVCMOS/ CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 5.
VCCO
Q1
VOUT RL 50 VCCO - 2V
FIGURE 5. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CCO
*
For logic high, VOUT = VOH_MAX = VCCO_MAX - 0.9V (V
CCO_MAX
-V
OH_MAX
) = 0.9V =V - 1.7V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CCO_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CCO_MAX
CCO_MAX
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
L
CCO_MAX
-V
OH_MAX
)=
[(2V - 0.9V)/50] * 0.9V = 19.8mW ))/R ] * (V
L
Pd_L = [(V
OL_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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LOW VOLTAGE, LVCMOS/ CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR RELIABILITY INFORMATION
TABLE 9.
JAVS. AIR FLOW TABLE FOR 52 LEAD LQFP
JA by Velocity (Linear Feet per Minute)
0 200
47.1C/W 36.4C/W
500
42.0C/W 34.0C/W
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards
58.0C/W 42.3C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS873990 is: 5788 Pin compatible with the MPC990
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ICS873990
LOW VOLTAGE, LVCMOS/ CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
52 LEAD LQFP
PACKAGE OUTLINE - Y SUFFIX
FOR
TABLE 10. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A2 b c D D1 E E1 e L ccc 0.45 0 --0.05 1.35 0.22 0.09 BCC MINIMUM NOMINAL 52 --1.40 0.32 -12.00 BASIC 10.00 BASIC 12.00 BASIC 10.00 BASIC 0.65 BASIC ---0.75 7 0.08 1.60 0.15 1.45 0.38 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
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ICS873990
LOW VOLTAGE, LVCMOS/ CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
Marking ICS873990AY ICS873990AY TBD TBD Package 52 Lead LQFP 52 Lead LQFP 52 Lead "Lead-Free" LQFP 52 Lead "Lead-Free" LQFP Shipping Packaging tray 500 tape & reel tray 500 tape & reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
TABLE 11. ORDERING INFORMATION
Part/Order Number ICS873990AY ICS873990AYT ICS873990AYLF ICS873990AYLFT
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 873990AY
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ICS873990
LOW VOLTAGE, LVCMOS/ CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR
REVISION HISTORY SHEET
Rev B
Table T5 T11
Page 1 6 15
Description of Change Features Section - added Lead-Free bullet. Cr ystal Characteristics - added Drive Level. Ordering Information Table - added Lead-Free par t number and note.
Date 6/13/05
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