View ICS85411AMI_4134975.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

LOW SKEW, 1-TO-2 DIFFERENTIAL-TOLVDS FANOUT BUFFER
ICS85411I
GENERAL DESCRIPTION
The ICS85411I is a low skew, high performance IC S 1-to-2 Differential-to-LVDS Fanout Buffer and a HiPerClockSTM member of the HiPerClockSTM family of High Performance Clock Solutions from IDT. The CLK, nCLK pair can accept most standard differential input levels.The ICS85411I is characterized to operate from a 3.3V power supply. Guaranteed output and par t-to-par t skew characteristics make the ICS85411I ideal for those clock distribution applications demanding well defined perfor mance and repeatability.
FEATURES
* Two differential LVDS outputs * One differential CLK, nCLK clock input * CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL * Maximum output frequency: 650MHz * Translates any single ended input signal to LVDS levels with resistor bias on nCLK input * Output skew: 25ps (maximum) * Part-to-part skew: 300ps (maximum) * Additive phase jitter, RMS: 0.05ps (typical) * Propagation delay: 2.5ns (maximum) * 3.3V operating supply * -40C to 85C ambient operating temperature * Available in both standard (RoHS 5) and lead free (RoHS 6) packages
BLOCK DIAGRAM
CLK nCLK Q0 nQ0 Q1 nQ1
PIN ASSIGNMENT
Q0 nQ0 Q1 nQ1 1 2 3 4 8 7 6 5 VDD CLK nCLK GND
ICS85411I
8-Lead SOIC 3.90mm x 4.90mm x 1.37mm package body M Package Top View
IDT TM / ICSTM DIFFERENTIAL-TO-LVDS FANOUT BUFFER
1
ICS85411AMI REV. B NOVEMBER 7, 2007
ICS85411I LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 4 5 6 7 8 Name Q0, nQ0 Q1, nQ1 GND nCLK CLK VDD Type Output Output Power Input Input Power Pullup Description Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Power supply ground. Pulldown Inver ting differential clock input. Non-inver ting differential clock input. Positive supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
IDT TM / ICSTM DIFFERENTIAL-TO-LVDS FANOUT BUFFER
2
ICS85411AMI REV. B NOVEMBER 7, 2007
ICS85411I LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, IO Continuous Current Surge Current Storage Temperature, TSTG 4.6V -0.5V to VDD + 0.5V 10mA 15mA -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, JA 112.7C/W (0 lfpm)
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V10%, TA = -40C TO 85C
Symbol VDD IDD Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 2.97 Typical 3.3 Maximum 3.63 50 Units V mA
TABLE 3B. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V10%, TA = -40C TO 85C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current CLK nCLK CLK nCLK Test Conditions VDD = VIN = 3.63V VDD = VIN = 3.63V VDD = 3.63, VIN = 0V VDD = 3.63V, VIN = 0V -150 -5 0.15 0.5 1. 3 VDD - 0.85 Minimum Typical Maximum 5 150 Units A A A A V V
Peak-to-Peak Input Voltage; NOTE 1
Common Mode Input Voltage; NOTE 1, 2 VCMR NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode voltage is defined as VIH.
TABLE 3C. LVDS DC CHARACTERISTICS, VDD = 3.3V10%, TA = -40C TO 85C
Symbol VOD VOD VOS VOS IOFF IOSD IOS VOH VOL Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change Power Off Leakage Differential Output Shor t Circuit Current Output Shor t Circuit Current Output High Voltage Output Low Voltage 0.9 -20 1.325 Test Conditions Minimum 247 Typical 325 0 1.45 5 1 -3.5 -3.5 1.34 1.06 Maximum 454 50 1.575 50 +2 0 -5 -5 1.6 Units mV mV V mV A mA mA V V
IDT TM / ICSTM DIFFERENTIAL-TO-LVDS FANOUT BUFFER
3
ICS85411AMI REV. B NOVEMBER 7, 2007
ICS85411I LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
TABLE 4. AC CHARACTERISTICS, VDD = 3.3V10% TA = -40C TO 85C
Symbol Parameter fMAX tPD t sk(o) t sk(pp) t jit t R / tF odc Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Output Rise/Fall Time Output Duty Cycle 1.5 Test Conditions Minimum Typical Maximum 650 2.5 25 300 (12kHz to 20MHz) 20% to 80% @ 50MHz f > 500MHz 150 46 0.05 350 54 52 Units MHz ns ps ps ps ps % %
f 500MHz 48 All parameters measured at 650MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
IDT TM / ICSTM DIFFERENTIAL-TO-LVDS FANOUT BUFFER
4
ICS85411AMI REV. B NOVEMBER 7, 2007
ICS85411I LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz
0 -10 -20 -30 -40 -50 -60
band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.
Input/Output Additive Phase Jitter @ 200MHz (12kHz to 20MHz)
= 0.05ps typical
SSB PHASE NOISE dBc/HZ
-70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1M 10M 100M 500M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the
device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment.
IDT TM / ICSTM DIFFERENTIAL-TO-LVDS FANOUT BUFFER
5
ICS85411AMI REV. B NOVEMBER 7, 2007
ICS85411I LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
VDD
SCOPE
3.3V10% POWER SUPPLY + Float GND -
nCLK
VDD
Qx
V
CLK
PP
Cross Points
V
CMR
LVDS
nQx
GND
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx PART 1 Qx nQy PART 2 Qy tsk(pp)
nQx Qx
nQy Qy
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nCLK
80%
CLK nQ0, nQ1 Q0, Q1
tPD
80% VOD
Clock Outputs
20% tR tF
20%
PROPAGATION DELAY
nQ0, nQ1 Q0, Q1
OUTPUT RISE/FALL TIME
VDD out
t
PERIOD
t PW
DC Input
LVDS
100
VOD/ VOD out
odc =
t PW t PERIOD
x 100%
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
DIFFERENTIAL OUTPUT VOLTAGE SETUP
IDT TM / ICSTM DIFFERENTIAL-TO-LVDS FANOUT BUFFER
6
ICS85411AMI REV. B NOVEMBER 7, 2007
ICS85411I LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
VDD out DC Input
out
VOS/ VOS
OFFSET VOLTAGE SETUP
VDD
out
DC Input
LVDS
IOSB out
OUTPUT SHORT CIRCUIT CURRENT SETUP
IDT TM / ICSTM DIFFERENTIAL-TO-LVDS FANOUT BUFFER
LVDS
LVDS
IOFF
VDD
POWER OFF LEAKAGE SETUP
VDD
IOS
DC Input out
LVDS
out
IOSD
DIFFERENTIAL OUTPUT SHORT CIRCUIT CURRENT SETUP
7
ICS85411AMI REV. B NOVEMBER 7, 2007
ICS85411I LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED OUTPUT PINS OUTPUTS:
LVDS All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, there should be no trace attached.
IDT TM / ICSTM DIFFERENTIAL-TO-LVDS FANOUT BUFFER
8
ICS85411AMI REV. B NOVEMBER 7, 2007
ICS85411I LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 2A, the input termination applies for IDT HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 2A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN IDT HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 2B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm
CLK
nCLK
Receiv er
FIGURE 2C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 2D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 125 R4 125 CLK Zo = 50 Ohm C2 nCLK HiPerClockS Input
R5 100 - 200
R6 100 - 200
R1 84
R2 84
R5,R6 locate near the driver pin.
FIGURE 2E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE
BY
IDT TM / ICSTM DIFFERENTIAL-TO-LVDS FANOUT BUFFER
9
ICS85411AMI REV. B NOVEMBER 7, 2007
ICS85411I LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 3. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs.
3.3V 3.3V LVDS + R1 100
-
100 Ohm Differential Transmission Line
FIGURE 3. TYPICAL LVDS DRIVER TERMINATION
IDT TM / ICSTM DIFFERENTIAL-TO-LVDS FANOUT BUFFER
10
ICS85411AMI REV. B NOVEMBER 7, 2007
ICS85411I LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85411I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS85411I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 10% = 3.63V, which gives worst case results.
*
Power (core)MAX = VDD_MAX * IDD_MAX = 3.63V * 50mA = 181.5mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3C/W per Table 5 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.182W * 103.3C/W = 103.8C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 5. THERMAL RESISTANCE JA
FOR
8-LEAD SOIC, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 153.3C/W 112.7C/W
200
128.5C/W 103.3C/W
500
115.5C/W 97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
IDT TM / ICSTM DIFFERENTIAL-TO-LVDS FANOUT BUFFER
11
ICS85411AMI REV. B NOVEMBER 7, 2007
ICS85411I LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE
FOR
8 LEAD SOIC
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 153.3C/W 112.7C/W
200
128.5C/W 103.3C/W
500
115.5C/W 97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85411I is: 636
IDT TM / ICSTM DIFFERENTIAL-TO-LVDS FANOUT BUFFER
12
ICS85411AMI REV. B NOVEMBER 7, 2007
ICS85411I LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC
TABLE 7. PACKAGE DIMENSIONS
SYMBOL N A A1 B C D E e H h L 5.80 0.25 0.40 0 1.35 0.10 0.33 0.19 4.80 3.80 1.27 BASIC 6.20 0.50 1.27 8 Millimeters MINIMUN 8 1.75 0.25 0.51 0.25 5.00 4.00 MAXIMUM
Reference Document: JEDEC Publication 95, MS-012
IDT TM / ICSTM DIFFERENTIAL-TO-LVDS FANOUT BUFFER
13
ICS85411AMI REV. B NOVEMBER 7, 2007
ICS85411I LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS85411AMI ICS85411AMIT ICS85411AMILF ICS85411AMILFT Marking 85411AI 85411AI 85411AIL 85411AIL Package 8 lead SOIC 8 lead SOIC 8 lead "Lead Free" SOIC 8 lead "Lead Free" SOIC Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT TM / ICSTM DIFFERENTIAL-TO-LVDS FANOUT BUFFER
14
ICS85411AMI REV. B NOVEMBER 7, 2007
ICS85411I LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
REVISION HISTORY SHEET Rev Table T3C B 8 11 3, 4 Page 3 Description of Change Changed VDD from 5% to 10% throughout datasheet. LVDS DC Characteristics Table - changed VOD range from 200mV min./360mV max. to 247mV min./454mV max. Changed VOD from 40mV max. to 50mV max. Changed VOS from 1.125mV min./1.375mV max. to 1.325mV min./1.575mV max. Changed VOS from 25mV max. to 50mV max. Added Recommendations for Unused Output Pins. Added Power Considerations. Corrected temperature in tables. Date
9/25/06
B
3x, 4
11/7/07
IDT TM / ICSTM DIFFERENTIAL-TO-LVDS FANOUT BUFFER
15
ICS85411AMI REV. B NOVEMBER 7, 2007
ICS85411I LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015 408-284-8200 Fax: 408-284-2775
For Tech Support
netcom@idt.com 480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.)
Asia Pacific and Japan
Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505
Europe
IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851
(c) 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

▲Up To Search▲

Price & Availability of ICS85411AMI

	To Download ICS85411AMI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .