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 BUS IC
y K-Bus transceiver LIN- / K-Bus transceiver LIN transceiver + VREG LIN transceiver LIN transceiver + VREG + WD Single wire CAN transceiver CAN transceiver
DC/DC CONVERTER
MOTOR DRIVER IC
RIPPLE COUNTER
DRIVER IC
I/O IC
SENSOR IC
SENSOR INTERFACE IC
y K-Bus transceiver
FEATURES y y y y y y y y y y Supply voltage range VS 6.9V to 19V Supply voltage range VDD 4.5V to 5.5V Data rate up to 9.600 Baud Bus-line input voltage range from - 24V to + 30V (+40V for t < 0.5s) Internal monitoring of prohibited conditions Output slewrate control to reduce EMI Very low standby current (30A typical) Useable as diagnostic interface to ISO 9141 - 40C to + 125C operating temperature SO14n package Undefined states are avoided during low voltage conditions by means of a Power-on-Reset which blocks the outputs. The inputs feature internal pull-up and pull-down current sources to maintain defined levels. The bus pins TRM and REC feature a wide input voltage range from - 24V to + 40V independent of VS and VDD. This ensures that in case of missing ground or power supply connection the operation of other devices using the bus is not affected. DESCRIPTION The IC is designed for communication via bidirectional serial data channels. In addition to the level conversion of transmit and receive signals from the micro processor's voltage level to the 12V bus level, the device includes plausibility checks in order to guarantee undisturbed bus communication in case of corrupted data from the micro controller. PINNING Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Name RxMI MIR GND VDD TRM REC VS PU MI SEN/STA TxD BCEN RxD NRxD Description Receive data from MI-Bus MI-Bus input Ground +5V supply Transmitter output K-Bus input +12V supply Switching pull-up between VDD and VS MI-mode, disables slewrate control on TRM Status of transmit path Transmit data to TRM Enable bit compare function Receive data from K-Bus Inverted RxD
RxMI MIR GND VDD TRM REC VS
1 2 3 4 5 6 7
E910.05
PACKAGE
14 13 12 11 10 9 8
NRxD RxD BCEN TxD SEN/STA MI PU
APPLICATION y Automotive low speed bus systems
BLOCK DIAGRAM
VBAT
VS
VDD
VDD
RxD NRxD Ref. 12
REC
TRM
C
TxD BCEN SEN/STA PU MI RxMI
control
slewrate control & currentlimitation
MIR Ref.5
Note ELMOS Semiconductor AG (below ELMOS) reserves the right to make changes to the product contained in this publication without notice. ELMOS assumes no responsibility for the use of any circuits described herein, conveys no licence under any patent or other right, and makes no representation that the circuits are free of patent infringement. While the information in this publication has been checked, no responsibility, however, is assumed for inaccuracies. ELMOS does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of a life-support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications.
8
Copyright (c) 2005 ELMOS Reproduction, in part or whole, without the prior written consent of ELMOS, is prohibited. www.elmos.de | sales@elmos.de
elmos product catalog june 2005
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