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| STA2416 BluetoothTM Baseband with integrated flash Target Specification Features BluetoothTM specification compliance: V1.1 and V1.2 SW compatible with STLC2416 2 layer class 4 PCB compatible - Point-to-point, point-to-multi-point (up to 7 slaves) and scatternet capability Asynchronous connection oriented (ACL) logical transport link Synchronous connection oriented (SCO) links: 2 simultaneous SCO channels Supports pitch-period error concealment (PPEC) - Improves speech quality in the vicinity of interference - Improves coexistence with WLAN - Works at receiver, no Bluetooth implication Adaptive frequency hopping (AFH): hopping kernel, channel assessment as master and as slave Faster connection: interlaced scan for page and inquiry scan, first FHS without random backoff, RSSI used to limit range Extended SCO (eSCO) links Standard BlueRF bus interface QoS flush Clock support - System clock input: any integer value from 12 to 33 MHz - LPO clock input at 3.2 and 32 kHz or via the embedded 32 kHz crystal oscillator cell ARM7TDMI 32-bit CPU Memory - Integrated 4 Mbit flash Part number STA2416 Package LFBGA120 (10x10x1.4mm) LFBGA120 (10x10x1.4mm) - 64 KByte on-chip RAM - 4 KByte on-chip boot ROM Low power architecture with sleep mode HW support for packet types - ACL: DM1, 3, 5 and DH1, 3, 5 - SCO: HV1, 3 and DV - eSCO: EV3, 5 Communication interfaces - Synchronous serial interface, supporting up to 32-bit data - Two enhanced 16550 UARTs with 128-byte FIFO depth - 12 Mbps USB interface - Fast master I2C bus interface - Multi slot PCM interface - 15 programmable GPIOs - 2 external interrupts and various interrupt possibilities through other interfaces 32 KHz clock out Efficient support for WLAN coexistence Ciphering support for up to 128-bit key Receiver signal strength indication (RSSI) support for power-controlled links Separate control for external power amplifier (PA) for class1 power support Software support: low level (up to HCI) stack or embedded stack with profiles - Support of UART and USB HCI transport layers Packing Tube December 2006 Rev 1 1/38 www.st.com 1 This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice. Contents STA2416 Contents 1 2 3 Application features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram and pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 3.2 3.3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin description and assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 Quick reference data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 4.2 4.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 I/O specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3.1 4.3.2 Specifications for 3.3 V I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Specifications for 1.8 V I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.4 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 Baseband . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1.1 5.1.2 Baseband 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Baseband 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2 Integrated Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2.1 Flash signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 General specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1 6.2 6.3 6.4 6.5 6.6 6.7 System clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1.1 Slow clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Boot procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Master reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Interrupts/wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 V1.2 detailed functionality - extended SCO . . . . . . . . . . . . . . . . . . . . . . . 22 V1.2 detailed functionality - adaptive frequency hopping . . . . . . . . . . . . . 23 2/38 STA2416 Contents 6.8 6.9 6.10 V1.2 detailed functionality - faster connection . . . . . . . . . . . . . . . . . . . . . 23 V1.2 detailed functionality - quality of service . . . . . . . . . . . . . . . . . . . . . 24 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.10.1 6.10.2 6.10.3 6.10.4 Sniff or park . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Inquiry/page scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 No connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Active link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.11 6.12 SW initiated low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 BluetoothTM - WLAN coexistence in collocated scenario . . . . . . . . . . . . . 25 6.12.1 6.12.2 6.12.3 6.12.4 6.12.5 Algorithm 1: PTA (packet traffic arbitration) . . . . . . . . . . . . . . . . . . . . . . 26 Algorithm 2: WLAN master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Algorithm 3: BluetoothTM master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Algorithm 4: Two-wire mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Algorithm 5: Alternating wireless medium access (AWMA) . . . . . . . . . . 27 7 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.1 7.2 UART interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Synchronous serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.2.1 7.2.2 2 Feature description: Agilent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Feature description: 32-bit SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.3 7.4 7.5 7.6 7.7 I C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 USB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 JTAG interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 RF interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 PCM voice interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8 HCI UART transport layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.1 UART settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9 10 11 12 HCI USB transport layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Class1 power support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3/38 List of tables STA2416 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 LVTTL DC input specification (3V 4/38 STA2416 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin out (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 eSCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 AFH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Algorithm 1: PTA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Algorithm 2: WLAN master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Algorithm 3: BluetoothTM master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Agilent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 32-bit SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 USB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 PCM (A-law, m-law) standard mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Linear mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 PCM interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 UART transport layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 LFBGA120 (10x10x1.4mm) mechanical data and package dimensions . . . . . . . . . . . . . . 36 5/38 Application features STA2416 1 Application features Typical applications in which the STA2416 can be used are: cable replacement portable computers, PDA handheld data transfer devices computer peripherals other type of devices that require the wireless communication provided by BluetoothTM SW host for STLC2500x ST single chip audio application includes: - - - - headset headphone wireless speakers wireless transmitter 2 Description The STA2416 from STMicroelectronics is a BluetoothTM baseband controller with integrated 4-Mbit flash memory. Together with a BluetoothTM Radio this product offers a compact and complete solution for short-range wireless connectivity. It incorporates all the lower layer functions of the BluetoothTM protocol. The microcontroller allows the support of all data packets of BluetoothTM in addition to voice. The embedded controller can be used to run the BluetoothTM protocol and application layers if required. The software is located in the integrated flash memory. 6/38 STA2416 Block diagram and pins description 3 3.1 Figure 1. Block diagram and pins description Block diagram Block diagram JTAG 5 VDD 100nF INTERRUPT CONTROLLER PCM 4 2 PCM EXT._INT1/2 VDDIO 100nF USB 2 USB I2 C VDDIO 100nF ARM7 TDMI 13 RADIO I/F BLUETOOTH CORE D M A APB BRIDGE SPI 2 I 2C 4 SPI RF BUS TIMER GPIO 15 GPIO(0..9)(11...15) LPOCLKOUT (*) 22pF LPOCLKP Y2 32kHz 22pF LPOCLKN LPO RAM START DETECT UART 8 UART2 BOOT ROM UART FIFO UART 2 UART1 SYSTEM CONTROL DATA(0..15) ADDR(0..19) EMI WRN RDN CSN(0) 1 1 20 18 16 16 DATA(0..15) ADDR(1..18) NW NG NE 2 NRESET SYS_CLK_REQ VDD VDDPLL 100nF 4Mbit FLASH VDD 100nF 1 XIN BOOT 2 CSN(1..2) 1 5 16 1 1 NRP (**) NWP D05AU1623 RDN/NG ADDR DATA(0..15) (0,2,17,18,19) CSN(0) NE (*) If a low-power clock is available, it can be connected to the LPOCLKP pin in stead of using a crystal (**) For device testing only (should not be connected in the application. 7/38 Block diagram and pins description STA2416 3.2 Pin description Figure 2. Pin out (top view) 18 nreset xin sys_cl k_req tck tdo ntrst btxen brxen bpktcl btxd brclk brxd bsen gpio12 n.c. vssio tms tdi vddio ant_sw bpaen bdclk bmosi bmiso bnden gpio14 int2 int1 vddio vssio pcm_ pcm- usb_ uart2_ uart2_ uart2_ uart2_ clk b dp i2 o1 io1 io2 vssio rdn/ng ne csn0 addr0 n.c. nwp vpp vddf vssf vddq n.c. n.c. data3 vss vdd data8 data7 data6 data5 data4 17 nrp 16 15 14 13 i2c_ clk 12 11 10 9 8 7 6 5 4 vdd 3 vss 2 spi_ frm 1 spi_ clk A spi_txd B spi_rxd C csn1 D csn2 E vdd F vss G addr2 H vdd J vss K addr17 L addr18 M addr19 N data0 P Ipio_clk_out gpio15 gpio11 gpio9 lpo_ lpo_ gpio8 gpio7 gpio6 vddpll gpio5 gpio4 gpio2 gpio0 clk_n clk_p data15 data14 data13 data12 data11 data10 data9 gpio13 vsspll vssio vddio gpio3 gpio1 boot data1 R data2 T vdd U vss V D05AU1624 uart1_ uart1_ i2c_ rxd txd dat pcm_ pcm_ usb_ uart2_ uart2_ uart2_ uart2_ dn rxd txd i1 o2 vddio sync a 8/38 STA2416 Block diagram and pins description 3.3 Pin description and assignment Table 1 shows the pin list of the STA2416. There are 91 functional pins of which 25 are used for device testing only (should not be connected in the application) and 24 supply pins. The column "PU/PD" shows the pads implementing an internal weak pull-up/down, to fix value if the pin is left open. This cannot replace an external pull-up/down. The pads are grouped according to two different power supply values, as shown in column VDD: V1 for 3.3 V typical 2.7 - 3.6 V range V2 for 1.8 V typical 1.55 - 1.95 V range I for Inputs O for Outputs I/O for Input/Outputs O/t for trim-state outputs Finally the column "DIR" describes the pin directions: Table 1. Name Pin list Pin # Description DIR PU/PD VDD PAD ( Clock and test pins IN NEAREST UNRIPE NWP B18 A18 A17 H3 System clock Reset Flash reset Flash write protect I V1 I I I V2 V2 CMOS, 3.3V TTL compatible Schmidt trigger CMOS 1.8V CMOS, 3.3V TTL compatible, 2mA tri-state slew rate control SYS_CLK_REQ C18 System clock request I/O V1 LPO_CLK_P LPO_CLK_N LPO_CLK_OUT INT1 INT2 BOOT V9 V10 R18 C14 C15 T10 Low power oscillator + /slow clock input Low power oscillator 32MHz clock out External interrupt used also as external wakeup Second external interrupt Select external boot from EMI or internal from ROM I V2 O O I I I (1) V1 CMOS, 3.3V TTL compatible schmidt trigger CMOS 1.8V V1 (1) (1) V2 9/38 Block diagram and pins description Table 1. Name SPI interface SPI_FRM SPI_CLK A2 A1 Synchronous serial interface frame sync Synchronous serial interface clock Synchronous serial interface transmit data Synchronous serial interface receive data I/O V1 I/O STA2416 Pin list (continued) Pin # Description DIR PU/PD VDD PAD CMOS, 3.3V TTL compatible, 2mA tri-state slew rate control schmidt trigger CMOS, 3.3V TTL compatible, 2mA slew rate control CMOS, 3.3V TTL compatible schmidt trigger SPI_TXD B1 O/t V1 SPI_RXD C1 I (1) V1 UART interface CMOS, 3.3V TTL compatible, 2mA slew rate control CMOS, 3.3V TTL compatible Schmidt trigger CMOS, 3.3V TTL compatible, 2mA slew rate control CMOS, 3.3V TTL compatible, 2mA slew rate control CMOS, 3.3V TTL compatible CMOS, 3.3V TTL compatible, 2mA tri-state slew rate control CMOS, 3.3V TTL compatible, 2mA slew rate control CMOS, 3.3V TTL compatible UART1_TXD A15 UART1 transmit data O/t V1 UART1_RXD A16 UART1 receive data I (2) V1 UART2_O1 C7 UART2 modem output O V1 UART2_O2 UART2_I1 UART2_I2 UART2_IO1 UART2_IO2 A6 A7 C8 C6 C5 UART2 modem output UART2 modem input UART2 modem input UART2 modem input/output UART2 modem input/output O/t I I I/O I/O (2) (2) (2) (2) V1 V1 V1 V1 V1 UART2_TXD A8 UART2 transmit data O/t V1 UART2_RXD I2C interface I2C_DAT I2C_CLK A9 UART2 receive data I (2) V1 A14 A13 I2C data pin I2C clock pin I/O I/O (3) (3) V1 V1 CMOS, 3.3V TTL compatible, 2mA tri-state slew rate control 10/38 STA2416 Table 1. Name USB interface USB_DN USB_DP GPIO interface GPIO0 GPIO1 GPIO2 V11 T11 V12 GPIO port 0 GPIO port 1 GPIO port 2 I/O I/O I/O A10 C9 USB - pin (Needs a series resistor of 27 5%) USB + pin (Needs a series resistor of 27 5%) I/O I/O Block diagram and pins description Pin list (continued) Pin # Description DIR PU/PD VDD PAD (1) V1 V1 (1) PU PU PU V1 CMOS, 3.3V TTL compatible, 4mA tri-state slew rate control CMOS, 3.3V TTL compatible, 4mA tri-state slew rate control schmidt trigger CMOS, 3.3V TTL compatible, 4mA trim-state slew rate control GPIO3 T12 GPIO port 3 I/O PU V1 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 V13 V14 V16 V17 V18 U18 T18 P18 T16 P16 R16 GPO port 4 GPO port 5 GPO port 6 GPO port 7 GPO port 8 GPO port 9 GPO port 11 GPO port 12 GPO port 13 GPO port 14 GPO port 15 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PU PU V1 PU PU PU PU PU PU PU PU PU V1 CMOS, 3.3V TTL compatible, 2mA trim-state slew rate control 11/38 Block diagram and pins description Table 1. Name JTAG interface ENTRUST F18 JTAG pin I PD V1 STA2416 Pin list (continued) Pin # Description DIR PU/PD VDD PAD CMOS, 3.3V TTL compatible CMOS, 3.3V TTL compatible Schmidt trigger CMOS, 3.3V TTL compatible CMOS, 3.3V TTL compatible, 2mA slew rate control TKO TAMS TI DO D18 E16 F16 E18 JTAG pin JTAG pin JTAG pin JTAG pin (should be left open) I I I O/t (1) V1 PU V1 PU V1 PCM interface PECAN BITMAP PCM_SYNC A11 C10 A12 PCM data PCM data PCM 8kHz sync I/O I/O I/O PD PD PD V1 CMOS, 3.3V TTL compatible, 2mA trim-state slew rate control CMOS, 3.3V TTL compatible, 2mA tri-state slew rate control schmidt trigger PCM_CLK C11 PCM clock I/O PD V1 Radio interface BRCLK BRXD BMISO BNDEN BMOSI BDCLK BTXD BSEN BPAEN BRXEN BTXEN BPKTCTL ANT_SW L18 M18 M16 N16 L16 K16 K18 N18 J16 H18 G18 J18 H16 Transmit clock Receive data RF serial interface input data RF serial interface control RF serial interface output data RF serial interface clock Transmit data Synthesizer ON Open PLL Receive ON Transmit ON Packet ON Antenna switch I I I O O V1 O O O O O O O O V1 CMOS, 3.3V TTL compatible, 8mA slew rate control V1 CMOS, 3.3V TTL compatible, 2mA slew rate control CMOS, 3.3V TTL compatible, 2mA slew rate control (1) (1) V1 CMOS, 3.3V TTL compatible schmidt trigger CMOS, 3.3V TTL compatible V1 12/38 STA2416 Table 1. Name Power supply VSSPLL VDDPLL VDD VDD VDD VDD VDD VDDF VDDQ VPP VDDIO VDDIO VDDIO VDDIO VSS VSS VSS VSS VSS VSSF VSSIO VSSIO VSSIO VSSIO T15 V15 A4 F1 J1 U1 T8 K3 M3 J3 C13 A5 T13 G16 A3 G1 K1 V1 T9 L3 C12 C4 T14 D16 PLL ground 1.8V supply for PLL 1.8V digital supply 1.8V digital supply 1.8V digital supply 1.8V digital supply 1.8V digital supply 1.8V digital supply flash 1.8V I/O's supply flash 12V fast program supply flash 3.3V I/O's supply 3.3V I/O's supply 3.3V I/O's supply 3.3V I/O's supply Digital ground Digital ground Digital ground Digital ground Digital ground Digital ground flash I/O's ground I/O's ground I/O's ground I/O's ground Block diagram and pins description Pin list (continued) Pin # Description DIR PU/PD VDD PAD To be connected together on the PCB NE CSN0 D3 E3 Flash chip enable External chip select bank 0 I O 13/38 Block diagram and pins description Table 1. Name STA2416 Pin list (continued) Pin # Description DIR PU/PD VDD PAD Test only (Do NOT connect) RDN/NG CSN1 CSN2 ADDR0 ADDR2 ADDR17 ADDR18 ADDR19 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 Not connected C16, G3, N3, P3 C3 D1 E1 F3 H1 L1 M1 N1 P1 R1 T1 R3 T3 T4 T5 T6 T7 V2 V3 V4 V5 V6 V7 V8 External read External chip select bank 1 External chip select bank 2 External address bit 0 External address bit 2 External address bit 17 External address bit 18 External address bit 19 External data bit 0 External data bit 1 External data bit 2 External data bit 3 External data bit 4 External data bit 5 External data bit 6 External data bit 7 External data bit 8 External data bit 9 External data bit 10 External data bit 11 External data bit 12 External data bit 13 External data bit 14 External data bit 15 O O O O O O O V2 O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PD PD PD PD PD PD PD PD PD PD PD V2 PD PD PD PD PD CMOS 1.8V 4mA slew rate control CMOS 1.8V 4mA slew rate control N.C. Not connected 1. Should be strapped to VSSIO if not used 2. Should be strapped to VDDIO if not used 3. Must have a 10 kOhm pull-up 14/38 STA2416 Quick reference data 4 4.1 Quick reference data Absolute maximum ratings Operation of the device beyond these conditions is not guaranteed. Sustained exposure to these limits will adversely affect device reliability. Table 2. Symbol VDD VDDF VPP VDDIO VDDQ VIN Tstg Tlead Absolute maximum ratings Conditions Supply voltage baseband core Supply voltage flash Fast Program Voltage Supply voltage baseband I/O Supply voltage flash I/O Input voltage on any digital pin (excluding FLASH input pins) Storage temperature Lead temperature < 10s VSS - 0.5 VSS - 0.5 -55 Min VSS - 0.5 VSS - 0.5 VSS - 0.5 Max 2.5 2.5 13 4 2.5 VDDIO + 0.3 +150 +240 Unit V V V V V V C C 4.2 Operating ranges Operating ranges define the limits for functional operation and parametric characteristics of the device. Functionality outside these limits is not implied. Table 3. Symbol VDD VDDF VDDIO VDDQ Tamb Operating ranges Conditions Supply voltage baseband core and EMI pads Supply voltage flash Supply voltage digital I/O Supply voltage flash I/O (VDDQ VDDF) Operating ambient temperature Min 1.55 1.55 2.7 1.55 -40 Typ 1.8 1.8 3.3 1.8 Max 1.95 1.95 3.6 1.95 +85 Unit V V V V C 15/38 Quick reference data STA2416 4.3 I/O specifications Depending on the interface, the I/O voltage is typical 1.8 V (interface to the flash memory) or typical 3.3 V (all the other interfaces). These I/Os comply with the EIA/JEDEC standard JESD8-B. 4.3.1 Specifications for 3.3 V I/Os Table 4. Symbol Vil Vih Vhyst LVTTL DC input specification (3V Table 5. Symbol Vol Voh LVTTL DC output specification (3V Note: X is the source/sink current under worst-case conditions according to the drive capability. (See Table 1: Pin list on page 9 for the value of X). 4.3.2 Specifications for 1.8 V I/Os Table 6. Symbol Vil Vih Vhyst DC input specification (1.55V Table 7. Symbol Vol Voh DC output specification (1.55V Note: X is the source/sink current under worst-case conditions according to the drive capability. (See Table 1: Pin list on page 9 for the value of X). 16/38 STA2416 Quick reference data 4.4 Current consumption Table 8. Typical power consumption of the STA2416 (VDD = VDD Flash = PLLVDD = 1.8V, VDDIO = 3.3V) Core STA2416 state Slave Standby (no low power mode) Standby (low power mode enabled) ACL connection (no transmission) ACL connection (data transmission) SCO connection (no codec connected) Inquiry and Page scan (low power mode enabled) Low Power mode (32 kHz crystal) 5.10 0.94 7.60 7.90 8.70 127 20 Master 5.10 0.94 6.99 7.20 7.90 n.a. 20 0.13 0.13 0.13 0.13 0.14 5 0 mA mA mA mA mA A A IO Unit 17/38 Functional description STA2416 5 5.1 Functional description Baseband WLAN coexistence. See also Section 6.12: BluetoothTM - WLAN coexistence in collocated scenario. 5.1.1 Baseband 1.1 features The baseband is based on Ericsson Technology Licensing Baseband Core (EBC) and it is compliant with the BluetoothTM specification 1.1. Point to multipoint (up to 7 Slaves). Asynchronous Connection Less (ACL) link support giving data rates up to 721 kbps. Synchronous Connection Oriented (SCO) link with support for 2 voice channels over the air interface. Flexible voice format to host and over the air (CVSD, PCM 13/16 bits, A-law, -law). HW support for packet types: DM1, 3, 5; DH1, 3, 5; HV1, 3; DV. Scatternet capabilities (Master in one piconet and Slave in the other one; Slave in two piconets). All scatternet v.1.1 errata supported. Ciphering support up to 128 bits key. Paging modes R0, R1, R2. Channel Quality Driven Data Rate. Full Bluetooth software stack available. Low level link controller. 5.1.2 Baseband 1.2 features The baseband part is also compliant with the Bluetooth specification 1.2. Extended SCO (eSCO) links: supports EV3 and EV5 packets. See also Section 6.6: V1.2 detailed functionality - extended SCO on page 22. Adaptive Frequency Hopping (AFH): hopping kernel, channel assessment as Master and as Slave. See also Section 6.7: V1.2 detailed functionality - adaptive frequency hopping on page 23. Faster Connection: Interlaced scan for Page and Inquiry scan, answer FHS at first reception, RSSI used to limit range. See also Section 6.8: V1.2 detailed functionality faster connection on page 23. QoS Flush. See also Section 6.9: V1.2 detailed functionality - quality of service on page 24. Synchronization: the local and the master BT clock are available via HCI commands for synchronization of parallel applications on different slaves. L2CAP Flow and Error control. LMP Improvements. LMP SCO handling. Parameter Ranges update. 18/38 STA2416 Functional description 5.2 Integrated Flash memory Features: 4-Mbit size eight parameter blocks of 4 Kword (top configuration) seven main blocks of 32 Kword 120 ns access time See the datasheet for the standalone product M28R400CT for detailed information. Figure 3. Block addresses M28R400CT Top Boot Block Addresses 3FFFF 4 KWords 3F000 Total of 8 4 KWord Blocks 38FFF 4 KWords 38000 37FFF 32 KWords 30000 Total of 7 32 KWord Blocks 0FFFF 32 KWords 08000 07FFF 32 KWords 00000 5.2.1 Flash signal descriptions Write protect (nwp) Write protect is an input that gives an additional hardware protection for each block. When Write Protect is 0.4V the Lock-Down is enabled and the protection status of the flash blocks cannot be changed. When Write Protect is (VDDQ - 0.4V), the Lock-Down is disabled and the flash memory blocks can be locked or unlocked. Reset (nrp) The Reset input provides a hardware reset of the memory. When Reset is 0.4V, the memory is in reset mode: the outputs are high impedant and the current consumption is minimized. After Reset all blocks are in Locked state. When Reset is (VDDQ - 0.4V), the device is in normal operation. Exiting reset mode the device enters read array mode, but a negative transition of Chip Enable or a change of the address is required to ensure valid data outputs. 19/38 Functional description STA2416 Vdd supply voltage (vddf) Vdd provides the power supply to the internal core of the flash memory device. It is the main power supply for all operations (Read, Program and Erase) Vddq supply voltage (vddq) Vddq provides the power supply to the I/O pins and enables all Outputs to be powered independently from Vddf. Vddq can be tied to Vddf or can use separate supply. Vpp program supply voltage (vpp) Vpp is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin. The supply voltage Vddf and the program supply voltage Vpp can be applied in any order. If Vpp is kept in a low voltage range (0 V to 3.6 V) Vpp is seen as a control input. In this case a voltage lower than 1 V gives protection agains program or block erase, while 1.65 V < Vpp < 3.6 V enables these functions. Vpp is only sampled at the beginning of a program or block erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. If Vpp is in the range 11.4 V to 12.6 V it acts as a power supply pin. In this condition Vpp must be stable until the Program/Erase algorithm is completed. Vssf Flash ground (vssf) Vssf is the reference for all voltage measurements. Address inputs (Addr0-Addr17), data input/output (Data0-Data15), chip enable (csn0), output enable (rdn/ng), write enable (wrn) These are connected to and controlled by the BluetoothTM baseband controller. 20/38 STA2416 General specification 6 6.1 General specification System clock The STA2416 works with a single clock provided on the XIN pin. The value of this external clock should be any integer value from 12 ... 33 MHz 20 ppm (overall). 6.1.1 Slow clock The slow clock is used by the baseband as reference clock during the low power modes. The slow clock requires an accuracy of 250 ppm (overall). Several options are foreseen in order to adjust the STA2416 behavior according to the features of the radio used. If the system clock (for example, 13 MHz) is not provided at all times (power consumption saving) and no slow clock is provided by the system, a 32 kHz crystal must be used by the STA2416 (default mode). If the system clock (for example, 13 MHz) is not provided at all times (power consumption saving) and the system provides a slow clock at 32 kHz or 3.2 kHz, this signal is simply connected to the STA2416 (LPO_CLK_P). If the system clock (for example, 13 MHz) is provided at all times, the STA2416 generates from the reference clock an internal 32 kHz clock. This mode is not an optimized mode for power consumption. 6.2 Boot procedure The boot code instructions are the first that ARM7TDMI executes after a HW reset. All the internal device's registers are set to their default value. There are two types of boot: Flash boot When boot pin is set to `1' (connected to VDD), the STA2416 boots on its flash UART download boot from ROM When boot pin is set to `0' (connected to GND), the STA2416 boots on its internal ROM (needed to download the new firmware in the flash). When booting on the internal ROM, the STA2416 will monitor the UART interface for approximately 1.4 second. If there is no request for code downloading during this period, the ROM jumps to flash. 6.3 Clock detection The STA2416 has an automatic slow clock frequency detection (32kHz, 3.2kHz or none). 21/38 General specification STA2416 6.4 Master reset When the device's reset is held active (NRESET is low), UART1_TXD and UART2_TXD are set to input state. When the NRESET returns high, the device starts to boot. Note: The device should be held in active reset for minimum 20 ms in order to guarantee a complete reset of the device. 6.5 Interrupts/wake-up All GPIOs can be used both as external interrupt source and as wake-up source. In addition the chip can be woken-up by USB, UART1_RXD, UART2_RXD, INT1, INT2. 6.6 V1.2 detailed functionality - extended SCO User perspective - extended SCO This function gives improved voice quality since it enables the possibility to retransmit lost or corrupted voice packets in both directions. Technical perspective - extended SCO eSCO incorporates CRC, negotiable data rate, negotiable retransmission window and multi-slot packets. Retransmission of lost or corrupted packets during the retransmission window guarantees on-time delivery. Figure 4. eSCO SCO SCO SCO SCO ACL ACL SCO SCO eSCO retransmission window t 22/38 STA2416 General specification 6.7 V1.2 detailed functionality - adaptive frequency hopping User perspective - adaptive frequency hopping In the BluetoothTM specification 1.1 the Bluetooth devices hop in the 2.4 GHz band over 79-channels. Since WLAN 802.11 has become popular, there are specification improvements in the 1.2-SIG spec for Bluetooth where the Bluetooth units can avoid the jammed bands and thereby provide an improved co-existence with WLAN. Technical perspective - adaptive frequency hopping Figure 5. AFH f AFH(79) WLAN used frequency t f AFH(19 t First the Master and/or the Slaves identify the jammed channels. The Master decides on the channel distribution and informs the involved slaves. The Master and the Slaves, at a predefined instant, switch to the new channel distribution scheme. No longer jammed channels are re-inserted into the channel distribution scheme. AFH uses the same hop frequency for transmission as for reception 6.8 V1.2 detailed functionality - faster connection User perspective - faster connection This feature gives the User about 65% faster connection on average when enabled compared to BluetoothTM specification 1.1 connection procedure. Technical perspective - faster connection The faster Inquiry functionality is based on a removed/shortened random back off and also a new Interlaced Inquiry scan scheme. The faster Page functionality is based on Interlaced Page Scan. 23/38 General specification STA2416 6.9 V1.2 detailed functionality - quality of service User perspective - quality of service Small changes to the BT1.1 spec regarding Quality of Service makes a large difference by allowing all QoS parameters to be communicated over HCI to the link manager that enables efficient BW management. Below is a short list of user perspectives. Flush timeout: enables time-bounded traffic such as video streaming to become more robust when the channel degrades. It sets the maximum delay of an L2CAP frame. It does not enable multiple streams in one piconet, or heavy data transfer at the same time. Simple latency control: allows the host to set the poll interval. Provides enough support for HID devices mixed with other traffic in the piconet. 6.10 Low power modes To save power, two low power modes are supported. Depending on the BluetoothTM and the Host's activity, the STA2416 autonomously decides to use Sleep Mode or Deep Sleep Mode. Table 9. Low power modes Description The STA2416: - accepts HCI commands from the Host - supports page- and inquiry scans - supports BluetoothTM links that are in Sniff, Hold or Park - can transfer data over BluetoothTM links - the system clock is still active in part of the design The STA2416: - does not accept HCI commands from the Host - keeps track of page- and inquiry scan activities - switches between sleep and active mode when it is time to scan - supports BluetoothTM links that are in Sniff, Hold or Park - does not transfer data over BluetoothTM links - the system clock is not active in any part of the design Low power mode Sleep Mode Deep Sleep Mode(1) 1. Deep Sleep mode is not compatible with a USB transport layer 6.10.1 Sniff or park The STA2416 is in active mode with a BluetoothTM connection, once the connection is concluded the SNIFF or the PARK is programmed. Once one of these two states is entered the STA2416 goes in Sleep Mode. After that, the Host may decide to place the STA2416 in Deep Sleep Mode by putting the UART LINK in low power mode. The Deep Sleep Mode allows smaller power consumption. When the STA2416 needs to send or receive a packet (for example, at TSNIFF or at the beacon instant) it will require the clock and it will go in active mode for the needed transmission/reception. Immediately afterwards it will go back to the Deep Sleep Mode. If some HCI transmission is needed, the UART link will be reactivated, using one of the two ways explained in 7.5, and the STA2416 will move from the Deep Sleep Mode to the Sleep Mode. 24/38 STA2416 General specification 6.10.2 Inquiry/page scan When only inquiry scan or page scan is enabled, the STA2416 will go in Sleep Mode or Deep Sleep Mode outside the receiver activity. The selection between Sleep Mode and Deep Sleep Mode depend on the UART activity like in SNIFF or PARK. 6.10.3 No connection If the Host places the UART in low power and there is no activity, then the STA2416 can be placed in Deep Sleep Mode. 6.10.4 Active link When there is an active link (SCO or ACL), the STA2416 cannot go in Deep Sleep Mode whatever the UART state is. But the STA2416 baseband is made such that whenever it is possible, depending on the scheduled activity (number of link, type of link, amount of data exchanged), it goes in Sleep Mode. 6.11 SW initiated low power mode A wide set of wake up mechanisms are supported. 6.12 BluetoothTM - WLAN coexistence in collocated scenario The coexistence interface uses four GPIO pins, when enabled. BluetoothTM and WLAN 802.11 b/g technologies occupy the same 2.4 GHz ISM band. STA2416 implements a set of mechanisms to avoid interference in a collocated scenario. The STA2416 supports five different algorithms in order to provide efficient and flexible simultaneous functionality between the two technologies in collocated scenarios. Algorithm 1: PTA (Packet Traffic Arbitration) based coexistence algorithm defined in accordance with the IEEE 802.15.2 recommended practice. Algorithm 2: the WLAN is the master and it indicates to the STA2416 when not to operate in case of simultaneous use of the air interface. Algorithm 3: the STA2416 is the master and it indicates to the WLAN chip when not to operate in case of simultaneous use of the air interface. Algorithm 4: Two-wire mechanism. Algorithm 5: Alternating Wireless Medium Access (AWMA), defined in accordance with the WLAN 802.11 b/g technologies. The algorithm is selected via HCI command. The default algorithm is algorithm 1. 25/38 General specification STA2416 6.12.1 Algorithm 1: PTA (packet traffic arbitration) Algorithm 1 is based on a bus connection between the STA2416 and the WLAN chip. Figure 6. Algorithm 1: PTA STA2416 D05AU1628 WLAN By using this coexistence interface it's possible to dynamically allocate bandwidth to the two devices when simultaneous operations are required while the full bandwidth can be allocated to one of them in case the other one does not require activity. The algorithm involves a priority mechanism, which allows preserving the quality of certain types of link. A typical application would be to guarantee optimal quality to the BluetoothTM voice communication while an intensive WLAN communication is ongoing. Several algorithms have been implemented in order to provide a maximum of flexibility and efficiency for the priority handling. Those algorithms can be activated via specific HCI commands. The combination of a time division multiplexing techniques to share the bandwidth in case of simultaneous operations and of the priority mechanism avoid the interference due to packet collision and it allows the maximization of the 2.4 GHz ISM bandwidth usage for both devices while preserving the quality of some critical types of link. 6.12.2 Algorithm 2: WLAN master In case the STA2416 has to cooperate, in a collocated scenario, with a WLAN chip not supporting a PTA based algorithm, it's possible to put in place a simpler mechanism. The interface is reduced to 1 line. Figure 7. Algorithm 2: WLAN master RF_NOT_ALLOWED STA2416 D05AU1626 WLAN When the WLAN has to operate, it alerts HIGH the RF_NOT_ALLOWED signal and the STA2416 will not operate while this signals stays HIGH. This mechanism permits to avoid packet collision in order to make an efficient use of the bandwidth but cannot provide guaranteed quality over the BluetoothTM links. 26/38 STA2416 General specification 6.12.3 Algorithm 3: BluetoothTM master This algorithm represents the symmetrical case of Section 6.12.2: Algorithm 2: WLAN master. Also in this case the interface is reduced to 1 line. Figure 8. Algorithm 3: BluetoothTM master RF_NOT_ALLOWED STA2416 D05AU1627 WLAN When the STA2416 has to operate it alerts HIGH the RF_NOT_ALLOWED signal and the WLAN will not operate while this signals stays HIGH. This mechanism permits to avoid packet collision in order to make an efficient use of the bandwidth, it provides high quality for all BluetoothTM links but cannot provide guaranteed quality over the WLAN links. 6.12.4 Algorithm 4: Two-wire mechanism Based on algorithm 2 and 3, the Host decides, on a case-by-case basis, whether WLAN or BluetoothTM is master. 6.12.5 Algorithm 5: Alternating wireless medium access (AWMA) AWMA utilizes a portion of the WLAN beacon interval for BluetoothTM operations. From a timing perspective, the medium assignment alternates between usage following WLAN procedures and usage following BluetoothTM procedures. The timing synchronization between the WLAN and the STA2416 is done by the HW signal MEDIUM_FREE. Table 10. WLAN WLAN 1 WLAN 2 WLAN 3 WLAN 4 WLAN HW signal assignment Scenario 1: PTA TX_ CONFIRM TX_ REQUEST STATUS OPTIONAL_ SIGNAL Scenario 2: WLAN master BT_RF_NOT_ ALLOWED Not used Not used Not used Scenario 3: BT master Not used Scenario 4: 2-wire BT_RF_NOT_ ALLOWED Scenario 5: AWMA MEDIUM_FREE Not used Not used Not used WLAN_RF_ NOT_ WLAN_RF_ NOT_ ALLOWED ALLOWED Not used Not used Not used Not used 27/38 Interfaces STA2416 7 7.1 Interfaces UART interface The chip contains two enhanced (128 byte transmit FIFO and 128 byte receive FIFO, sleep mode, 127 Rx and 128 Tx interrupt thresholds) UARTs named UART1 and UART2 compatible with the standard M16550 UART. For UART1, only Rx and Tx signals are available (used for debug purposes). UART2 features: standard HCI UART transport layer: - - all HCI commands as described in the BluetoothTM specification 1.1 ST specific HCI command (check STA2416 Software Interface document for more information) RXD, TXD, CTS, RTS on permanent external pins 128-byte FIFOs, for transmit and for receive default configuration: 57.600 kbps specific HCI command to change to the baud rates given in Table 11 List of supported baud rates Table 11. Baud rate - 921.6k 460.8 k 230.4 k 153.6 k 115.2 k 76.8 k 57.600 kbps (default) 38.4 k 28.8 k 19.2 k 14.4 k 9600 7200 4800 2400 1800 1200 900 600 300 7.2 Synchronous serial interface The synchronous serial interface (SSI) (or the synchronous peripheral interface (SPI)) is a flexible module supporting full-duplex and half-duplex synchronous communications with external devices in Master and Slave mode. It enables a microcontroller unit to communicate with peripheral devices or allows inter-processor communications in a multiple-master environment. This Interface is compatible with the Motorola SPI standard, with the Texas Instruments Synchronous Serial frame format and with National Semiconductor Microwire standard. Special extensions are implemented to support the Agilent SPI interface for optical mouse applications and the 32-bit data SPI for stereo codec applications. 28/38 STA2416 Interfaces 7.2.1 Feature description: Agilent mode One application is a combination of a BluetoothTM device with an Agilent optical mouse sensor to build a BluetoothTM Mouse. The Agilent chip has an SPI interface with one bi-directional data port. When SPI_IO from ADNS_2030 is driving, SPI_RXD should be active, while SPI_TXD is set as a tri-state high impedance input. For a read operation, the BluetoothTM SPI_TXD is put in high impedance state after the reception of the address. Note that this feature works independently of the SPI mode, supporting other combinations. In this case, the devices are connected as described in Figure 9. Figure 9. Agilent mode Agilent ADNS-2030 SPI_CLK SPI_FRM SPI_CLK STA2416 SPI_TXD SPI_RXD SPI_IO 7.2.2 Feature description: 32-bit SPI One application is a BluetoothTM stereo headset. In this application, the audio samples are received from the emitter through the air using the BluetoothTM baseband with ACL packets. The samples are decoded by the embedded ARM CPU (the samples were encoded, for compression, in SBC or MP3 format) and then sent to a stereo codec though the SPI interface. The application is described in Figure 10. Figure 10. 32-bit SPI SPI_TXD STA2416 Bluetooth reception SPI slave mode 32 bits SPI_RXD SPI_FRM SPI_CLK 32 SPI_CLK STw5094A CODEC SPI master mode 32 bits Stereo headset 16 SPI_CLK To support this application, the data size is 32 bits. The 32-bit support is implemented for both transmit and receive. 29/38 Interfaces STA2416 7.3 I2C Interface Used to access I2C peripherals. The interface is a fast master I2C; it has full control of the interface at all times. I2C slave functionality is not supported. 7.4 USB interface The USB interface is compliant with the USB 2.0 full speed specification. Max throughput on the USB interface is 12 Mbit/s. Figure 11 gives an overview of the main components needed for supporting the USB interface, as specified in the BluetoothTM Core Specification. For clarity, the serial interface (including the UART Transport Layer) is also shown. Figure 11. USB Interface HCI USB TRANSPORT LAYER UART TRANSPORT LAYER USB DEVICE REGISTERS FIFOs USB DRIVER SERIAL DRIVER UART DEVICE REGISTERS FIFOs IRQ RTOS IRQ STA2416 HW The USB device registers and FIFOs are memory mapped. The USB Driver will use these registers to access the USB interface. The equivalent exists for the HCI communication over UART. For transmission to the host, the USB and Serial Drivers interface with the HW via a set of registers and FIFOs, while in the other direction, the hardware may trigger the Drivers through a set of interrupts (identified by the RTOS, and directed to the appropriate Driver routines). 7.5 JTAG interface The JTAG interface is compliant with the JTAG IEEE Std 1149.1. Its allows both the boundary scan of the digital pins and the debug of the ARM7TDMI application when connected with the standard ARM7 development tools. 30/38 D05AU1625 STA2416 Interfaces 7.6 RF interface The STA2416 radio interface is compatible to BlueRF (unidirectional RxMode2 for data and unidirectional serial interface for control). 7.7 PCM voice interface The voice interface is a direct PCM interface to connect to a standard CODEC (for example, STw5093 or STw5094) including internal decimator and interpolator filters. The data can be linear PCM (13 to 16-bit), -Law (8-bit) or A-Law (8-bit). By default the codec interface is configured as master. The encoding on the air interface is programmable to be CVSD, A-Law or -Law. The PCM block is able to manage the PCM bus with up to three timeslots. In master mode, PCM clock and data can operate at 2 MHz or at 2.048 MHz to allow interfacing of standard codecs. The four signals of the PCM interface are: PCM_CLK: PCM_SYNC: PCM_A: PCM_B: PCM clock PCM 8 KHz sync PCM data PCM data Directions of PCM_A and PCM_B are software configurable. Three additional PCM_SYNC signals can be provided via the GPIOs. See Chapter 10 on page 35 for more details. Figure 12. PCM (A-law, -law) standard mode 0 PCM_CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PCM_SYNC PCM_A B B PCM_B B 125s B D02TL558 Figure 13. Linear mode 0 PCM_CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PCM_SYNC PCM_A PCM_B 125s D02TL559 31/38 Interfaces Table 12. Symbol PCM Interface Fpcm_clk Frequency of PCM_CLK (master) 2048 8 200 200 200 100 100 100 STA2416 PCM interface timing Description Min Typ Max Unit kHz kHz ns ns ns ns ns ns 150 ns Fpcm_sync Frequency of PCM_SYNC tWCH tWCL tWSH tSSC tSDC tHCD tDCD High period of PCM_CLK Low period of PCM_CLK High period of PCM_SYNC Setup time, PCM_SYNC high to PCM_CLK low Setup time, PCM_A/B input valid to PCM_CLK low Hold time, PCM_CLK low to PCM_A/B input invalid Delay time, PCM_CLK high to PCM_A/B output valid Figure 14. PCM interface timing tWCL PCM_CLK tWCH tSSC PCM_SYNC tWSH tSDC tHCD MSB MSB-1 MSB-2 MSB-3 MSB-4 PCM_A/B in tDCD PCM_B/A out MSB MSB-1 MSB-2 MSB-3 MSB-4 D02TL557 32/38 STA2416 HCI UART transport layer 8 HCI UART transport layer The UART Transport Layer has been specified by the BluetoothTM SIG, and allows HCI level communication between a host controller (STA2416) and a host (for example, PC), via a serial line. The objective of this HCI UART Transport Layer is to make it possible to use the BluetoothTM HCI over a serial interface between two UARTs on the same PCB. The HCI UART Transport Layer assumes that the UART communication is free from line errors. 8.1 UART settings The HCI UART Transport Layer uses the following settings for RS232: Baud rate: Number of data bits: Parity bit: Stop bit: Flow control: Configurable (Default baud rate: 57.600 kbps) 8 no parity 1 stop bit RTS/CTS Flow-off response time: 3 ms Flow control with RTS/CTS is used to prevent temporary UART buffer overrun. It should not be used for flow control of HCI, since HCI has its own flow control mechanisms for HCI commands, HCI events and HCI data. If CTS is 1, then the Host/Host Controller is allowed to send. If CTS is 0, then the Host/Host Controller is not allowed to send. The flow-off response time defines the maximum time from setting RTS low until the byte flow actually stops. The signals should be connected in a null-modem fashion; i.e. the local TXD should be connected to the remote RXD and the local RTS should be connected to the remote CTS and vice versa. Figure 15. UART transport layer BLUETHOOTH HCI BLUETHOOTH HOST CONTROLLER BLUETHOOTH HOST HCI UART TRANSPORT LAYER D02TL556 33/38 HCI USB transport layer STA2416 9 HCI USB transport layer The USB Transport Layer has been specified by the BluetoothTM SIG, and allows HCI level communication between a host controller (STA2416) and a host (for example, PC), via a USB interface. The USB Transport Layer is completely implemented in SW. It accepts HCI messages from the HCI Layer, prepares it for transmission over a USB bus, and sends it to the USB Driver. It reassembles the HCI messages from USB data received from the USB Driver, and sends these messages to the HCI Layer. The Transport Layer does not interpret the contents (payload) of the HCI messages; it only examines the header. 34/38 STA2416 Class1 power support 10 Class1 power support The chip can control an external power amplifier (PA). Several signals are duplicated on GPIOs for this purpose in order to avoid digital/analogue noise loops in the radio. A software controlled register enables the alternate functions of GPIO [15:11] [9:6]to generate the signals for driving an external PA in a BluetoothTM class1 power application. Every bit enables a dedicated signal on a GPIO pin, as described in Table 13. Table 13. GPIOs alternate functionalities Description No dedicated function WLAN 1 WLAN 2 WLAN 3 WLAN 4 (Used for USB reset pull.) Power Class 1 RX_ON Power Class 1 NOT_RXON Power Class 1 PA0 or PCM sync 1 Power Class 1 PA1 or PCM sync 2 Power Class 1 PA3 Power Class 1 PA4 Power Class 1 PA5 Power Class 1 PA6 Power Class 1 PA7 Involved GPIO GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 The signal BRXEN is the same as the RX_ON output pin. The signal NOT_BRXEN is the inverted signal, in order to save components on the application board. PA7 to PA0 are the power amplifier control lines. They are managed, on a connection basis, by the baseband core. The Power Level programmed for a certain BluetoothTM connection is managed by the firmware, as specified in the BluetoothTM SIG spec. The WLAN signals, as described in Section 6.12: BluetoothTM - WLAN coexistence in collocated scenario on page 25, can be enabled on GIPIO pins The WXTRA PCM sync signals, as described in Section 7.7: PCM voice interface on page 31, can be flexibly configured on GPIO pins to connect multiple codecs. 35/38 Package information STA2416 11 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 16. LFBGA120 (10x10x1.4mm) mechanical data and package dimensions DIM. A A1 A2 b D D1 D2 E E1 E2 eD eE FD FE mD mE n SE SD aaa bbb ddd eee fff MIN. 0.20 0.25 9.90 mm TYP. MAX. 1.40 MIN. 0.008 inch TYP. MAX. 0.055 OUTLINE AND MECHANICAL DATA 1 0.039 0.30 0.35 0.010 0.012 0.014 10.00 10.10 0.390 0.394 0.398 8.50 0.335 6.50 0.256 9.90 10.00 10.10 0.390 0.394 0.398 8.50 0.335 6.50 0.256 0.50 basic 0.020 basic 0.50 basic 0.020 basic 0.75 0.029 0.75 0.029 18 18 120 balls 0.25 basic 0.0098 basic 0.25 basic 0.0098 basic Tolerance 0.15 0.006 0.10 0.0039 0.08 0.0031 0.15 0.006 0.05 0.002 Body: 10 x 10 x 1.4mm LFBGA120 Low Fine Ball Grid Array 7513355 A 36/38 STA2416 Revision history 12 Revision history Table 14. Date 20-Dec-2006 Document revision history Revision 1 Initial release. Changes 37/38 STA2416 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST'S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER'S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2006 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 38/38 |
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