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LOW SKEW, 1-TO-4 DIFFERENTIAL-TOLVDS FANOUT BUFFER
ICS889832
GENERAL DESCRIPTION
The ICS889832 is a high speed 1-to-4 DifferentialIC S to-LVDS Fanout Buffer and is a member of the HiPerClockSTM HiPerClockSTM family of high performance clock solutions from IDT. The ICS889832 is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The internally terminated differential input and VREF_AC pin allow other differential signal families such as LVPECL, LVDS, and SSTL to be easily interfaced to the input with minimal use of external components. The device also has an output enable pin which may be useful for system test and debug purposes. The ICS889832 is packaged in a small 3mm x 3mm 16-pin VFQFN package which makes it ideal for use in spaceconstrained applications.
FEATURES
* Four differential LVDS outputs * IN, nIN pair can accept the following differential input levels: LVPECL, LVDS, SSTL * 50 internal input termination to VT * Output frequency: >2GHz * Output skew: 25ps (maximum) * Part-to-part skew: 200ps (maximum) * Additive phase jitter, RMS: <0.2ps (typical) * Propagation delay: 510ps (maximum) * 2.5V operating supply * -40C to 85C ambient operating temperature * Available in both standard (RoHS 5) and lead-free (RoHS 6) packages
BLOCK DIAGRAM
Q0 nQ0 IN
50
PIN ASSIGNMENT
nQ0
Q1 1 nQ1 2 Q2 3
16 15 14 13 12 11 10 9 5
Q3
VDD
Q0
GND
IN VT VREF_AC nIN
Q1 nQ1
50
nQ2 4 6
nQ3
7
VDD
8
EN
VT nIN
Q2 VREF_AC EN
D Q
nQ2
ICS889832
16-Lead VFQFN 3mm x 3mm x 0.95 package body K Package Top View
Q3 nQ3
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TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 4 5, 6 7, 14 Name Q1, nQ1 Q2, nQ2 Q3, nQ3 VDD Type Output Output Output Power Description Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Positive supply pins. Synchronizing clock enable. When LOW, Q outputs will go LOW and nQ outputs will go HIGH on the next LOW transition at IN inputs. Input threshold is VDD/2V. Includes a 37k pull-up resistor. Default state is HIGH when left floating. The internal latch is clocked on the falling edge of the input signal IN. LVTTL / LVCMOS interface levels. Inver ting differential clock input. 50 internal input termination to VT. Reference voltage for AC-coupled applications. Termination input. Non-inver ting differential clock input. 50 internal input termination to VT. Power supply ground.
8
EN
Input
Pullup
9 10 11 12 13
nIN VREF_AC VT IN GND
Input Output Input Input Power
15, 16 Q0, nQ0 Output Differential output pair. LVDS interface levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol RPULLUP Parameter Input Pullup Resistor Test Conditions Minimum Typical 37 Maximum Units k
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TABLE 3A. CONTROL INPUT FUNCTION TABLE
Input EN 0 Q0:Q3 Disabled; LOW Outputs nQ0:nQ3 Disabled; HIGH
1 Enabled Enabled After EN switches, the clock outputs are disabled or enabled following a falling input clock edge as shown in Figure 1.
EN
VDD/2 tS tH VDD/2
nIN IN nQx Qx
VIN
tPD
VOUT Swing
FIGURE 1. EN TIMING DIAGRAM
TABLE 3B. TRUTH TABLE
Inputs IN 0 1 X nI N 1 0 X EN 1 1 0 0 1 0(NOTE1) Outputs Q0:Q3 nQ0:nQ3 1 0 1(NOTE1)
NOTE 1: On next negative transition of the input signal (IN).
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ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, IO (LVDS) Continuous Current Surge Current Input Current, IN, nIN VT Current, IVT Input Sink/Source, IREF_AC Operating Temperature Range, TA Storage Temperature, TSTG Package Thermal Impedance, JA
(Junction-to-Ambient)
4.6V -0.5V to VDD + 0.5 V 10mA 15mA 50mA 100mA 0.5mA -40C to +85C -65C to 150C 51.5C/W (0 lfpm)
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V 5%; TA = -40C TO 85C
Symbol VDD IDD Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 2.375 Typical 2.5 Maximum 2.625 120 Units V mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 2.5V 5%; TA = -40C TO 85C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current EN EN VDD = VIN = 2.625V VDD = 2.625V, VIN = 0V -150 Test Conditions Minimum 1.7 0 Typical Maximum VDD + 0.3 0.7 5 Units V V A A
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 2.5V 5%; TA = -40C TO 85C
Symbol RIN VIH VIL VIN VREF_AC VDIFF_IN IIN Parameter Differential Input Resistance Input High Voltage Input Low Voltage Input Voltage Swing Reference Voltage Differential Input Voltage Swing Input Current; NOTE 1 (IN, nIN) (IN, nIN) (IN, nIN) (IN, nIN) Test Conditions IN-to-VT Minimum 40 1.2 0 0.15 VDD - 1.42 0.3 VDD - 1.37 Typical 50 Maximum 60 VDD VIH - 0.15 2.8 VDD - 1.32 3.4 35 Units V V V V V mA
NOTE 1: Guaranteed by design.
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TABLE 4D. LVDS DC CHARACTERISTICS, VDD = 2.5V 5%; TA = -40C TO 85C
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change 1 1.25 Test Conditions Minimum 0.3 Typical 0.4 Maximum 0.5 50 1.5 50 Units mV mV V mV
TABLE 5. AC CHARACTERISTICS, VDD = 2.5V 5%; TA = -40C TO 85C
Symbol fMAX Parameter Maximum Output Frequency Propagation Delay; (Differential); NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section Output Rise/Fall Time Clock Enable Setup Time Clock Enable Hold Time EN to IN, nIN EN to IN, nIN Integration Range: 12kHz - 20MHz 20% to 80% 70 300 300 Condition Minimum Typical >2 275 390 510 25 200 <0.2 150 235 Maximum Units GHz ps ps ps ps ps ps ps
t PD t sk(o) t sk(pp) t jit
tR/tF tS tH
All parameters are measured at 1GHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz
0 -10 -20 -30 -40 -50 -60
band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 200MHz (12kHz to 20MHz) = <0.2ps (typical)
SSB PHASE NOISE dBc/HZ
-70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device
meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment.
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PARAMETER MEASUREMENT INFORMATION
VDD
SCOPE
2.5V5% POWER SUPPLY + Float GND -
VDD
Qx
nIN
LVDS
nQx
V
IN
Cross Points
V
IH
IN
V
IL
GND
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx PART 1 Qx nQy PART 2 Qy
nQx Qx nQy Qy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nIN
80% Clock Outputs
80% VOD
IN nQ0:nQ3 Q0:Q3
20% tR tF
20%
tPD
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
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nIN IN VIN, VOUT VDIFF_IN, VDIFF_OUT 800mV (typical)
EN
t HOLD t SET-UP
400mV (typical)
SETUP & HOLD TIME
SINGLE ENDED & DIFFERENTIAL INPUT VOLTAGE SWING
VDD

VDD
out
out
out
VOS/ VOS
DIFFERENTIAL OUTPUT VOLTAGE SETUP
OFFSET VOLTAGE SETUP
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DC Input
LVDS
DC Input
out
100
VOD/ VOD
LVDS
ICS889832 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
APPLICATION INFORMATION
LVPECL INPUT WITH BUILT-IN 50 TERMINATIONS INTERFACE
The IN /nIN with built-in 50 terminations accepts LVDS, LVPECL, LVHSTL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 1A to 1f show interface examples for the HiPerClockS IN/nIN input with built-in 50 terminations driven by the most common
3.3V or 2.5V 2.5V
driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
2.5V
2.5V
Zo = 50 Ohm IN Zo = 50 Ohm LVDS VT nIN
Zo = 50 Ohm IN Zo = 50 Ohm VT nIN 2.5V LVPECL R1 18
Receiver With Built-In 50 Ohm
Receiver With Built-In 50 Ohm
FIGURE 1A. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY AN LVDS DRIVER
FIGURE 1B. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY AN LVPECL DRIVER
2.5V
2.5V
2.5V
2.5V
Zo = 50 Ohm IN Zo = 50 Ohm VT nIN CML - Open Collector
Zo = 50 Ohm IN Zo = 50 Ohm VT nIN CML - Built-in 50 Ohm Pull-up
Receiver With Built-In 50 Ohm
Receiver With Built-In 50 Ohm
FIGURE 1C. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY AN OPEN COLLECTOR CML DRIVER
FIGURE 1D. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY A CML DRIVER WITH BUILT-IN 50 PULLUP
2.5V 3.3V
3.3V 2.5V
3.3V LVPECL
Zo = 50 Ohm
C1 IN 50 Ohm VT
3.3V CML with Built-In Pullup
Zo = 50 Ohm
C1 IN 50 Ohm VT
Zo = 50 Ohm
C2 nIN
50 Ohm REF_AC
Zo = 50 Ohm
C2 nIN
50 Ohm REF_AC Receiver with Built-In 50
R5 100 - 200 Ohm
R5 100 - 200 Ohm
Receiver with Built-In 50
FIGURE 1E. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50
FIGURE 1F. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY A 3.3V CML DRIVER WITH BUILT-IN PULLUP
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RECOMMENDATIONS FOR UNUSED OUTPUT PINS OUTPUTS:
LVDS Output All unused LVDS outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
2.5V LVDS DRIVER TERMINATION
Figure 2 shows a typical termination for LVDS driver in characteristic impedance of 100 differential (50 single)
2.5V LVDS_Driv er + R1 100
transmission line environment. For buffer with multiple LDVS driver, it is recommended to terminate the unused outputs.
2.5V
-
100 Ohm Differential Transmission Line Differential Transmission Line 100
FIGURE 2. TYPICAL LVDS DRIVER TERMINATION
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POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS889832. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS889832 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results.
*
Power_MAX = VDD_MAX * IDD_MAX = 2.625V * 120mA = 315mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow of and a multi-layer board, the appropriate value is 51.5C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.315W * 51.5C/W = 101.2C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA
FOR
16-PIN VFQFN, FORCED CONVECTION
JA vs. 0 Air Flow (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards 51.5C/W
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RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
FOR
16 LEAD VFQFN
JA vs. 0 Air Flow (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards 51.5C/W
TRANSISTOR COUNT
The transistor count for ICS889832 is: 206 Pin compatible with SY89832U
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PACKAGE OUTLINE - K SUFFIX FOR 16 LEAD VFQFN
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A3 b e ND NE D D2 E E2 L 0.25 0.30 0.25 3.0 1.25 0.50 0.18 0.50 BASIC 4 4 3.0 1.25 0.80 0 0.25 Reference 0.30 MINIMUM 16 1.0 0.05 MAXIMUM
Reference Document: JEDEC Publication 95, MO-220
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TABLE 9. ORDERING INFORMATION
Part/Order Number ICS889832AK ICS889832AKT ICS889832AK ICS889832AKT Marking 832A 832A TBD TBD Package 16 Lead VFQFN 16 Lead VFQFN 16 Lead "Lead-Free" VFQFN 16 Lead "Lead-Free" VFQFN Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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Corporate Headquarters
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Asia Pacific and Japan
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Europe
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(c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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