View ICS98UAE877A_4112457.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DATASHEET
1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
ICS98UAE877A
Description
The PLL clock buffer, ICS98UAE877A, is designed for a VDDQ of 1.5V, an AVDD of 1.5V and differential data input and output levels. ICS98UAE877A is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to ten differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock outputs (FB_OUTT, FBOUTC). The clock outputs are controlled by the input clocks (CLK_INT, CLK_INC), the feedback clocks (FB_INT, FB_INC), the LVCMOS program pins (OE, OS) and the Analog Power input (AVDD). When OE is low, the outputs (except FB_OUTT/FB_OUTC) are disabled while the internal PLL continues to maintain its locked-in frequency. OS (Output Select) is a program pin that must be tied to GND or VDDQ. When OS is high, OE will function as described above. When OS is low, OE has no effect on CLKT7/CLKC7 (they are free running in addition to FB_OUTT/FB_OUTC). When AVDD is grounded, the PLL is turned off and bypassed for test purposes. When both clock signals (CLK_INT, CLK_INC) are logic low, the device will enter a low power mode. An input logic detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform a low power state where all outputs, the feedback and the PLL are OFF. When the inputs transition from both being logic low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input clock pair (CLK_INT, CLK_INC) within the specified stabilization time tSTAB. The PLL in ICS98UAE877A clock driver uses the input clocks (CLK_INT, CLK_INC) and the feedback clocks (FB_INT, FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT[0:9], CLKC[0:9]). ICS98UAE877A is also able to track Spread Spectrum Clocking (SSC) for reduced EMI. ICS98UAE877A is available in Commercial Temperature Range (0C to 70C) and Industrial Temperature Range (-40C to +85C). See Ordering Information for details
Features
* * * * * *
Low skew, low jitter PLL clock driver 1 to 10 differential clock distribution Feedback pins for input to output synchronization Spread Spectrum tolerant inputs Auto PD when input signal is at a certain logic state Available in 52-ball VFBGA and a 40-pin MLF
Applications
* DDR2 Memory Modules / Zero Delay Board Fan Out * Provides complete DDR DIMM solution with
IDT74SSTUAE32xxx family
Switching Characteristics
* Period jitter: * Half-period jitter: * Output-Output Skew * Cycle-Cycle Jitter
40ps (DDR2-400/533) 30ps (DDR2-667) 60ps (DDR2-400/533) 50ps (DDR2-667) 40ps (DDR2-400/533) 30ps (DDR2-667) 40ps
1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
1
ICS98UAE877A
7181/2
ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
COMMERCIAL TEMPERATURE GRADE
Block Diagram
LD or OE OE OS AVDD
(1)
POWER DOWN AND LD, OS, or OE TEST MODE PLL BYPASS LOGIC LD
CLKT0 CLKC0 CLKT1 CLKC1 CLKT2 CLKC2 CLKT3 CLKC3 CLKT4 CLKC4
CLK_INT CLK_INC 10K - 100K FBIN_INT FBIN_INC PLL
CLKT5 CLKC5 CLKT6 CLKC6 CLKT7 CLKC7 CLKT8 CLKC8 CLKT9 CLKC9
NOTE: 1. The Logic Detect (LD) powers down the device when a logic LOW is applied to both CLK_INT and CLK_INC.
FBOUTT FBOUTC
1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
2
ICS98UAE877A
7181/2
ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
COMMERCIAL TEMPERATURE GRADE
Pin Configurations
CLKC1 CLKC0 CLKC5 CLKT6 CLKC6 32 CLKT1 CLKT0 CLKT5 VDDQ VDDQ 31
1 A
2
3
4
5
6
40
39
38
37
36
35
34
B C D E F G H J
33
VDDQ CLKC2 CLKT2 CLK_INT CLK_INC VDDQ AGND AVDD VDDQ GND
1 2 3 4 5 6 7 8 9 10
11 12 13 14 15 16 17 18 19 20
30 29 28 27 26 25 24 23 22 21
CLKC7 CLKT7 VDDQ FB_INT FB_INC FBOUTC FBOUTT VDDQ OE OS
CLKT3
CLKT4
CLKT8
VDDQ
CLKC4
CLKC3
CLKC9
K
A B C D E F G H J K
1 CLKT1 CLKC1 CLKC2 CLKT2 CLK_INT CLK_INC AGND AVDD CLKT3 CLKC3
2 CLKT0 GND GND VDDQ VDDQ VDDQ VDDQ GND GND CLKC4
3 CLKC0 GND NB VDDQ NB NB VDDQ NB GND CLKT4
4 CLKC5 GND NB VDDQ NB NB VDDQ NB GND CLKT9
5 CLKT5 GND GND OS VDDQ OE VDDQ GND GND CLKC9
6 CLKT6 CLKC6 CLKC7 CLKT7 FB_INT FB_INC FB_OUTC FB_OUTT CLKT8 CLKC8
40-PIN MLF TOP VIEW
176 BALL BGA TOP VIEW
1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
3
ICS98UAE877A
CLKC8
CLKT9
VDDQ
7181/2
ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
COMMERCIAL TEMPERATURE GRADE
Pin Descriptions
Terminal Name
AGND AVDD CLK_INT CLK_INC FB_INT FB_INC FB_OUTT FB_OUTC OE OS GND VDDQ CLKT[0:9] CLKC[0:9] NB Analog Ground Analog Power Clock Input with a 10K-100K pulldown resistor Complementary Clock Input with a 10K-100K pulldown resistor Feedback Clock Input Complementary Feedback clock input Feedback Clock Output Complementary Feedback clock Output Output Enable (Asynchronous) Output Select (tied to GND or VDDQ) Ground Logic and Output Power Clock Outputs Complementary Clock Outputs No Ball
Description
Electrical Characteristics
Ground 1.5V Nominal Differential Input Differential Input Differential Input Differential Input Differential Output Differential Output LVCMOS Input LVCMOS Input Ground 1.5V Nominal Differential Outputs Differential Outputs
1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
4
ICS98UAE877A
7181/2
ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
COMMERCIAL TEMPERATURE GRADE
Function Table
Inputs AVDD
GND GND GND GND 1.5V (nom) 1.5V (nom) 1.5V (nom) 1.5V (nom) 1.5V (nom) 1.5V (nom) 1
Outputs CLK_ INT
L H L H L H L H L H
OE
H H L L L L H H X X
OS
X X H L H L X X X X
CLK_ INC
H L H L H L H L L H
CLKT
L H L(Z)1 L(Z), CLKT7 active1 L(Z)1 L(Z), CLKT7 active1 L H L(Z)
1
CLKC
H L L(Z)1 L(Z), CLKC7 active1 L(Z)1 L(Z), CLKC7 active1 H L L(Z)
1
FB_ OUTT
L H
FB_ OUTC
H L
PLL
Bypassed/Off Bypassed/Off Bypassed/Off
H L H L H L(Z)
1
L H L H L L(Z)
1
Bypassed/Off On On On On Off
Reserved
Outputs are disabled to a LOW state meeting the IODL limit.
Absolute Maximum Ratings
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Item
Supply Voltage, (AVDD and VDDQ) Logic Inputs Ambient Operating Temperature Storage Temperature -0.5V to 2.5V
Rating
GND - 0.5V to VDDQ + 0.5V -40C to +85C -65 to +150C
1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
5
ICS98UAE877A
7181/2
ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
COMMERCIAL TEMPERATURE GRADE
DC Electrical Characteristics Over Operating Range
Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0C to +70C, Industrial: TA = -40C to +85C; Supply Voltage AVDD/VDDQ = 1.5V 0.075V. Symbol VOH VOL VIK IIH IIL IODL IDD1.5 IDDLD CIN1 COUT 1
1
Parameter
Output HIGH Voltage Output LOW Voltage Input Clamp Voltage Input HIGH Current Input LOW Current Output Disabled LOW Current Operating Supply Current Input Capacitance Output Capacitance
Test Conditions
IOH = -100A IOH = -6mA IOL = 100A IOL = 6mA IIN = -18mA CLK_INT, CLK_INC; VI = VDD or GND OS, FB_INT, FB_INC; VI = VDD or GND OE = L, VODL = 100mV CL = 0pF @ 410MHz CL = 0pF VI = VDDQ or GND VOUT = VDDQ or GND
Min.
VDDQ - 2 1.1
Typ.
1.45 0.25
Max.
Units
V
0.1 0.6 -1.2
V V A A A
250 10
100 300 500 2 2 3 3
mA A pF
Guaranteed by design, not 100% tested in production.
1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
6
ICS98UAE877A
7181/2
ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
COMMERCIAL TEMPERATURE GRADE
Recommended Operating Conditions
Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0C to +70C, Industrial: TA = -40C to +85C; Supply Voltage AVDD/VDDQ = 1.5V 0.075V. Symbol AVDD, VDDQ VIL
Parameter1
Supply Voltage LOW - Level Input Voltage HIGH -Level Input Voltage DC Input Signal Voltage2
Conditions
Min.
1.425
Typ.
1.5
Max.
1.575
Units
V
CLK_INT, CLK_INC, FB_INT, FB_INC OE, OS CLK_INT, CLK_INC, FB_INT, FB_INC OE, OS -0.3 DC - CLK_INT, CLK_INC, FB_INT, FB_INC AC - CLK_INT, CLK_INC, FB_INT, FB_INC 0.35 0.65 x VDDQ
0.35 x VDDQ
V
VIH
V
VIN
VDDQ + 0.3
V
VID
Differential Input Signal Voltage3
VDDQ + 0.4 0.6 VDDQ/2 - 0.1 VDDQ/2 0.15 VDDQ/2 VDDQ/2 +0.1 VDDQ/2 + 0.15 -6
V
VOX VIX IOH IOL TA
Output Differential Cross-Voltage4 Input Differential Cross-Voltage4 HIGH-Level Output Current LOW-Level Output Current Operating Free-Air Temperature
V
mA 6 -40 +85 C
1 Unused inputs must be held HIGH or LOW to prevent them from floating. 2 DC input signal voltage specifies the allowable DC execution of differential input. 3 Differential inputs signal voltages specifies the differential voltage [VTR-VCP] required for switching, where VTR is the true input level and VCP is the complementary input level. 4 Differential cross-point voltage is expected to track variations of VDDQ and is the voltage at which the differential signal must be crossing.
1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
7
ICS98UAE877A
7181/2
ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
COMMERCIAL TEMPERATURE GRADE
Timing Requirements Over Recommended Operating Free-Air Temperature Range
Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0C to +70C, Industrial: TA = -40C to +85C; Supply Voltage AVDD/VDDQ = 1.5V 0.075V.
Symbol
freqOP freqAPP dTIN TSTAB
Parameter1
Max Clock Frequency
2 3
Conditions
1.5V 0.075V @ 25C 1.5V 0.075V @ 25C
Min.
95 160 40
Max.
410 410 60 9
Units
MHz MHz % s
Application Frequency Range Input Clock Duty Cycle CLK Stabilization
4
1 The PLL must be able to handle spread spectrum induced skew. 2 Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters. (Used for low speed system debug.) 3 Application clock frequency indicates a range over which the PLL must meet all timing parameters. 4 Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal, within the value specificied by the Static Phase Offset (t), after power-up. During normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal when CLK and CLK go to a logic low state, enter the power-down mode and later return to active operation. CLK and CLK may be left floating after they have been driven low for one complete clock cycle.
1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
8
ICS98UAE877A
7181/2
ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
COMMERCIAL TEMPERATURE GRADE
Switching Characteristics Over Recommended Free Air Operating Range
Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0C to +70C, Industrial: TA = -40C to +85C; Supply Voltage AVDD/VDDQ = 1.5V 0.075V
Symbol
tEN tDIS tJIT(PER)
Parameter1
Output Enable Time Output Disable Time Period Jitter
Conditions
OE to any output OE to any output
(MHz)
160 - 410 160 - 270 271 - 410 160 - 270 271 - 410
Min.
Typ.
4.73 5.82
Max.
8 8 40 30 60 50
Units
ns ns ps ps
-40 -30 -60 -50 1 0.5 2.5
tJIT(HPER) Half-Period Jitter Input Clock
SLr1(i)
4 v/ns 2 40 -40 50 20 v/ns ps ps ps ps ps ps KHz % MHz
Input Slew Rate Output Clock Slew Rate Cycle-to-Cycle Period Jitter Dynamic Phase Offset Static Phase Offset tJIT(PER) + t()DYN + tSKEW(O) t()DYN + tSKEW(O) Output-to-Output Skew SSC Modulation Frequency SSC Clock Input Frequency Deviation PLL Loop Bandwidth (-3dB from unity gain)
Output Enable (OE, OS) 160 - 410
SLr1(o)
0.8 0 0
tJIT(CC+) tJIT(CC-) t()DYN tSPO2
160 - 270 271 - 410 271 - 410
-50 -20 -60 0
60 80 60
(su) t(h)
tSKEW
160 - 270 271 - 410 30 0 2
60 30 33 -0.5
1 2
Guaranteed for application frequency range. Static phase offset shifted by design.
1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
9
ICS98UAE877A
7181/2
ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
COMMERCIAL TEMPERATURE GRADE
Parameter Measurement Information
VDD ICS98UAE877A V(CLK)
V(CLK)
GND
Figure 1: IBIS Model Output Load
VDD/2 C = 10pF GND SCOPE
ICS98UAE877A
Z = 60 L = 2.97" Z = 120 Z = 60 L = 2.97" C = 10pF
R = 10
Z = 50 R = 1M C = 1pF
R = 10
Z = 50
VTT R = 1M C = 1pF VTT Note: VTT = GND
GND VDD/2
Figure 2: Output Load Test Circuit
Yx, FB_OUTC
Yx, FB_OUTT tC(N) tJIT(CC) = tC(N) + tC(N + 1) tC(N + 1)
Figure 3: Cycle-to-Cycle Jitter
1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
10
ICS98UAE877A
7181/2
ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
COMMERCIAL TEMPERATURE GRADE
CLK_INC
CLK_INT
CLK_INC
CLK_INT t()n n=N t() = 1 N Figure 4: Static Phase Offset t()n t()n+1
Yx
Yx
Yx, FB_OUTC
Yx, FB_OUTT tSKEW
Figure 5: Output Skew
Yx, FB_OUTC
Yx, FB_OUTT tC(n) Yx, FB_OUTC
Yx, FB_OUTT 1 fo
t(JIT_PER) = tC(n) -
1 fo
Figure 6: Period Jitter
1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
11
ICS98UAE877A
7181/2
ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
COMMERCIAL TEMPERATURE GRADE
Yx, FB_OUTC
Yx, FB_OUTT tJIT(HPER_n) tJIT(HPER_n+1)
1 fo
tJIT(HPER) = tJIT(HPER_n) -
1 2xfo
Figure 7: Half-Period Jitter
80%
80% VID VOD
20% Clock Inputs and outputs tSLR
20% tSLF
Figure 8: Input and Output Slew Rates
1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
12
ICS98UAE877A
7181/2
ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
COMMERCIAL TEMPERATURE GRADE
CLK
CLK
FB_IN
FB_IN t() SSC OFF SSC ON t()dyn SSC OFF SSC ON t()dyn t()dyn t()
t()dyn
Figure 9: Dynamic Phase Offset
50% VDDQ OE Y 50% VDDQ Y, Y Y
tEN
OE 50% VDDQ
tDIS Y 50% VDDQ Y
Figure 10: Time Delay Between OE and Clock Output (Y, Y)
1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
13
ICS98UAE877A
7181/2
ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
COMMERCIAL TEMPERATURE GRADE
VIA CARD
1
BEAD 0603
AVDD 4.7uF 1206 0.1uF 0603
VDDQ
2200pF 0603 AGND PLL
GND
VIA CARD
Figure 11. AVDD Filtering
*Place the 2200pF capacitors close to the PLL. *Use wide traces for PLL Analog power and GND. Connect PLL and caps to AGND trace and connect trace to one GND via (farthest from PLL). *Recommended bead: Fair-rite P/N 2506036017Y0 or equivalent (0.8 DC max., 600 at 100MHz).
1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
14
ICS98UAE877A
7181/2
ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
COMMERCIAL TEMPERATURE GRADE
Package Outline and Package Dimensions - BGA
Package dimensions are kept current with JEDEC Publication No. 95
C SEATING PLANE A1 T b REF 4 3 2 1 A B C D Alpha Designations for Vertical Grid (Letters I, O, Q, and S not used) d TYP D1 Numeric Designations for Horizontal Grid
D
-e- TYP
TOP VIEW E h TYP 0.12 C E1
c REF
-e- TYP
ALL DIMENSIONS IN MILLIMETERS D 7.00 Bsc BALL GRID d T Min/Max e E Horiz Vert Total Min/Max 0.25/0.45 4.50 Bsc 0.86/1.00 0.65 Bsc 6 10 60 h Min/Max 0.15/0.31 D1 5.85 Bsc REF. DIMS E1 b c 3.25 Bsc 0.575 0.625 **
NOTE: Ball grid total indicates maximum ball count for package. Lesser quantity may be used. * Source Ref.: JEDEC Publication 95, MO-205*, MO-255** 10-0055
1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
15
ICS98UAE877A
7181/2
ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
COMMERCIAL TEMPERATURE GRADE
Package Outline and Package Dimensions - MLF
Package dimensions are kept current with JEDEC Publication No. 95
Seating Plane (Ref.) ND & NE Even
Index Area N
A1 A3 L
(ND - 1) x e (Ref.)
e/2 1 2 or Anvil Singulation 1 2 Sawn Singulation Top View E2 E2/2
(Typ.) If ND & NE are Even
E
(NE - 1) x e (Ref.)
b A C 0.08 C (Ref.) ND & NE Odd e D2/2 D2 Thermal Base
D
Thermally Enhanced, Very Thin, Fine Pitch Quad Flat / No Lead Plastic Package
Symbol
A A1 A3 b e N Nd Ne D x E BASIC D2 E2 L 2.75 2.75 0.30 0.18 0.50 BASIC 40 10 10 6.00 x 6.00 3.05 3.05 0.5
Min.
0.80 0 0.25 Reference
Max.
1.00 0.05 0.30
1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
16
ICS98UAE877A
7181/2
ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
COMMERCIAL TEMPERATURE GRADE
Ordering Information
ICSS98UAE XX XXX Device Type Package X X Shipping Shipping Carrier Carrier T Blank I HLF KLF 877A Tape and Reel 0C to +70C (Commercial) -40C to +85C (Industrial) Low Profile, Fine Pitch, Ball Grid Array - Lead-Free Very Thin, Fine Pitch Quad Flat Package - Lead-Free 1.5V Low-Power Wide-Range Frequency Clock Driver
1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
17
ICS98UAE877A
7181/2
ICS98UAE877A 1.5V LOW-POWER WIDE-RANGE FREQUENCY CLOCK DRIVER
COMMERCIAL TEMPERATURE GRADE
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015 408-284-8200 Fax: 408-284-2775
Corporate Headquarters
Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.)
Asia Pacific and Japan
Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505
Europe
IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339
(c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

▲Up To Search▲

Price & Availability of ICS98UAE877A

	To Download ICS98UAE877A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .