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| Low Charge Injection 8-Channel High Voltage Analog Switch Ordering Information Package Options Operating VPP 40V to 80V 80V to 150V VPP - VNN 160V 160V 28-lead plastic chip carrier HV21716PJ HV21816PJ Die HV21716X HV21816X LETE - OBSO - HV21716 HV21816 Features HVCMOS(R) technology for high performance Low charge injection Very low quiescent power dissipation - 10A Output On-resistance typically 22 ohms Low parasitic capacitances DC to 10MHz analog signal frequency -50dB typical output off isolation at 5MHz CMOS logic circuitry for low power Excellent noise immunity On-chip shift register and latch logic circuitry Flexible high voltage supplies Surface mount package available General Description Not recommended for new designs. Please use HV20220 for all new designs. This device is a low charge injection 8-channel high-voltage analog switch integrated circuit (IC) intended for use in applications requiring high voltage switching controlled by low voltage control signals, such as ultrasound imaging and printers. Input data is shifted into an 8-bit shift register which can then be retained in an 8-bit latch. To reduce any possible clock feedthrough noise, Latch Enable (LE) should be left high until all bits are clocked in. Using HVCMOS technology, this switch combines high voltage bilateral DMOS switches and low power CMOS logic to provide efficient control of high voltage analog signals. Absolute Maximum Ratings* VDD logic power supply voltage VPP - VNN supply voltage VPP positive high voltage supply VNN negative high voltage supply Logic input voltages Analog signal range Peak analog signal current/channel Storage temperature Power dissipation -0.5V to +18V 174V -0.5V to +160V +0.5V to -160V -0.5V to VDD +0.3V VNN to VPP 3.0A -65C to +150C 1.2W * Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. 13-66 HV21716/HV21816 Electrical Characteristics (over operating conditions, VPP = +80V, VNN = -80V, and VDD= 15V unless otherwise noted) DC Characteristics Characteristics Small Signal Switch (ON) Resistance Small Signal Switch (ON) Resistance Matching Large Signal Switch (ON) Resistance Switch Off Leakage Per Switch DC Offset Switch Off DC Offset Switch On Pos. HV Supply Current Neg. HV Supply Current Pos. HV Supply Current Neg. HV Supply Current Switch Output Peak Current Output Switch Frequency IPP Supply Current INN Supply Current Logic Supply Average Current Logic Supply Quiescent Current Data Out Source Current Data Out Sink Current fSW IPP INN IDD IDDQ ISOR ISINK 0.45 0.45 4.0 4.0 6.0 10 0.45 0.45 0.70 0.70 3.5 3.5 4.0 IPPQ INNQ IPPQ INNQ 3.0 Sym RONS RONS RONS RONL ISOL 5.0 300 500 0C min max 24 18 20 min +25C typ 22 18 5.0 13 1.0 100 100 10 -10 10 -10 3.0 max 25 20 20 22 10 300 500 50 -50 50 -50 2.0 50 5.0 5.0 6.0 10 0.40 0.40 5.5 5.5 6.0 10 2.0 15 300 500 +70C min max 28 23 20 Units ohms ohms % ohms A mV mV A A A A A KHz mA mA mA A mA mA VOUT = VDD - 0.7V VOUT = 0.7V ALL SWS OFF ALL SWS ON ISW = 5mA VSIG 0.1% Duty Cycle Duty Cycle = 50% HV output switching frequency = 50KHz fCLK = 3MHz Test Conditions ISIG = 5mA ISIG = 200mA ISW = 5mA VSIG = VPP -10V, ISIG = 1.0A VSIG = VPP -10V and VNN +10V RL = 100K RL = 100K LETE - OBSO - 13 13 13-67 HV21716/HV21816 AC Characteristics Characteristics Time to Turn Off VSIG* Set Up Time Before LE Rises Time Width of LE Clock Delay Time to Data Out Turn On Time Turn Off Time Off Isolation Sym min tSIG (OFF) tSD tWLE tDO tON tOFF KO -30 -45 Clock Freq Set Up Time Data to Clock Hold Time Data from Clock Switch Crosstalk Off Capacitance SW to GND On Capacitance SW to GND Output Voltage Spike fCLK tSU tH KCR CSG(OFF) CSG(ON) +VSPK -VSPK * Time required for analog signal to turn off before output switch turns off (critical timing). 0C max min 0 150 150 175 3.0 5.0 -30 -45 5.0 15 35 -60 5.0 25 17 50 15 35 -60 5.0 25 150 150 +25C typ max min +70C max Units ns Test Conditions 150 150 175 3.0 5.0 -33 -50 5.0 8.0 -70 12 38 150 150 17 50 20 35 -60 5.0 25 17 50 -30 -45 5.0 190 3.0 5.0 ns ns ns s s dB dB MHz ns ns dB pF pF mV f = 5MHz, 50 load 0V, 1MHz 0V, 1MHz VPP = +80V, VNN = -80V, RL = 50 RL = 10K RL = 10K f = 5MHz, 1K// 15pF load f = 5MHz, 50 load 50% duty cycle fDATA = fCLK/2 Operating Conditions* Symbol VPP1, 3 VNN1, 3 VDD1, 3 VIH VIL VSIG2 TA ETE - OBSOL - Device HV21716 X X X X X X X X X X X X X X HV21816 Value 40V to 80V 80V to 150V -10V to VPP -160V 10V to 15.5V VDD -2.0V to VDD 0V to 2.0V VNN +10V to VPP -10 0C to 70C Notes: 1. Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last. 2. VSIG must be VNN VSIG VPP or floating during power up/down transistion. 3. Rise and fall times of power supplies, VDD, VPP, and VNN should not be less than 1.0msec. 13-68 HV21716/HV21816 Test Circuits VPP -10 ISOL VPP -10V VIN = 10 VP-P @5MHz 50 NC RL VOUT 10K VNN +10 50 +80V -80V VPP VNN VDD GND 15V +80V -80V VPP VNN VDD GND 15V +80V -80V VPP VNN VDD GND 15V KCR = 20Log VOUT VIN Switch OFF Leakage Crosstalk TON /TOFF VIN = 10 VP-P @5MHz VOUT +VSPK VOUT -VSPK 50 VOUT RL 100K RL 1K RL +80V -80V VPP VNN VDD GND 15V +80V -80V VPP VNN VDD GND 15V +80V -80V VPP VNN VDD GND 15V KO = 20Log VOUT VIN LETE - Logic Timing Waveforms OBSO - DN-1 DN DN+1 DATA IN 50% 50% LE 50% 50% t WLE t SD 50% t SU th t DO DATA OUT 50% t OFF V OUT (TYP) OFF ON 90% 10% t ON 50% OFF Isolation DC Offset ON/OFF Output Voltage Spike 13 13 CLOCK 13-69 HV21716/HV21816 Logic Diagram LATCHES DIN D LE D LE D LE D LE 8 BIT SHIFT REGISTER D LE D LE D LE D LE LEVEL SHIFTERS OUTPUT SWITCHES SW0 CLK SW1 SW2 SW3 SW4 SW5 DOUT SW6 SW7 VNN VPP VDD Truth Table D0 L H L H L H L H L H L H L H D1 D2 D3 D4 D5 D6 LETE - OBSO - LE D7 LE SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 L L L L L L L L L L L L L L OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON HOLD PREVIOUS STATE Notes: 1. The eight switches operate independently. 2. Serial data is clocked in on the L H transition CLK. 3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flows through the latch. 4. DOUT is high when switch 7 is on. 5. Shift register clockng has no effect on the switch states if LE is H. L H X X X X X X X X L L H 13-70 Typical Performance Curves 40 35 RON vs. Ambient Temp TA VDD = 15V & VPP/VNN = 80V LETE - - OBSO 50 RON vs. VPP/VNN VDD = 15V RON (ohms) @ 5mA HV21716/HV21816 30 RON (ohms) 40 25 ISW = 5mA 20 15 10 5 0 -55 -25 30 TA = 125C TA = 85C 20 TA = 25C TA = 0C TA = -45C 0 25 50 75 100 125 150 Ambient Temp TA (C) 10 VPP 0 20 40 60 80 100 120 140 160 VNN -160 -140 -120 -100 -80 -60 -40 -20 0 IPP/INN vs. Output Switching Frequency VDD = 15V & VPP/VNN = 80V 400 300 200 ISWITCH (mA) Switch Current vs. Switch Voltage Drop VDD = 15V & VPP/VNN = 80V TA = 0C TA = 25C IPP/INN Average Current (mA) 40 TA = 125C 30 TA = 70C TA = 25C 20 TA = -55C 10 100 0 -100 -200 -300 -400 0 -4 -3 -2 -1 0 1 VSWITCH (volts) 2 3 4 TA = 70C 0 0 100 200 300 HV Output Switching Freq (KHz) TDO vs. Ambient Temp TA VPP/VNN = 80V 400 13 200 175 Junction Temp Tj (C) Junction Temp Tj vs. Switch Peak Current VSIG Freq = 10KHz & Duty Cycle = 0.1% VDD = 15V & VPP/VNN = 80V 13 275 250 150 125 100 75 50 25 0 0 TA = 75C 225 VDD = 10V 200 TDO (ns) 175 150 125 100 75 VDD = 15V TA = 25C 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Switch Peak Current (A) 13-71 -50 -25 0 25 50 75 Ambient Temp TA (C) 100 125 HV21716/HV21816 Typical Performance Curves 40 36 32 VDD = 10V TWLE (ns) TWLE vs. Ambient Temp VPP/VNN = 80V LETE - OBSO - 110 100 90 TSD (ns) TSD vs. Ambient Temp VPP/VNN = 80V 28 24 20 16 12 8 -50 -25 0 25 50 75 100 125 Ambient Temp TA (C) TH vs. Ambient Temp VPP/VNN = 80V VDD = 15V 80 70 60 50 40 30 VDD = 10V VDD = 15V -50 -25 0 25 50 75 100 125 Ambient Temp TA (C) TSU vs. Ambient Temp VPP/VNN = 80V 18 17 16 16 14 12 TSU (ns) VDD = 10V 15 TH (ns) VDD = 10V 10 8 VDD = 15V 6 14 13 12 11 10 -50 -25 0 25 50 75 100 125 Ambient Temp TA (C) TON vs. Ambient Temp VPP/VNN = 80V VDD = 15V 4 2 0 -50 -25 0 25 50 75 100 125 Ambient Temp TA (C) TOFF vs. Ambient Temp VPP/VNN = 80V 800 700 600 TON (ns) 2.5 VDD = 10V 2.0 TOFF (ns) VDD = 10V 500 400 300 200 100 0 -50 -25 0 25 50 75 100 125 Ambient Temp TA (C) VDD = 15V VDD = 15V 1.5 1 0 -50 -25 0 25 50 75 100 125 Ambient Temp TA (C) 13-72 HV21716/HV21816 Typical Performance Curves I DD vs CLK Frequency VDD = 15V, VPP/VNN = 80V, TA = 0C to 70C 6 -120 -100 -80 -60 -40 -20 Off Isolation vs Signal Voltage Frequency VDD = 15V, VPP/VNN = 80V I DD Current (mA) 4 3 2 1 Off Isolation (db) 5 10K 100K 1M 10M 10K 100K 1M 10M CLK Frequency (Hz) Signal Voltage Frequency (Hz) Crosstalk vs Analog Signal Frequency VDD = 15V, VPP/VNN = 80V -100 -90 Crosstalk (db) -80 70 C -70 0 C -60 -50 100K 1M 10M 100M LETE - OBSO - 13 Analog Signal Frequency (Hz) 13 13-73 HV21716/HV21816 Pin Configurations 28-Pin J-Lead Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Function SW3 SW3 SW2 SW2 N/C N/C SW1 SW1 SW0 SW0 VPP VNN GND VDD Pin 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Function N/C DIN CLK LE DOUT SW7 SW7 SW6 SW6 N/C SW5 SW5 SW4 SW4 Package Outlines 25 26 27 24 23 22 21 20 19 18 17 16 15 14 13 12 28 1 2 3 4 5 6 7 8 9 10 11 top view 28-pin J-Lead Package LETE - OBSO - 13-74 HV2216 8-Channel High Voltage Analog Switch Ordering Information Package Options VPP - VNN 160V 28-pin plastic DIP HV2216P 28-lead plastic chip carrier HV2216PJ Die HV2216X Features HVCMOS technology for high performance Very low quiescent power dissipation - 10A Output On-resistance typically 22 ohms Low parasitic capacitances DC to 10MHz analog signal frequency -50dB typical output off isolation at 5MHz CMOS logic circuitry for low power Excellent noise immunity On-chip shift register, latch and clear logic circuitry Flexible high voltage supplies Surface mount package available (R) General Description Not recommended for new designs. Please use HV20220 for all new designs. This device is an 8-channel high-voltage analog switch integrated circuit (IC) intended for use in applications requiring high voltage switching controlled by low voltage control signals, such as ultrasound imaging and printers. Input data is shifted into an 8-bit shift register which can then be retained in an 8-bit latch. To reduce any possible clock feedthrough noise, Latch Enable (LE) should be left high until all bits are clocked in. Using HVCMOS technology, this switch combines high voltage bilateral DMOS switches and low power CMOS logic to provide efficient control of high voltage analog signals. This IC is suitable for various combinations of high voltage supplies, e.g., for HV2216 +40V/-120V, or +80V/-80V or +150V/ -10V. 13 13 Absolute Maximum Ratings* VDD Logic power supply voltage VPP - VNN Supply voltage VPP Positive high voltage supply VNN Negative high voltage supply Logic input voltages Analog Signal Range Peak analog signal current/channel Storage temperature Power dissipation -0.5V to +18V 174V -0.5V to +160V +0.5V to -160V -0.5V to VDD +0.3V VNN to VPP 3.0A -65C to +150C 1.2W * Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. 13-75 |
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