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| ZILOG PRELIMINARY Z89390 CPS DC-9030-01 PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION Z89390 16-BIT DIGITAL SIGNAL PROCESSOR GENERAL DESCRIPTION The Z89390 is a CMOS Digital Signal Processor (DSP). Single-cycle instruction execution and a Harvard bus structure promotes efficient algorithm execution. The processor contains 512 word data RAM and 64K word of external program address space is accessible. Six register pointers provide circular buffering capabilities and dual operand fetching. Three vectored interrupts are complemented by a six level stack. The CODEC interface enables high-speed transfer rates to accommodate digital audio and voice data. A dedicated Counter/Timer provides the necessary timing signals for the CODEC interface. An additional 13-bit timer is available for general-purpose use. The Z89390 is optimized to accommodate intricate signal processing algorithms. The 20-MIP operating performance and efficient architecture provides real-time execution. Compression, filtering, frequency detection, audio, voice detection/synthesis and other available algorithms can all be accommodated. The on-board peripherals provide additional cost advantages. Development tools for the IBM PC include a relocatable assembler, a linker loader debugger. Notes: All Signals with a preceding front slash, "/", are active Low, e.g., B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Power Ground Circuit VCC GND Device VDD VSS DC 9030-00 1 ZILOG PRELIMINARY Z89390 CPS DC-9030-01 GENERAL DESCRIPTION (Continued) External Program ROM PD15-PD0 PA15-PA0 16 PD PA 16 16 Register Pointer 0-2 256 Word RAM 0 256 Word RAM 1 Register Pointer 4-6 PC Instruction Register 16 16 EXT0-15 16-Bit Bus Switch S-Bus X 16 x16 Multiplier EXT5-1 EXT5-2 24-bit P 24 24-Bit Bus P Bus EXT6-1 EXT6-2 EXT7-1 EXT7-2 CODEC Interface RXD TXD SCLK FS0 FS1 Y Switch Stack Ready D Bus 16-bit I/O Port 3 EA0-2 WAIT, RD/WR, /OS MUX Shifter Status (5) EXT4 13-Bit Timer 3 B ALU A Interrupt /INTO-2 /RESET ACC User Port Note: EXT5, EXT6, and INTERRUPT1 are used for the CODEC Interface. EXT4 and INTERRUPT2 are used for the 13-bit timer. 2 2 UI0-1 UO0-1 Z89391 Functional Block Diagram 2 DC 9030-00 ZILOG PRELIMINARY Z89390 CPS DC-9030-01 PIN DESCRIPTION EXT14 EXT15 EXT13 EXT12 EXT2 EXT1 EXT0 RXD VSS VSS VSS PA3 PA6 PA5 PA2 PA1 VCC PA0 11 VSS EXT3 PA8 EXT4 PA9 VSSP EXT5 PA10 EXT6 PA11 EXT7 TXD PA12 EXT8 PA13 EXT9 VSS PA14 EXT10 PA15 VCC PA7 PA4 N/C 1 84 12 75 74 VSS PD15 FS1 PD14 UO1 PD13 UO0 PD12 INT0 FS0 Z89390 84-Pin PLCC HALT PD11 CLK /D5 PD10 VDDP PD9 EA2 PD8 EA1 32 33 VSS PD0 EXT11 PD1 PD2 PD3 INT2 INT1 UI1 42 43 VDD RD//WR SCLK PD4 PD5 /RESET PD6 EA0 PD7 UI0 WAIT 54 53 VCC VDD 84-Pin PLCC Pin Assignments DC 9030-00 3 ZILOG PRELIMINARY Z89390 CPS DC-9030-01 ABSOLUTE MAXIMUM RATINGS Symbol VCC TSTG TA Description Supply Voltage (*) Storage Temp Oper Ambient Temp Min. -0.3 -65 Max. +7.0 +150 Units V C C Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended period may affect device reliability. Notes: * Voltage on all pins with respect to GND. See Ordering Information. STANDARD TEST CONDITIONS +5V The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to ground. Positive current flows into the referenced pin (Test Load). From Output Under T est 2.1 K 30 pF 9.1 K . Test Load Diagram DC ELECTRICAL CHARACTERISTICS (VDD= 5V 10%, TA = 0C to +70C unless otherwise specified) Symbol IDD IDC VIH VIL IL VOH VOL IFL Parameter Supply Current DC Power Consumption Input High Level Input Low Level Input Leakage Output High Voltage Output Low Voltage Output Floating Leakage Current IOH = -100 A IOL = 2.0 mA Condition VDD = 5.25V fclock = 20 MHz VDD = 5.25V 2.5 0.8 10 VDD- 0.2 0.5 5 Min. Max. 80 Typical 70 5 Units mA mA V V A V V A 4 DC 9030-00 ZILOG PRELIMINARY Z89390 CPS DC-9030-01 AC ELECTRICAL CHARACTERISTICS (VDD = 5V 10%, TA = 0C to +70C unless otherwise specified) Symbol Clock TCY Tr Tf CPW I/O DSSET DSHOLD EASET EAHOLD RDSET RDHOLD WRSET WRHOLD Interrupt INTSET INTWIDTH Codec Interface SSET FSSET TXSET RXSET RXHOLD Reset RRISE RSET RWIDTH /DS Setup Time from CLOCK Fall /DS Hold Time from CLOCK Rise EA Setup Time to /DS Fall EA Hold Time from /DS Rise Data Read Setup Time to /DS Rise Data Read Hold Time from /DS Rise Data Write Setup Time to /DS Rise Data Write Hold Time from /DS Rise Interrupt Setup Time to CLOCK Fall Interrupt Low Pulse Width SCLK Setup Time from Clock Rise FSYNC Setup Time from SCLK Rise TXD Setup Time from SCLK Rise RXD Setup Time to SCLK Fall RXD Hold Time from SCLK Fall 0 4 12 4 14 6 5 7 1 TCY 15 6 7 7 0 15 15 Parameter Clock Cycle Time Clock Rise Time Clock Fall Time Clock Pulse Width Min (ns) 50 2 2 23 Max (ns) 18 Reset Rise Time Reset Setup Time to CLOCK Rise Interrupt Low Pulse Width 1000 15 2 TCY External Program Memory PASET PA Setup Time from CLOCK Rise PDSET PD Setup Time to CLOCK Rise PDHOLD PD Hold Time from CLOCK Rise Wait State WSET WHOLD Halt HSET HHOLD Halt Setup Time to CLOCK Rise Halt Hold Time from CLOCK Rise 5 10 10 WAIT Setup Time to CLOCK Rise WAIT Hold Time from CLOCK Rise 23 1 3 10 DC 9030-00 5 ZILOG PRELIMINARY Z89390 CPS DC-9030-01 AC TIMING DIAGRAM TCY Tr Tf CLOCK DSHOLD DSSET CPW /DS EASET EAHOLD EA(2:0) Valid Address Out RD//WR RDHOLD RDSET EXT(15:0) Data In Read Timing Diagram TCY CLOCK WHOLD WSET WAIT /DS EA(2:0) Valid Address Out RD//WR EXT(15:0) Data In Read Timing Diagram Using WAIT Pin 6 DC 9030-00 ZILOG TCY PRELIMINARY Z89390 CPS DC-9030-01 CLOCK DSHOLD DSSET /DS EASET EAHOLD EA(2:0) Valid Address Out EASET EAHOLD RD//WR WRHOLD WRSET EXT(15:0) Data In Write Timing Diagram TCY CLOCK WHOLD WSET WAIT /DS EA(2:0) Valid Address Out RD//WR EXT(15:0) Data In Write Timing Diagram Using WAIT Pin DC 9030-00 7 ZILOG PRELIMINARY Z89390 CPS DC-9030-01 AC TIMING (Continued) TCY CLOCK SSET SCLK FSSET FSSET FS0, FS1 TXSET TXD 1 0 RXHOLD RXSET 1 0 1 RXD 1 0 1 0 1 Codec Interface Timing Diagram 8 DC 9030-00 ZILOG PRELIMINARY Z89390 CPS DC-9030-01 AC TIMING (Continued) TCY CLOCK INTSET INT 0,1,2 INTWidth PROGRAM ADDRESS Fetch N -1 Fetch N Fetch N +1 Fetch Int_Addr Fetch I Fetch I +1 EXECUTE Execute N -1 Execute N CALL Int Routine Execute Int Routine Interrupt Timing Diagram TCY CLOCK HHOLD HSET HALT HALT Timing Diagram DC 9030-00 9 ZILOG PRELIMINARY Z89390 CPS DC-9030-01 AC TIMING (Continued) TCY CLOCK RSET /RESET RWIDTH INTERNAL RESET RRISE EXECUTE Cycle 0 Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Code Execution RD/WR /DS UO0-1 EA0-2 EXT0-15 Tri-Stated PA0-15 Tri-Stated Access Reset Vector RAM/ REGISTERS Intact* * The RAM and hardware registers are left intact during a warm reset. A cold reset will produce random data in these locations. The status register is set to zeroes in both cases. RESET Timing Diagram TCY CLOCK PASET PROGRAM ADDRESS Valid Valid Valid PDSET PDHOLD PROGRAM DATA Valid Valid Valid External Memory Port Timing Diagram 10 DC 9030-00 ZILOG PRELIMINARY Z89390 CPS DC-9030-01 (c) 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. Zilog's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 FAX 408 370-8056 Internet: http://www.zilog.com DC 9030-00 11 |
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