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[AK7780]
AK7780
24bit 5ch ADC & SRC + Audio DSP
GENERAL DESCRIPTION The AK7780 is a highly integrated audio processor, including a 28-bit floating point DSP, two 24-bit stereo ADC's and one mono ADC. The stereo ADC's feature high performance, achieving 96dB dynamic range, they include 8:1 input selectors. The ADC supports sampling frequencies from 7.35 kHz to 96 kHz. The AK7780 also includes a stereo sample rate converter (SRC), so it can be used as a master device when it receives digital audio inputs. The DSP includes 168kbits of SRAM for audio delay data that is suitable for creating simulated surround fields. The programmable DSP block is realized with 2560step/fs DSP. It supports sampling frequencies from 7.35kHz to 96 kHz. The AK7780 is used to implement complete sound field control, such as echo, 3D, parametric equalization, and other sound enhancements. It is packaged in a 100-lead LQFP package. FEATURES [DSP] Main Word length: 28-bit (Data RAM F24.4 limited range floating point) Instruction cycle time: 8.1 ns (2560step/fs fs=48kHz; 1280step/fs fs=96kHz) Multiplier: 24 x 16 40-bit (Double precision available) Divider: 24 / 24 24-bit ALU: 44-bit arithmetic operation (overflow margin: 4-bits) F24.4 arithmetic and logic operation Shift+Register: Flexible setting Program RAM: 2048 x 36-bit Coefficient RAM: 2048 x 16-bit Data RAM: 2048 x 28-bit (F24.4[sign bit + 23-bit mantissa + 4-bit exponent]) Offset RAM: 64 x 13-bit Internal Delay RAM: 168kbits ( 6144 x 28 bit / 2048 x 28 bit + 8192 x 14 bit / 3072 x 28 bit + 6144 x 14 bit / 4096 x 28 bit + 4096 x 14 bit) 4 pattern setting 28bit = F24.4 [24 bit sign & mantissa: 4 bit exponent] 14bit = F10.4 [10 bit sign & mantissa: 4 bit exponent] Sampling frequency: 7.35kHz ~ 96kHz Serial interface port for microcontroller or I2C BUS control Master Clock: 2560fs (generated by PLL from 32fs ,64fs, 256fs and 384fs) Master/Slave operation Serial signal input port (10ch): MSB justified 24-bit / LSB justified 16/20/24-bit and I2S Serial signal output port(12ch): MSB justified 24-bit / LSB justified 24,16-bit and I2S (SDOUT1,SDOUT2 and SDOUT3) [ADC] 4 channels (2 stereo pairs) 24-bit 64X over-sampling delta-sigma (fs = 7.35kHz ~ 96kHz) DR, S/N: 96dBA (fs = 48kHz, fully-differential input) S/(N+D): 92dB (fs = 48kHz) Digital HPF (fc = 1Hz)
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[ADC] Mono single channel 24-bit 64X over-sampling delta sigma (fs = 7.35kHz ~ 96kHz) DR, S/N: 95dBA ( fs = 48kHz) Includes digital attenuator [SRC] Stereo pair Input frequency 7.35kHz ~ 96kHz Output frequency 44.1kHz ~ 96kHz [Other] Power supply: +3.3V 0.3V, +1.7V~+2.0V(typ +1.8V) Operating temperature range: -40C~85C Package: 100pin LQFP(0.5mm pitch)
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[AK7780]
BLOCK DIAGRAM
AINL+,AINR+ AINL-,AINRAINL2,AINR2 AINL3,AINR3 AINL4,AINR4 AINL5,AINR5 AINL6,AINR6 AINL7,AINR7 AINL8,AINR8 AINM
4
2
222222
pull down Hi-z I/O
ASEL1[2:0]
ADCM
ASEL2[2:0]
ctrl reg sw
3 AVDD
ADC1
ADC2
VOL MUX
SELOA1[1:0] 0 1 2 3 SELOA2[1:0] 0 1 2 3 SEL_SDO6 OUTA1E_ N
VREF
VREFH VCOM VREFL
3 AVSS
SDOUTA1
SDIN6
SELI5
SDOUT6 SDOUT5
SDOUT6
SWIRP T SWG1 OUT6E_ N OUT5E_ N OUT4E_ N OUT3E_ N
SDOUT5 SDOUT4 SDOUT3 SDOUT2 SDOUT1
SDIN5
SELI4
SDIN5 SDIN4
SDOUT4
SWG0
SDIN4
SDOUT3
SEL_SDO2
SDOUT2
SELI3
OUT2E_ N
SDIN3
SDIN3 SDIN2
SELI1
SDOUT1 IRPT GPO1 GPO0
OUT1E_ N SEL_SDO1
SDIN2
I2CSEL
MICIF
RQ_N/CAD1 SCLK/SCL SI/CAD0 SO
SDIN1
SDIN1
SRCI SRCOUT
R_SRCSMUTE
DSP
JX2 JX1
SDA RDY JX2 JX1 JX0
WDTE_N
P_SRCSMUTE
R_SRCRST_N
P_SRCRST SRC_LRCK SRC_BICK
SRC
JX0 WDT CRC
SRCSET[1] SRCSET[0] SRC_LFLT TESTO UNLOCK
CRC_E LOCK_E
STO
LRCLK_O BITCLK_O TESTI2 TESTI1 CKM[2:0] 3 P_CKRST
CKRST_N
R_CKRST_N
CONTROLLER
XTI XTO
(Master="H",Slave="L") DSPRST_N
CLKO2E_N
CLKO2 CLKO1
SMODE
CLKO1E_N
P_DSPRST
R_DSPRST_N
S_RESET_N
P_ADRST
R_ADRST_N
2 BVSS
ADRST_N
INIT_RESET
7 DVDD18 3 8 DVSS 3 6 DVDD
LRCLK_I BITCLK_I LFLT
Figure 1. Whole Block Diagram * Figure 1 shows a simplified diagram of the AK7780, which isn't the perfect same as the actual circuit diagram. Each describes the relationship of reset control and target reset blocks.
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[AK7780]
CP0,CP1
DP0
DP1
DLP0,DLP1 DLRAM 6kwx28bit (Default) OFRAM 64wx13bit
CRAM 2048wx16bit
1024wx28bit 1024wx28bit
DRAM CBUS(16bit) DBUS(28bit) Micon I/F Control Serial I/F
MPX16
MPX24
X Multiply 16bitx24bit40bit
Y
DEC
PRAM 2048w x 36bit PC Stack : 5level(max)
28bit 40bit MUL 44bit DBUS SHIFT 44bit A ALU 44bit Overflow Margin: 4bit 44bit DR0~3 44bit Over Flow Data Generator B
TMP 8x28bit PTMP(LIFO) 6x28bit 2x24bit 2x24/20/16bit 2x24/20/16bit 2x24/20/16bit 2x24/20/16bit 2x24/20/16bit 2x24bit 2x24/16bit 2x24/16bit 2x24/16bit 2x24bit 2x24bit SDIN6 SDIN5 SDIN4 SDIN3 SDIN2 SDIN1 SDOUT6 SDOUT5 SDOUT4 SDOUT3 SDOUT2 SDOUT1
Division 24/2424
Peak Detector
Figure 2. DSP Block Diagram
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[AK7780]
Ordering Guide
AK7780VQ AKD7780 -40 +85C 100pin LQFP(0.5mm pitch) Evaluation Board for AK7780
Pin layout
P_SRCSMUT P_SRCRST SDA
SRC_LRCK
SRC_LFLT
SRC_BICK
TESTO AINM AINR4 AINL4 AINR3 AINL3 AINR2 AINL2 AVDD VREFH VCOM VREFL AVSS AINRAINR+ AINLAINL+ AINR5 AINL5 AINR6 AINL6 AINR7 AINL7 AINR8 AINL8
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42
SDOUTA1 STO RDY
SDOUT6
DVDD18
DVDD18
AVSS AVDD TESTI2
CLKO2
SDIN1
DVDD
DVDD
DVSS
DVSS
BVSS
JX0
JX1
JX2
SO DVDD DVSS DVDD18 SCLK/SCL SI / CAD0 RQ / CAD1 P_DSPRST P_ADRST P_CKRST INIT_RESET DVSS DVDD18 LRCLK_I BITCLK_I SDIN5 SDIN4 SDIN3 SDIN2 DVDD18 DVSS DVDD CLKO1 SDOUT5 SDOUT4
100 pin LQFP
(TOP VIEW)
41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
pin
AVDD TESTI1 DVDD I2CSEL DVSS XTO DVSS AVSS BVSS SRCSET[1] SRCSET[0] DVDD18 LFLT XTI LRCLK_O BITCLK_O CKM[1] CKM[0] CKM[2] DVDD18 DVSS DVDD SDOUT2 SDOUT1 SDOUT3
Input Output I/O Power
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PIN FUNCTION
No 1 2 3 4 Pin Name LFLT AVSS AVDD TESTI1 I/O Function Classification Filter connection pin for AK7780 core PLL O When using the PLL function, connect with R (1.5k) and C (47nF) in series Analog Output and connected to analog ground (AVSS) see. 9. System design (1) - Analog ground 0V Analog Power Power supply pin for analog section 3.3V (typ) Supply I TEST pin (Internal pull-down) * Connect to DVSS TEST
5 6 7 8 9 10 11
I2CSEL SRCSET [1] SRCSET [0] BVSS DVDD DVSS XTI
I2CBUS select pin * I2CSEL= "L": Normal serial interface I * I2CSEL= "H": I2CBus selected mode. SCL and SDA are active. I2CSEL must be set to "L (DVSS)" or "H (DVDD)". I SRC select pin 1 I SRC select pin 0 Silicon substrate potential 0V Connect to AVSS.
I2C Select
SRC Analog Power Supply Digital Power Supply
- Power supply pin for digital section 3.3V (typ) - Ground pin for digital section 0V Master clock input pin I Connect a crystal between this pin and the XTO pin, or input an external CMOS clock signal to the XTI pin. Crystal oscillator output pin O When using a crystal, connect it between XTI and XTO. When using an external clock, keep this pin open. - Ground pin for digital section 0V - Power supply pin for digital section 1.8V (typ) I Clock mode select pin 1 I Clock mode select pin 0 I Clock mode select pin 2 - Power supply pin for digital section 1.8V (typ) - Ground pin for digital section 0V - Power supply pin for digital section 3.3V (typ)
System Clock
12 13 14 15 16 17 18 19 20
XTO DVSS DVDD18 CKM [1] CKM [0] CKM [2] DVDD18 DVSS DVDD
Digital Power Supply
Mode select
Digital Power Supply
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No 21
22 23 24 25 26 27 28 29 30 31 32
Function LR channel select clock output pin LRCLK_O O Master mode: Outputs fs clock. Slave mode: Outputs LRCLK_I clock. Serial bit clock output pin BITCLK_O O Master mode: Outputs 64fs clock. Slave mode: Outputs BITCLK_I clock SDOUT1 SDOUT2 SDOUT3 SDOUT4 SDOUT5 CLKO1 DVDD DVSS DVDD18 SDIN2 O O O O O O DSP Serial data output pin * Compatible with MSB justified 24 bits / I2S. DSP Serial data output pin * Compatible with MSB justified 24 bits / I2S. DSP Serial data output pin * Compatible with MSB justified 24 bits / LSB justified 24 and 16 bits/ I2S. DSP Serial data output pin * Compatible with MSB justified 24 bits / LSB justified 24 and 16 bits/ I2S. DSP Serial data output pin * Compatible with MSB justified 24 bits / LSB justified 24 and 16 bits/ I2S. Clock output pin 1 Select the output frequency through a control register.
Pin Name
I/O
Classification
System Clock
Digital section Serial output data
Clock output
- Power supply pin for digital section 3.3V(typ) - Ground pin for digital section 0.0V - Power supply pin for digital section 1.8V(typ) DSP serial data input pin Compatible with MSB justified 24 bits / LSB justified 24, 20 and 16 bits / I2S. * If not used, connect to DVSS DSP serial data input pin I Compatible with MSB justified 24 bits / LSB justified 24, 20 and 16 bits / I2S. * If not used, connect to DVSS Digital section Serial input data DSP serial data input pin I Compatible with MSB justified 24 bits / LSB justified 24, 20 and 16 bits / I2S. * If not used, connect to DVSS DSP serial data input pin I Compatible with MSB justified 24 bits / LSB justified 24, 20 and 16 bits / I2S. * If not used, connect to DVSS I Digital Power Supply
33
SDIN3
34
SDIN4
35
SDIN5
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No 36 37 38 39 40
Pin Name BITCLK_I LRCLK_I DVDD18 DVSS INIT_RESET
I/O I Serial bit clock input pin
Function
Classification System Clock Digital power supply
I LR channel select clock input pin. - Power supply pin for digital section 1.8V(typ) - Ground pin for digital section 0.0V I
41
P_CKRST
I
42
P_ADRST
I
43
P_DSPRST
I
44
RQ CAD1
I
Reset pin ( for initialization) Use for initialization. When changing CKM[2:0], XTI or BITCLK_I input frequency, this reset pin must be used. Clock reset pin When changing CKM[2:0] and XTI or BITCLK_I input frequency without using INIT_RESET, pin control is necessary. The control register R_CKRST_N can also rest the clock. Reset ADC Reset pin The control register R_ADRST_N can also reset the ADC. P_ADRST = "L" and P_DSPRST = "L" state causes a system reset (S_RESET). DSP Reset pin The control register R_DSPRST_N can also rest the DSP. P_ADRST = "L" and P_DSPRST = "L" state causes a system reset (S_RESET). I2CSEL= "L" Microcomputer Microcomputer interface write request pin. Interface. After initial reset, if the microcomputer interface is not used, leave RQ = "H" I2C
I I2CSEL="H" I2C Bus address setting pin 1
45
SI CAD0
Microcomputer interface serial data input and serial data output control Microcomputer I pin. Interface. When SI is not used, leave SI = "L". I I2CSEL= "H" I2C Bus address pin 0 I2CSEL= "L" I Microcomputer interface serial data clock pin. When SCLK is not used, leave SCLK= "H" I I2CSEL= "H" I2C bus data clock pin - Power supply pin for digital section 1.8V(typ) - Ground pin for digital section 0.0V - Power supply pin for digital section 3.3V(typ) O Serial data output pin for microcomputer interfaces. When RQ = "H", SO = Hi-Z Microcomputer Interface. Digital power supply I2C Microcomputer Interface. I2C
46
SCLK SCL
47 48 49 50
DVDD18 DVSS DVDD SO
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No 51
Pin Name RDY
I/O
Function
O Data write ready output pin for microcomputer interface. Status output pin Normal state output "H". O When WDT, CRC error or SRC UNLOCK occurs, then output "L". See 3.(1) Whole block diagram. DSP or ADC Serial data output pin O * Compatible with MSB justified 24 bits / I2S. DSP or ADC Serial data output pin O * Compatible with MSB justified 24 bits / I2S. Clock output pin 2 O Select the output frequency through a control register. - Power supply pin for digital section 3.3V(typ) - Ground pin for digital section 0.0V - Power supply pin for digital section 1.8V(typ) External condition jump pin I * When not used, connect to DVSS External condition jump pin I * When not used, connect to DVSS External condition jump pin I * When not used, connect to DVSS DSP/SRC Serial input pin I Input pin for SRC. When not used, connect to DVSS. I SRC Serial bit clock input pin. I SRC LR channel select clock input pin. I2CSEL= "L" SDA Outputs "L" level. I2CSEL= "H" I/O 2 I C bus interface data pin SRC Reset pin I The control register R_SRCRST_N can also rest the SRC. - Power supply pin for digital section 1.8V(typ) I - Ground pin for digital section 0.0V
Classification Microcomputer Interface. Status
52
STO
53 54 55 56 57 58 59 60 61 62 63 64 65
SDOUTA1 SDOUT6 CLKO2 DVDD DVSS DVDD18 JX2 JX1 JX0 SDIN1 SRC_BICK SRC_LRCK SDA
Digital section Serial output data Clock output Digital power supply
Conditional input
Digital section Serial input data SRC
I2C
66 67 68 69 70 71 72 73 74 75
P_SRCRST DVDD18 DVSS DVDD BVSS P_SRC SMUTE TESTI2 AVDD AVSS SRC_LFLT
RESET Digital power supply
- Power supply pin for digital section 3.3V(typ) Analog power Silicon substrate potential 0V supply Connect to AVSS. SRC Soft mute pin I The control register R_SRCSMUTE can also execute a soft mute on the SRC SRC. TEST pin ( Internal pull-down ) I TEST * Connect to DVSS. - Power supply pin for analog section 3.3V (typ) - Analog ground 0V RC Filter connection pin for SRC. O See p.86 10-2-5-2: SRC PLL loop filter setting. Analog power supply Analog output
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No 76 77 78 79 80 81 82 83 84 85
Pin Name TESTO AINM AINR4 AINL4 AINR3 AINL3 AINR2 AINL2 AVDD VREFH
I/O O I I I I I I I
Function TEST OUT pin Hi-Z Output pin. Leave it open. ADCM single ended analog input ADC1 or ADC2 Rch single ended analog input 4 ADC1 or ADC2 Lch single ended analog input 4 ADC1 or ADC2 Rch single ended analog input 3 ADC1 or ADC2 Lch single ended analog input 3 ADC1 or ADC2 Rch single ended analog input 2 ADC1 or ADC2 Lch single ended analog input 2
Classification TEST
Analog input
- Power supply pin for analog section 3.3V (typ) I
Analog Power Supply
86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
VCOM VREFL AVSS AINR- AINR+ AINL- AINL+ AINR5 AINL5 AINR6 AINL6 AINR7 AINL7 AINR8 AINL8
O I I I I I I I I I I I I I
Analog reference voltage input pin. Connect to AVDD, and connect 0.1F and 10F bypass capacitors between Analog input this pin and AVSS. Common voltage Analog output Connect to 0.1F and 10F capacitors between this pin and AVSS. Do not connect to external circuitry. Analog reference voltage input pin for low-level. Analog input Connect to AVSS. Analog Power Analog ground 0V Supply ADC1 or ADC2 Rch inverted input pin ADC1 or ADC2 Rch non- inverted input pin ADC1 or ADC2 Lch inverted input pin ADC1 or ADC2 Lch non- inverted input pin ADC1 or ADC2 Rch single ended analog input 5 ADC1 or ADC2 Lch single ended analog input 5 Analog input ADC1 or ADC2 Rch single ended analog input 6 ADC1 or ADC2 Lch single ended analog input 6 ADC1 or ADC2 Rch single ended analog input 7 ADC1 or ADC2 Lch single ended analog input 7 ADC1 or ADC2 Rch single ended analog input 8 ADC1 or ADC2 Lch single ended analog input 8
Note 1. Digital input pins must not be allowed to float Note 2. If analog input pins (AINR-, AINR+, AINL-, AINL+, AINL2-8, AINR2-8, AINM) are not used, leave them open. Note 3. I2CSEL should be set to "L" (DVSS) or "H" (DVDD). Relationship with I2CSEL and SDA. I2CSEL Normal Microcontroller Interface I2C bus compatible L L H H INIT_RESET L H L H SDA L L "Hi-Z" pull-up function
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ABSOLUTE MAXIMUM RATINGS
(AVSS = BVSS = DVSS = 0V: All indicated voltages are with respect to ground.) Item Symbol min Power supply voltage VA Analog(AVDD) -0.3 VD Digital(DVDD) -0.3 VD18 Digital(DVDD18) -0.3 |AVSS(BVSS) - DVSS| (Note 4) GND Input current (except for power supply pin ) IIN Analog input voltage AINL+, AINL-, AINR+, AINR-, VINA -0.3 AINL2-8, AINR2-8, AINM VREFH,VREFL Digital input voltage VIND -0.3 Operating ambient temperature Ta -40 Storage temperature Tstg -65 Note 4. AVSS (BVSS) should be at the same level as DVSS. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these critical conditions.
max 4.3 4.3 2.5 0.3 10 VA+0.3 VD+0.3 85 150
Unit V V V V mA V V C C
RECOMMENDED OPERATING CONDITIONS
(AVSS = BVSS = DVSS = 0V: All indicated voltages are with respect to ground.) Items Symbol min typ max Unit Power supply voltage AVDD VA 3.0 3.3 3.6 V DVDD VD 3.0 3.3 3.6 V DVDD18 VD18 1.7 1.8 2.0 V Reference voltage (VREF) VREFH (Note 5) VRH VA V VREFL (Note 6) VRL 0.0 V Note 5. VREFH normally connects to AVDD. Note 6. VREFL normally connects to AVSS Note: The analog input voltage and output voltage are proportional to the VREFH-VREFL voltages. * AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet.
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[AK7780]
ELECTRIC CHARACTERISTICS (1) Analog Characteristics
1) ADC Characteristics
(Unless otherwise specified, Ta = 25C; AVDD = DVDD = 3.3V, DVDD18=1.8V; VREFH = AVDD, VREFL = AVSS; BITCLK = 64 fs; signal frequency = 1kHz; Measurement bandwidth = 20Hz to 20kHz @ 48kHz, 20Hz ~ 40kHz @ 96kHz; ADC specified with differential inputs (ADC1, ADC2); CKM Mode 1(CKM[2:0]= "000"), SRC RESET) Parameter min typ max Resolution 24 Dynamic characteristics S/(N+D) fs = 48kHz (-1dBFS) (Note 7) 82 92 ADC1 Fs = 96kHz (-1dBFS) 90 ADC2 Dynamic range fs = 48kHz (A filter) (Note 7, Note 8) 88 96 fs = 96kHz 93 S/N fs = 48kHz (A filter) (Note 7) 88 96 fs = 96kHz 93 Inter-channel isolation (f=1kHz) (Note 9) 90 115 DC accuracy Channel gain mismatch 0.1 0.3 Analog input Input voltage ( Differential input ) (Note 10) 1.85 2.00 2.15 Input voltage ( Single-ended input ) (Note 11) 1.85 2.00 2.15 Input impedance (Note 12) 22 33 24 Monaural Resolution ADC part Dynamic characteristics S/(N+D fs = 48kHz (-1dBFS) 78 88 ADCM fs = 96kHz ( -1dBFS) 87 Dynamic range fs = 48kHz (A filter) (Note 8) 87 95 fs = 96kHz 92 S/N fs = 48kHz (A filter) 87 95 fs = 96kHz 92 Analog input Input voltage (Note 13) 1.85 2.00 2.15 Input impedance (Note 14) 22 33 Note 7. This value is not guaranteed for single-ended inputs. Note 8. Indicates S/(N+D) when -60 dBFS signal is applied. Note 9. Indicates isolation between L and R when -1dBFS signal is applied. Note 10. Target input pins are AINL+, AINL-, AINR+ and AINR-. Differential full scale is (FS=(VREFH-VREFL)x(2.0/3.3)) Note 11. Target input pins are AINL2~L8, AINR2~R8., Single-ended full scale is (FS=(VREFH-VREFL) x (2.0/3.3)) Note 12. Target input pins are AINL+, AINL-, AINR+, AINR-, AINL2-L8, AINR2-R8. Note 13. Target input pin is AINM, The full scale of this pin is (FS=(VREFH-VREFL) x (2.0/3.3)) Note 14. Target input pin is AINM. Stereo ADC Unit Bits dB dB dB dB dB dB dB dB Vp-p Vp-p k Bits dB dB dB dB dB dB Vp-p k
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2) SRC Characteristics
(Ta=25C; AVDD = 3.3V; DVDD=3.3V; DVDD18=1.8V; data = 24-bits; measurement bandwidth = 20Hz FSO/2; unless otherwise specified.) Parameter Symbol min typ max Units Resolution 24 Bits Input Sample Rate FSI 7.35 96 kHz Output Sample Rate FSO 44.1 96 kHz THD+N (Input= 1kHz, 0dBFS) FSO/FSI=44.1kHz/48kHz -113 dB FSO/FSI=44.1kHz/96kHz -112 dB FSO/FSI=48kHz/44.1kHz -113 dB FSO/FSI=48kHz/96kHz -113 dB FSO/FSI=48kHz/8kHz -112 -103 dB Dynamic Range (Input= 1kHz, -60dBFS) FSO/FSI=44.1kHz/48kHz 114 dB FSO/FSI=44.1kHz/96kHz 114 dB FSO/FSI=48kHz/44.1kHz 114 dB FSO/FSI=48kHz/96kHz 114 dB FSO/FSI=48kHz/8kHz 110 114 dB Dynamic Range (Input= 1kHz, -60dBFS, A-weighted FSO/FSI=44.1kHz/48kHz 116 dB Ratio between Input and Output Sample Rate FSO/FSI 0.45 6 -
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(2) DC Characteristics
(Ta = -40C ~ 85C; AVDD = DVDD = 3.0~3.6V; DVDD18 = 1.7~2.0V) Parameter Symbol min High level input voltage (Note 15) VIH 80%DVDD Low level input voltage (Note 15) VIL SCL,SDA High level input voltage VIH 70%DVDD SCL,SDA Low level input voltage VIL VOH DVDD-0.5 High level output voltage Iout=-100A VOL Low level output voltage Iout=100A (Note 16) SDA Low level output voltage Iout=3mA VOL Input leak current (Note 17) Iin Input leak current (pull-down) (Note 18) Iid Input leak current (XTI pin ) Iix typ max 20%DVDD 30%DVDD 0.5 0.4 10 22 26 Unit V V V V V V V A A A
Note 15. SCL (I2CSEL=1) and SDA pins are not included. (SCLK pin is included when I2CSEL=0) Note 16. SDA pin is not included. Note 17. The pull-down pins and XTI pin are not included. Note 18. The pull-down pins (Typ150k) are: TESTI1, TESTI2
(3) Current Consumption
(Ta=25C; AVDD=DVDD=3.0~3.6V(typ=3.3V,max=3.6V); DVDD18=1.7~2.0V(typ=1.8V, max=2.0V)) Power supply Parameter min typ max Power supply current (Note 19) 1) a) AVDD 52 70 b) DVDD 8 15 c) DVDD18 110 165 1 2) INIT_RESET = "L" (reference) (Note 20)
Unit mA mA mA mA
Note 19. Varies slightly according to the system frequency and contents of the DSP program. Note 20. This is a reference value when using a crystal oscillator. Since most of the supply current at the initial reset state is in the oscillator section, the value may vary slightly according to the crystal type and the external circuit. This is a "reference value" only.
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(4) Digital Filter Characteristics
1) ADC Section: ADC1, ADC2
(Ta=-40C~85C; AVDD = DVDD =3.0V~3.6V; DVDD18=1.7V~2.0V; fs=48kHz; Note 21) Parameter Symbol min typ max Unit PB 0 21.5 kHz Pass band (0.005dB) (Note 22) 21.768 kHz (-0.02dB) 24.00 kHz (-6.0dB) Stop band SB 26.5 kHz Pass band ripple (Note 22) PR 0.005 dB Stop band attenuation (Note 23, Note 24) SA 80 dB Group delay distortion 0 GD s Group delay (Ts=1/fs) GD 29 Ts Digital filter + SFC Amplitude characteristics (20Hz~20.0kHz) 0.01 dB Note 21. Each parameter is related to the sampling frequency (fs). HPF response is not included. Note 22. The pass band is from DC to 21.5kHz at fs = 48kHz. Note 23. The stop band is from 26.5kHz to 3.0455MHz at fs = 48kHz. Note 24. When fs = 48kHz, the analog modulator samples the analog input at 3.072MHz. The input signal is not attenuated by the digital filter in multiple bands (n x 3.072MHz 21.99kHz; n=0, 1, 2, 3...) of the sampling frequency.
2) ADC Section ADCM
(Ta=-40C~85C; AVDD = DVDD =3.0V~3.6V; DVDD18=1.7V~2.0V; fs = 48 kHz; Note 25) Parameter Symbol min typ max PB 0 21.5 Pass band (0.005dB) (Note 26) 21.768 (-0.02dB) 24.00 (-6.0dB) Stop band SB 26.5 Pass band ripple (Note 26) PR 0.005 Stop band attenuation (Note 27, Note 28) SA 80 Group delay distortion 0 GD Group delay (Ts=1/fs) (Note 29) GD 29 Digital filter + SFC Amplitude characteristics (20Hz~20.0kHz) 0.1
Unit kHz kHz kHz kHz dB dB s Ts dB
Note 25. Each parameter is related to the sampling frequency (fs). HPF response is not included. Note 26. The pass band is from DC to 21.5kHz at fs = 48kHz. Note 27. The stop band is from 26.5kHz to 3.0455MHz at fs = 48kHz. Note 28. When fs = 48kHz, the analog modulator samples the analog input at 3.072MHz. The input signal is not attenuated by the digital filter in the multiple bands (n x 3.072MHz 21.99kHz; n=0, 1, 2, 3...) of the sampling frequency. Note 29. VOL+ MUX path adds one additional Ts.
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3) SRC
(Ta=-40C~85C; AVDD=DVDD=3.0~3.6V; DVDD18 = 1.7~2.0V) Parameter Range Symbol min typ max Pass band -0.01dB PB 0 0.4583FSI 0.980 FSO/FSI 6.000 PB 0 0.4167FSI 0.900 FSO/FSI < 0.990 PB 0 0.2182FSI 0.533 FSO/FSI < 0.909 PB 0 0.2177FSI 0.490 FSO/FSI < 0.539 PB 0 0.1948FSI 0.450 FSO/FSI < 0.495 Stop band SB 0.5417FSI 0.980 FSO/FSI 6.000 SB 0.5021FSI 0.900 FSO/FSI < 0.990 SB 0.2974FSI 0.533 FSO/FSI < 0.909 SB 0.2812FSI 0.490 FSO/FSI < 0.539 SB 0.2604FSI 0.450 FSO/FSI < 0.495 Pass band ripple PR 0.01 Stop band attenuation SA 95.2 Group delay (Ts=1/fs) GD 56 (Note 30) Note 30. Measured from the rising edge of SRC_LRCK on the input to the rising edge of LRCLK_O on the output, with there is no phase difference between input and output.
Unit kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz dB dB Ts
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(5) Switching Characteristics
[ #h means hexadecimal code. (#=0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F)]
1) System Clock
(Ta = -40~85C; AVDD=DVDD=3.0V~3.6V; DVDD18 = 1.7V~2.0V) Parameter Symbol min XTI CKM[2:0] 0h,1h,2h,3h a) with a crystal oscillator: CKM[2:0]=0h,2h fXTI CKM[2:0]=1h,3h b) with an external clock Duty cycle CKM[2:0]=0h,2h CKM[2:0]=1h,3h Clock rise time Clock fall time LRCLK_I frequency Clock rise time Clock fall time (Note 31) fXTI -
typ
max
Unit
11.2896 12.288 16.9344 18.432 50
-
MHz MHz
fXTI fXTI tCR tCF fs tLR tLF
40 11.0 16.5
60 12.4 18.6 6 6 96 6 6
% MHz MHz ns ns kHz ns ns
7.35
48
BITCLK_I frequency High level width tBCLKH 64 ns Low level width tBCLKL 64 ns Clock rise time tBR 6 ns Clock fall time tBF 6 ns fBCLK 64 fs a) CKM[2:0]=2h,3h Duty cycle 40 50 60 % CKM[2:0]=2h,3h 0.23 6.2 MHz 64 fs b) CKM[2:0]=4h,5h (Note 32) fBCLK Duty cycle 40 50 60 % CKM[2:0]=4h fBCLK 2.75 3.1 MHz CKM[2:0]=5h fBCLK 5.5 6.2 MHz Note 31. LRCLK and sampling rate (fs) should match. Note 32. When BITCLK_I uses as a resource of master clock, it should be 64 clocks correctly divided within 1fs.
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(Ta = -40C ~85C; AVDD=DVDD=3.0~3.6V, DVDD18 = 1.7~2.0V) Parameter Symbol min fs 7.35 SRC_LRCK frequency (Note 33) Clock rise time Clock fall time SRC_BICK frequency High level width Low level width Clock rise time Clock fall time (Note 34) Duty factor Note 33. SRC_LRCK and sampling rate (fs) should match. Note 34. 128fs is up to fs = 48kHz. tLR tLF tBCLKH tBCLKL tBR tBF fBCLK 60 60
typ 48
max 96 6 6
Unit kHz ns ns ns ns ns ns fs % MHz
32 40 0.23
50
6 6 128 60 6.2
2) Reset
(Ta=-40C ~85C; AVDD=DVDD=3.0~3.6V; DVDD18 = 1.7~2.0V) Parameter Symbol min tRST 600 INIT_RESET (Note 35) P_CKRST P_ADRST P_DSPRST P_SRCRST tRST tRST tRST tRST 600 600 600 600
typ
max
Unit ns ns ns ns ns
Note 35. "L" is acceptable when power is turned on, but a stable master clock must present before transitioning to "H".
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3) Audio interface 3-1) SDIN1~SDIN5,SDOUT1~SDOUT6,SDOUTA1 (Up to fs = 96kHz) AKM Normal and I2S Compatible Format
(Ta = -40C~85C; AVDD=DVDD=3.0~3.6V, DVDD18 = 1.7~2.0V, CL=20pF) Parameter Symbol min Slave mode CKM[2:0]=2h, 3h, 4h, 5h 20 Delay time from BITCLK_I "" to LRCLK_I (Note 36) tBLRD tLRBD 20 Delay time from LRCLK_ I to BITCLK_I "" (Note 36) Delay time from LRCLK_I, LRCLK_O to serial data output tLRD Delay time from BITCLK_I, BITCLK_O to serial data tBSOD output Serial data input latch setup time tBSIDS 40 Serial data input latch hold time tBSIDH 40 Master mode CKM[2:0]=0h, 1h BITCLK_O frequency fBCLK BITCLK_O duty cycle tBLRD -20 Delay time from BITCLK_O "" to LRCLK_O Delay time from LRCLK_O to serial data output tLRD Delay time from BITCLK_O to serial data output tBSOD Serial data input latch setup time tBSIDS 40 Serial data input latch hold time tBSIDH 40 Note 36. LRCLK_I edge and BITCLK_I ""edge cannot be synchronous.
typ
max
Unit ns ns ns ns ns ns
40 40
64 50 40 40 40
fs % ns ns ns ns ns
3-2) SDIN1(SRCI Input) (Up to fs = 96kHz)
(Ta=-40C~85C; AVDD=DVDD=3.0~3.6V, DVDD18 = 1.7~2.0V) Parameter Symbol Slave mode Delay time from SRC_BICK "" to SRC_LRCK (Note 37) tBLRD Delay time from SRC_LRCK to SRC_BICK "" (Note 37) tLRBD Serial data input latch setup time tBSIDS Serial data input latch hold time tBSID H Note 37. SRC_BICK edge and SRC_LRCK edge cannot be synchronous.
min 20 20 40 40
typ
max
Unit ns ns ns ns
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3) Microcontroller Interface
(Ta = -40~85C; AVDD=DVDD=3.0V~3.6V, DVDD18 = 1.7~2.0V, CL = 20pF) Parameter Symbol min Microcomputer interface signal RQ Fall time RQ Rise time SCLK fall time SCLK rise time SCLK frequency SCLK low level width SCLK High level width Microcomputer to AK7780 Time from P_DSPRST , P_ADRST "" to RQ "" Time from RQ "" to P_DSPRST , P_ADRST "" RQ high level width Time from RQ "" to SCLK"" Time from SCLK"" to RQ "" SI latch setup time SI latch hold time AK7780 to Microcomputer Delay time from SCLK"" to SO output Hold time from SCLK"" to SO output tWRF tWRR tSF tSR fSCLK tSCLKL tSCLKH tREW tWRE tWRQH tWSC tSCW tSIS tSIH tSOS tSOH tRQHR tRQHS
typ
max 30 30 30 30 2.1
Unit ns ns ns ns MHz ns ns ns ns ns ns ns ns ns
200 200 500 500 500 500 800 200 200 300 200 600 600
(Note 38)
ns ns ns ns
Time from RQ "" to SO Hi-Z (Iout=360A) release RQ "" to SO Hi-Z set (Iout=360A) Note 38. Except last 1bit of the command code.
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4) I2C BUS Interface
(Ta = -40C~85C; AVDD=DVDD=3.0~3.6V, DVDD18 = 1.7~2.0V) Parameter Symbol I2C Timing SCL clock frequency fSCL Bus Free Time Between Transmissions tBUF Start Condition Hold Time (prior to first Clock pulse) tHD:STA Clock Low Time tLOW Clock High Time tHIGH Setup Time for Repeated Start Condition tSU:STA SDA Hold Time from SCL Falling tHD:DAT SDA Setup Time from SCL Rising tSU:DAT Rise Time of Both SDA and SCL Lines tR Fall Time of Both SDA and SCL Lines tF Setup Time for Stop Condition tSU:STO Pulse Width of Spike Noise Suppressed By Input Filter tSP Capacitive load on bus
2
Min
Typ
Max 400
Unit kHz s s s s s s s s s s ns pF
1.3 0.6 1.3 0.6 0.6 0 0.1
0.9 0.3 0.3
0.6 0
50 400
Cb
Note 39. I C is a registered trademark of Philips Semiconductors.
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(6) Timing Diagram
1) System clock
1/fXTI 1/fXTI tXTI=1/fXTI
VIH
XTI
tCR tCF
VIL
ts=1/fs 1/fs
LRCLK_I SRC_LRCK
tLR 1/fBCLK 1/fBCLK tLF
VIH VIL
tBCLK=1/fBCLK
VIH
BITCLK_I SRC_BICK
tBCLKH tBCLKL
VIL tBR tBF
2) RESET
NIT_RESET P_CKRST P_ADRST
P_DSPRST VIL tRST
P_SRCRST
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3) Audio Interface
Normal and I2S compatible format
LRCLK I LRCLK_O
tBLRD tLRBD tMB tMBL
50%DVDD
BITCLK_I BITCLK_O
tLRD SDOUT * tBSIDS SDIN * tBSIDH tBSOD
50%DVDD
50%DVDD
50%DVDD
SDIN * =SDIN1, SDIN2, SDIN3, SDIN4, SDIN5 SDOUT * =SDOUT1, SDOUT2, SDOUT3, SDOUT4, SDOUT5, SDOUT6, SDOUTA1
SRC
SRC_LRCK
tBLRD tLRBD 50%DVDD
SRC_BICK
50%DVDD
tBSIDS SRCI=SDIN1
tBSIDH 50%DVDD
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4) Microcontroller Interface
Microcontroller interface
RQ
tWRF tSF tWRR tSR
VIH VIL
SCLK
tSCLKL tSCLKH
VIH VIL
1/fSCLK 1/fSCLK
Microcontrollerr
AK7780 tREW tWRE
P_DSPRST P_ADRST RQ
tWSC tWRQH VIL VIH VIL
SI
tSIS tSIH
VIH VIL
SCLK
tSCW tWSC tSCW
VIH VIL
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AK7780
Microcontroller
SCLK
VIH VIL VIH VIL
tSOS tSOH
SO
Note: Timing during the RUN state is identical, except that P_DSPRST and P_ADRST are "H".
RQ
tRQHR tRQHS
VIH VIL
SO
Hi-Z
5) I2C Bus Interface
VIH SDA VIL tBUF SCL VIL tHD:STA Stop Start tHD:DAT tSU:DAT tSU:STA Start tSU:STO Stop tLOW tR tHIGH tF tSP VIH
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PACKAGE
* 100 pin LQFP (Unit: mm )
16.00.3 14.0 75 76 51 50 0.20max 1.70 Max.
16.00.3
100 1 0.5 0.220.05 25
26
0.170.05 0.10 M
1.0
0~10 0.50.2 0.10
Material & Lead finish
Package: Epoxy Lead-frame: Cu Lead-finish: Solder (Pb free) plate
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MARKING
AKM
AK7780VT XXXXXXX
1) 2) 3) 4)
Pin #1 indication Date Code: XXXXXXX(7digits) Marking Code: AK7780VT Asahi Kasei Logo
IMPORTANT NOTICE These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification.
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Thank you for your access to AKEMD product informations. More detail product informations are available, please contact our sales office or authorized distributors.
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