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JUNE 2004
XRD9818
REV. 1.0.1
3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
GENERAL DESCRIPTION
The XRD9818 is a fully integrated, high-performance analog signal processor/digitizer specifically designed for use in 3-channel/2-channel/1-channel CCD/CIS document imaging applications. Each channel of the XRD9818 includes a Correlated Double Sampler (CDS), Offset adjustment, Programmable Gain Amplifier (PGA). After the gain and offset adjustments the analog inputs are sequentially sampled and digitized by a 16-bit A/D converter. The digital output data is available in 8 or 4-bit wide multiplexed format. The analog front-end can be configured for use in CCD or CIS data acquisition applications. The CDS mode of operation supports both line and pixel-clamp modes and can be used to achieve significant reduction in system 1/f noise and CCD reset clock feed-through. Five programmable clamp levels are available in CCD mode to adjust for CCD signal swing and reset pulse size. For CIS mode there are 3 selectable reference options, two internally generated and one external applied reference. Two PGA ranges, programmable through the serial port, help interface the XRD9818 to CCD imagers that have either a 3V or 2V output swings. The range of 1x to 5x is used for 3V inputs and the range of 1.5x to 7.5x is used for 2V inputs. Each channel has an offset range of -180mV to 180mV (1.4mV/step) for fine adjustment and an additional -100mV to 200mV (100mV/step) of gross offset adjustment to correct for any system offsets.
FEATURES
* 16-Bit A/D Converter * Triple-Channel, 4MSPS Color Scan Mode * Single-Channel, 8MSPS Monochrome Scan Mode * Multiplexed 8-Bit or 4-Bit Output Data Formats * Triple Correlated Double Sampler * Triple 9-Bit Programmable Gain Amplifier * Two Programmable Gain Ranges * Triple 10-Bit Offset Compensation DAC * -280mV to +380mV Offset Compensation * 28-pin TSSOP Package * Internal Voltage Reference * 3V Operation with 5V Tolerant inputs * Low Power CMOS: 190mW @ 3.3V (typ), Power
Down 1mW (typ)
APPLICATIONS
* 48-Bit Color Scanners * High-performance CCD or CIS Color Scanners * Multifunction Peripherals * Film Scanners
Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com
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XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
REV. 1.0.1
FIGURE 1. BLOCK DIAGRAM OF THE XRD9818
INTERNAL TIMING CONTROL
BSAMP VSAMP ADCLK LCLMP
9-BIT
RED(+)
Programmable Buffered CDS or S/H
PGA
AVDD AVDD
REGISTER REGISTER VREF 1.24V
AGND AGND
10-Bit Offset DAC
REFIN 9-BIT
DVDD DGND
GRN(+) CMN(-)
Programmable Buffered CDS or S/H
PGA
3-1 MUX
OUTPUT PORT
16-BIT A/D
16 VREF- VCM VREF+
4/8
Output Data Bus
REGISTER REGISTER
CAPP CMREF CAPN
10-Bit Offset DAC
9-BIT
BLU(+)
Programmable Buffered CDS or S/H
PGA
REGISTER REGISTER
Clamp/ Reference DAC
I/O CONTROL AND CONFIGURATION REGISTERS
SDI SCLK LOAD
10-Bit Offset DAC
PRODUCT ORDERING INFORMATION
Product Number XRD9818ACG Package Type 28-Lead TSSOP Operating Temperature Range 0C to +70C
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XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
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FIGURE 2. PIN OUT OF THE XRD9818
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23
XRD9818
22 21 20 19 18 17 16 15
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PIN DESCRIPTIONS
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Name RED+ AGND AVDD LCLMP VSAMP BSAMP ADCLK DGND LOAD DVDD SDI SCLK ADCO[0] ADCO[1] ADCO[2] ADCO[3] ADCO[4] ADCO[5] ADCO[6] ADCO[7] AVDD AGND CAPN CAPP CMREF CMNBLU+ GRN+
Type analog ground power clock clock clock clock ground digital in power digital in clock output output output output output output output output power ground analog analog analog analog analog analog RED Analog Positive Input ANALOG GROUND ANALOG VDD Line Clamp clock Video Sample clock Black Sample clock ADC clock Digital GROUND Serial Port Load Digital VDD Serial Port Data Input Serial Port Clock ADC parallel out 0 ADC parallel out 1 ADC parallel out 2 ADC parallel out 3 ADC parallel out 4 ADC parallel out 5 ADC parallel out 6 ADC parallel out 7 ANALOG VDD ANALOG GROUND ADC Reference By-Pass ADC Reference By-Pass
Description
(8-bit LSB)
(4-bit LSB)
(8-bit/4-bit MSB)
Common Mode Reference for ADC COMMON Analog Reference Negative Input BLUE Analog Positive Input GREEN Analog Positive Input
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XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
REV. 1.0.1
ELECTRICAL CHARACTERISTICS - XRD9818
AVDD=DVDD=3.3V, ADCLK=12MHZ, PGA GAIN=MIN, PIXEL RATE=4MHZ, TA=25C UNLESS OTHERWISE SPECIFIED Parameter Symbol Min Typ Max Unit Conditions
SYSTEM SPECIFICATIONS (INCLUDES CDS, PGA AND A/D) Differential Non-Linearity Integral Non-Linearity Output Noise Low Gain Output Noise High Gain System Offset Low Gain System Offset High Gain DNL INL NMin NMax SOMin SOMax -50 -1.0 -0.9/+0.9 50 15 34 20 20 100 2.5 LSB LSB LSBrms LSBrms mV mV PGA Gain = min PGA Gain = min PGA Gain = min, GS=0 PGA Gain = max, GS=0 PGA Gain = min PGA Gain = max
Parameter
Symbol
Min
Typ
Max
Unit
Conditions
VOLTAGE REFERENCE SPECIFICATIONS Vref(+) Vref(-) Delta Vref [Vref(+) - Vref(-)] VCMREF CAPP CAPN VREF 1.9 0.5 1.25 2.2 0.7 1.5 2.5 0.9 1.75 V V V
VCM
1.05
1.2
1.35
V
Parameter
Symbol
Min
Typ
Max
Unit
Conditions
CDS - S/H SPECIFICATIONS Input Switch-On Resistance Input Switch-Off Resistance Internal Voltage Clamp Internal Voltage Clamp Max Reset Pulse Input Voltage Range Ron Roff Vclmp1 Vclmp2 Vrst INVR 66 2.8 -0.1 1.5 3.0 2.0 150 330 3.0 0.0 3.125 0.1 M V V V V V GS=0 GS=1 Clamp Enabled Clamp Disabled CL[2:0]=110 CL[2:0]=001
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XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
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ELECTRICAL CHARACTERISTICS (CONTINUED) - XRD9818
AVDD=DVDD=3.3V, ADCLK=12MHZ, PGA GAIN=MIN, PIXEL RATE=4MHZ, TA=25C UNLESS OTHERWISE SPECIFIED Parameter Symbol Min Typ Max Unit Conditions
OFFSET SPECIFICATIONS Fine Offset Range Min Fine Offset Range Max Fine Offset Step Fine Offset Range Linearity Gross Offset Range Min Gross Offset Range Max Gross Offset Step FOFRFOFR+ FOFRES FOFRL -255 +120 -180 +180 1.4 +/-1.5 -120 +255 mV mV mV %FS 8-bit (256 settings)
GOFRGOFR+ GOFRES
-260 +75
-200 +100 100
-150 +135 mV 2-bit (4 setting)
Parameter
Symbol
Min
Typ
Max
Unit
Conditions
PGA SPECIFICATIONS Gain Range Min Gain Range Max Gain Resolution Gain Range Min Gain Range Max Gain Resolution GRMin GRMax GRES GRMin GRMax GRES 0.84 4.5 -10.0 1.3 6.65 1 5 7.8 1.5 7.5 11.7 1.2 6.20 1.7 8.90 V/V V/V mV/lsb V/V V/V mV/lsb default Gain Select, GS=0 default Gain Select, GS=0 default Gain Select ,GS=0 Gain Select , GS=1 Gain Select , GS=1 Gain Select , GS=1
Parameter
Symbol
Min
Typ
Max
Unit
Conditions
DIGITAL INPUT SPECIFICATIONS Valid Input Logic Low Valid Input Logic High Low Level Input Current High Level Input Current Input Capacitance Vil Vih Iil Iih CIN 2.60 -5 10 0.1 65 10 5 150 0.5 V V A A pf w/internal 50K pull down R's
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XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
REV. 1.0.1
ELECTRICAL CHARACTERISTICS (CONTINUED) - XRD9818
AVDD=DVDD=3.3V, ADCLK=12MHZ, PGA GAIN=MIN, PIXEL RATE=4MHZ, TA=25C UNLESS OTHERWISE SPECIFIED Parameter Symbol Min Typ Max Unit Conditions
DIGITAL OUTPUT SPECIFICATIONS Valid Output Logic Low Valid Output Logic High Tristate Leakage Vol Voh IOLeak VDD-0.5 -10 0.1 +10 0.5 V V A ISink = 2.0mA, CL=10pf ISource = 2.0mA, CL=10pf
Parameter
Symbol
Min
Typ
Max
Unit
Conditions
POWER SUPPLIES - 3 CHANNEL MODE Analog Power Supply Digital Power Supply Analog IDD Digital IDD IDD Total Power Dissipation Power Down Current AVDD DVDD IAVDD IDVDD IDD PD IDDPDN 3.0 3.0 30 0.1 31 112 3.3 3.3 57 7 64 230 0.2 3.6 3.6 70 20 90 325 1.3 V V mA mA mA mW AVDD = DVDD = 3.6V AVDD = DVDD = 3.6V AVDD = DVDD = 3.6V AVDD = DVDD = 3.6V
Parameter
Symbol
Min
Typ
Max
Unit
Conditions
POWER SUPPLIES - 1 CHANNEL MODE Analog Power Supply Digital Power Supply IDD Total Power Dissipation Power Down Current AVDD DVDD IDD PD IDDPDN 3.0 3.0 3.3 3.3 40 145 0.2 1.3 3.6 3.6 V V mA mW mA AVDD = DVDD = 3.6V AVDD = DVDD = 3.6V
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ELECTRICAL CHARACTERISTICS (CONTINUED) - XRD9818
AVDD=DVDD=3.3V, ADCLK=12MHZ, PGA GAIN=MIN, PIXEL RATE=4MHZ, TA=25C UNLESS OTHERWISE SPECIFIED Parameter Symbol Min Typ Max Unit Conditions
SERIAL PORT WRITE TIMING SPECIFICATIONS Data Setup Time Data Hold Time Load Setup Time Load Hold Time SCLK Period Load Pulse High Period Tds Tdh Tls Tlh Tsclk Tlpw 10 10 10 10 125 125 ns ns
ns ns ns ns 1 SCLK period
Parameter
Symbol
Min
Typ
Max
Unit
Conditions
TIMING SPECIFICATIONS ADCLK Duty Cycle ADCLK Period daclk tcp3b tcp3n tcp2b tcp2n tcp1b tcp1n tcr3 tcr2 tcr1 tpwb tpwv tvfcr tstl tap todv lat 83.3 41.7 83.3 41.7 125 62.5 250 167 125 15 15 12 15 3 12 9 18 30 30 50 % ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ADCLK cycles B/N=0 (byte mode) B/N=1 (nibble mode) 3-CH, 8bit (byte) output 3-CH, 4bit (nibble) output 2-CH, 8bit (byte) output 2-CH, 4bit (nibble) output 1-CH, 8bit (byte) output 1-CH, 4bit (nibble) output 3-Channel Mode 2-Channel Mode 1-Channel Mode
Conversion Period
BSAMP Pulse Width VSAMP Pulse Width VSAMP edge delay from rising ADCLK Settling time Aperture Delay Output Delay Latency
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PRODUCT DESCRIPTION
1.0 INTRODUCTION
XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
REV. 1.0.1
The XRD9818 contains all of the circuitry required to create a complete 3-channel signal processor/digitizer for use in CCD/CIS imaging systems. It can be configured to operate in a 3-CH rotating (RGB), 2-CH rotating (RG, GR, GB or BR), or a 1-CH fixed (R, G or B) mode. Each channel includes a correlated-double-sampler/sample-hold (CDS/SH), channel offset adjustment and programmable gain amplifier (PGA). After signal conditioning the channel outputs are multiplexed and digitized by a 16-bit A/D converter. The XRD9818 has selectable 8-bit (byte) or 4-bit (nibble) data output modes. The ADCLK runs up to 12MHz in the 8-bit data output mode or 24MHz in the 4-bit data output mode. In order to maximize flexibility, the specific operating mode is programmable through internal configuration registers. In addition, the offset and gain of each channel can be independently programmed through separate offset and gain registers. The configuration, offset and gain register information is loaded through a 3-pin serial interface. 2.0 MODES OF OPERATION 2.1 3-CH CCD Mode In 3-CH mode the XRD9818 simultaneously samples the red, green and blue channel inputs. The CDS extracts the video information which corresponds to the difference between the sample black reference and video level for each pixel. The black reference level is sampled on the falling edge of BSAMP and the video level is sampled on the falling edge of VSAMP. This information is then level shifted and gained up according to the contents of the Offset and PGA registers respectively. The data is then sequentially converted (Red Green Blue) by a 16-bit A/D converter. In CCD mode, each channel input is sampled with respect to the CMN- input. This provides a sudo-differential input. Typically the CMN- input is connected to the CCD ground through a capacitor. This coupling capacitor should be at least 3 times the capacitor value used to couple the RED+, GRN+ and BLU+ inputs. The timing for this mode is shown in Figure 15. 2.2 2-CH CCD Mode The 2-CH mode operates identically to the 3-CH CCD mode except that only 2 channels are actively used to process CCD output signals. The two channels to be used and the order in which they process data is determined from the configuration of the Input-Mux/Channel-Select bits (CH[2:0]) located in the Mode 1 register. There are four possible 2-CH configurations, RG, GR, GB and BR. To conserve power that channel not being utilized is powered down. The timing for this mode is shown in Figure 16. 2.3 1-CH CCD Mode The 1-CH mode operates identically to the 3-CH or 2-CH CCD modes except that the channel sampled is fixed to only one input. The channel selection is set by the Input-Mux/Channel-Select bits (CH[2:0]) located in the Mode 1 register. There are three possible one channel modes: R, G or B. The channels not being used will be powered down to conserve power. The timing for this mode is shown in Figure 17.
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XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
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2.4
3-CH CIS Mode
In this mode the XRD9818 simultaneously samples (S/H) the red, green and blue channel inputs. The video level is sampled on the falling edge of VSAMP. Each channels S/H extracts the video information from each pixel. This data is level shifted and gained up according to the contents of the Offset and PGA registers respectively. The data is then sequentially converted (Red Green Blue) by a 16-bit A/D converter. In CIS mode, each channel input is sampled with respect to the voltage at the CMN- input. The voltage at CMN- can be either generated by a programmable internal reference (C/R DAC) or supplied by an external source. The timing for this mode is shown in Figure 18. 2.5 2-CH CIS Mode The 2-CH mode operates identically to the 3-CH CIS mode except that only 2 channels are actively used to process CIS output signals. The two channels to be used and the order in which they process data is determined from the configuration of the Input-Mux/Channel-Select bits (CH[2:0]) located in the Mode 1 register. There are four possible 2-CH configurations, RG, GR, GB and BR. To conserve power the channel not being utilized is powered down. 2.6 1-CH CIS Mode The 1-CH mode operates identically to the 3-CH or 2-CH CIS modes except that the channel sampled is fixed to only one input. The channel selection is set by the Input-Mux/Channel-Select bits (CH[2:0]) located in the Mode 1 register. There are three possible one channel modes: R, G or B. The channels not being used will be powered down.
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3.0 REGISTER MAP INTERNAL REGISTER MAP
XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
REV. 1.0.1
Register Name
RED Gain GREEN Gain BLUE Gain RED Offset GREEN Offset BLUE Offset MODE 1 MODE 2 BSAMPDelay VSAMPDelay ADCLKDelay TEST
Address
A3 0 0 0 0 0 0 0 0 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 A1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 D9 msb msb msb D8 D7 D6
Data Bits
D5 D4 D3 D2 D1 lsb lsb lsb D0
COR[1] COR[0] FOR[7] FOR[6] FOR[5] FOR[4] FOR[3] FOR[2] FOR[1] FOR[0] COG[1] COG[0] FOG[7] FOG[6] FOG[5] FOG[4] FOG[3] FOG[2] FOG[1] FOG[0] COB[1] COB[0] FOB[7] FOB[6] FOB[5] FOB[4] FOB[3] FOB[2] FOB[1] FOB[0] CH[2] PD BL[4] VL[4] A[4] * CH[1] OE BL[3] VL[3] A[3] * BL[2] VL[2] A[2] * BL[1] VL[1] A[1] * BL[0] VL[0] A[0] * BT[4] VT[4] DO[4] * CH[0] GS LC CCDEN B/N Lpol BT[3] VT[3] DO[3] * C/R[2] ADCpol BT[2] VT[2] DO[2] * C/R[1] Bpol BT[1] VT[1] DO[1] * C/R[0] Vpol BT[0] VT[0] DO[0] *
RESET/RB
1
1
1
1
Reset
READ
RB[3]
RB[2]
RB[1]
RB[0]
Note:
* Exar test bits, do not over write the default values. Shaded cells represent unused bits.
3.1
PGA Gain Registers
There are three PGA registers for individually programming the gain in the RED, GREEN, and BLUE channels. Each gain register has 9 bits of resolution. Bits D[9:1] control the gain while bit D0 is N/A (don't care). The XRD9818 has two gain ranges to help interface to imagers that have 3V or 2V of output signal swing. The GS bit, located in the MODE 1 register, defaults to GS=0 for a gain of 1x to 5x or if GS=1 the gain would be 1.5x to 7.5x. The gain range of 1 to 5x (GS=0) is intended for use with imagers that have a 3V output swing, while the gain range 1.5 to 7.5x is intended for imagers with 2V or less of output swing. The coding for the PGA registers is straight binary. See "Section 4.3, Programmable Gain" on page 20 for a functional description of the XRD9818's gain stage.
GAIN REGISTER SETTINGS
D9
msb
D8
D7
D6
D5
D4
D3
D2
D1
lsb
D0
N/A not used
Gain (V/V)
w/GS bit = 0*
1x ... 5x
Gain (V/V)
w/GS bit = 1
1.5x ... 7.5x
000000000* ... 111111111 * Power-on default value
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3.2
Offset Registers
There are three Offset registers for individual control of the offsets applied to the RED, GREEN, and BLUE channels. There are separate course and fine controls to set the desired offset compensation for each channel. Bits D9 and D8 set the course offset from -100mV to +200mV in 100mV increments. Bits D7:D0 set the fine offset range from -180mV to +180mV in 1.4mV increments. The polarity of the offset correction is defined as positive for the normal direction in which offsets occur in an imager, see Figure 11. Please see "Section 4.2, Programmable Offset Adjust" on page 19 for a description of the XRD9818's offset correction circuitry.
OFFSET REGISTER SETTINGS
D9
COx[1]
D8
COx[0]
D7
FOx[7]
D6
FOx[6]
D5
FOx[5]
D4
FOx[4]
D3
FOx[3]
D2
FOx[2]
D1
FOx[1]
D0
FOx[0]
Course offset control 00* 0mV 01 -100mV 10 100mV 11 200mV * Power-on default value
Fine offset control 01111111 150mV ... 00000000* 0mV 10000000 0mV ... 11111111 -150mV
3.3
Mode Registers
There are two mode registers that control the configuration and operation of the XRD9818. The Mode 1 register controls the configuration of input mux mode, gain range, Line Clamp enable, CCD or CIS select, byte or nibble data output mode and clamp level select. The Mode 2 register controls the power down, output enable and polarities of the input timing signals.
MODE 1 REGISTER SETTINGS
D9
CH[2]
D8
CH[1]
D7
CH[0]
D6
GS
0* 1x to 5x 1 1.5x to 7.5x
D5
LC
0* Line Clamp Off 1 Line Clamp On
D4
CCDEN
0* CCD 1 CIS
D3
B/N
0 byte output mode 1* nibble output mode
D2
C/R[2]
D1
C/R[1]
000 high Z 001 0V 010 1.25V 011 2.0V 100 2.6V 101 2.8V 110* 3.0V 111 VDD
D0
C/R[0]
000* 3CH (RGB) 001 RED channel 010 GRN channel 011 BLU channel 100 2CH (RG) 101 2CH (GR) 110 2CH (GB) 111 2CH (BR) * Power-on default value
CH[2:0] - Input Mux/Channel select. Selects between 3-CH (RGB), 1-CH RED, 1-CH GRN, 1-CH BLU, 2-CH (RG), 2-CH (GR), 2-CH (GB) or 2-CH (BR) input mux modes. GS - Gain Range Select. Gain range 1x to 5x for 3V input signals, range 1.5x to 7.5x for 2V signals. LC- Line Clamp enable. Gates clamping function with the timing signal LCLMP. CCDEN - CCD enable. Defines operation for a CCD or CIS imager input. B/N - Byte or Nibble output mode. Defines 8bit (byte) or 4bit (nibble) data output format. C/R[2:0] - Clamp/Reference Select. The setting determines the clamp/reference voltage applied to the CMN- input. The settings 2.0V through VDD are intended for use in CCD applications. The 0V, 1.25V or "high Z" settings are intended for use for CIS applications. If "high Z" is selected an external source can be applied to CMN- for the reference. For a description of the C/R DAC please See "Section 4.1.2, Clamp/Reference (C/R) DAC" on page 17.
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XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
REV. 1.0.1
MODE 2 REGISTER SETTINGS
D9
PD
0* Normal Operation 1 PWR Down
D8
OE
0* Normal Operation 1 Data bus tri-stated
D7
N/A
Not used
D6
N/A
Not used
D5
N/A
Not used
D4
N/A
Not used
D3
LPOL
0* NonInverted 1 Inverted
D2
ADCPOL
0* NonInverted 1 Inverted
D1
BPOL
0* NonInverted 1 Inverted
D0
VPOL
0* NonInverted 1 Inverted
* Power-on default lt value
PD - Power Down. Does not affect the internal register settings but does power down the entire part excluding the serial interface. There will be some power up settling time required to reestablish the ADC reference, CAPP and CAPN, voltages. OE - Output Enable. Tristate control for the output data bus. LPOL - LCLMP input polarity select. (Noninverting pol active high, inverted pol active low) ADCPOL - ADCLK polarity select. (Noninverting pol begins high, inverted pol begins low) BPOL - BSAMP polarity select. (Noninverting pol active high, inverted pol active low) VPOL - VSAMP polarity select. (Noninverting pol active high, inverted pol active low) 3.4 BSAMP Delay Register
The BSAMP Delay register controls the internal delays added to the leading and the trailing edges of the BSAMP timing signal. The width and position of the BSAMP pulse can be adjusted through the leading and trailing edge delay settings. This is useful to match the sampling requirements of the incoming CCD waveform.
BSAMP DELAY REGISTER SETTINGS
D9
BL[4]
D8
BL[3]
D7
BL[2]
D6
BL[1]
D5
BL[0]
D4
BT[4]
D3
BT[3]
D2
BT[2]
D1
BT[1]
D0
BT[0]
BSAMP Leading edge delay 00000* 0ns 00001 1ns ... 11110 30ns 11111 31ns * Power-on default value
BSAMP Trailing edge delay 00000* 0ns 00001 1ns ... 11110 30ns 11111 31ns
BL[4:0] - Sets the amount of delay added to the leading edge of BSAMP. BT[4:0] - Sets the amount of delay added to the trailing edge of BSAMP.
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3.5
VSAMP Delay Register
The VSAMP Delay register controls the internal delays added to the leading and the trailing edges of the VSAMP timing signal. The width and position of the VSAMP pulse can be adjusted through the leading and trailing edge delay settings. This is useful to match the sampling requirements of the incoming CCD/CIS waveform.
VSAMP DELAY REGISTER SETTINGS D9 VL[4] D8 VL[3] D7 VL[2] D6 VL[1] D5 VL[0] D4 VT[4] D3 VT[3] D2 VT[2] D1 VT[1] D0 VT[0]
VSAMP Leading edge delay 00000* 0ns 00001 1ns ... 11110 30ns 11111 31ns * Power-on default value
VSAMP Trailing edge delay 00000* 0ns 00001 1ns ... 11110 30ns 11111 31ns
VL[4:0] - Sets the amount of delay added to the leading edge of VSAMP. VT[4:0] - Sets the amount of delay added to the trailing edge of VSAMP. 3.6 ADCLK Delay Register
The ADCLK Delay register controls the delay added to the ADCLK timing signal and Data Output.
ADCLK DELAY REGISTER SETTINGS
D9
A[4]
D8
A[3]
D7
A[2]
ADCLK delay 00000* 0ns 00001 1ns ... 11110 30ns 11111 31ns
D6
A[1]
D5
A[0]
D4
DO[4]
D3
DO[3]
D2
DO[2]
Output Data valid delay 00000* 0ns 00001 0.5ns ... 11110 15.0ns 11111 15.5ns
D1
DO[1]
D0
DO[0]
* Power-on default value
A[4:0] - Sets the amount of internal delay added to the ADCLK signal. DO[4:0] - Sets the amount of delay from internal ADCLK to valid data out. 3.7 Test Register
The TEST register is used for EXAR internal test requirements. Do not over write this register.
TEST REGISTER SETTINGS
D9
Test Only
D8
Test Only
D7
Test Only
D6
Test Only
D5
Test Only
D4
Test Only
D3
Test Only
D2
Test Only
D1
Test Only
D0
Test Only
00000000* Do not modify * Power-on default value
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XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
REV. 1.0.1
Reset and ReadBack Register
This register controls the reset and readback function of the XRD9818. The part can be reset to its power-up default state by writing to the RESET bit. This will reset all register contents to their default state, reset the serial port contents and counters and configure the input mux to the red input channel. The XRD9818 will automatically recover approximately 10ns after the RESET bit is set high. After the reset recovery the register contents will be reset to their default conditions and the RESET bit will be set back to a low. The readback function is controlled through this register also. The READ bit simply enables the readback function. When the READ bit is set high the contents of the register pointed to by the address in RB[3:0] is put out on the data output bus. The register contents are output to the 10 LSB's and the 6 MSB's are padded with zeros. The output data format is set to either Byte or Nibble format as controlled by the B/N bit (D3) in the MODE 1 register. The register contents will continually be output to the data bus until the readback bit is set low. RESET/READBACK REGISTER
D9 Reset D8 Read D7 N/A
Not used
D6 N/A
Not used
D5 N/A
Not used
D4 N/A
Not used
D3 RB[3]
D2 RB[2]
D1 RB[1]
D0 RB[0]
0* Normal Oper- 0* Normal Operation ation 1 Reset Device 1 Readback Enabled
Address of register to be read 0000* RED Gain register 0001 GREEN Gain register ... 1111 RESET/RB register
* Power-on default value
Reset - Returns all internal register values back to their default settings. Read - Readback enable. RB[3:0] - Readback register address. Points to the internal register of interest to be read.
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XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
REV. 1.0.1
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4.0 CIRCUIT OPERATION 4.1 4.1.1 Analog Inputs Sampling
The XRD9818's analog front end (AFE) uses a switched capacitor network to achieve a correlated double sample (CDS) of the input in CCD mode or a sample and hold (S/H) of the input in CIS mode. Figure 3 shows the 9818's AFE (CDS/SH + PGA) which samples and gains the input signal. Figure 4 shows the external and internal timing requirements to achieve a correlated double sample and gain of a CCD input signal. FIGURE 3. XRD9818 INPUT CIRCUITRY
B
SW4 SW8
V
Input SW1 Reference
SW2
R
C3 C1
SW6
V
C7 C5 to ADC
CL
SW3
C2
C6 SW7 C4
R
V
C8
SW5
B
SW9
V
C1 = C2 = 7.5pf C3 = C4 = 7.5pf or 11pf C5 = C6 = 1.5pf or 7.89pf C7 = C8 = 1pf
In addition to sampling and gaining the CCD signal the 9818 input is designed to reject the reset pulse noise present also. The XRD9818 can withstand reset pulses up to 1.5V or more depending upon the input conditions. The timing signal R controls SW2 and SW3 is generated internally by the XRD9818. SW2 and SW3 open after a short delay following the sampling edge of VSAMP and close at the leading edge of BSAMP. FIGURE 4. INTERNAL AFE SAMPLE TIMING (EX. 3CH CCD MODE)
CCDIN
ADCLK byte ADCLK nibble BSAMP VSAMP
R
B V
Note :
V = ADCLK VSAMP
The XRD9818 utilizes a differential input and signal path which samples the CCD reference level on capacitors C1 and C2. When B goes high, SW4 and SW5 close storing the CCD reference level on C1 and C2. When B goes low a fixed gain is applied to the input signal as it tracks the video input. When V goes high the video content is applied to capacitors C5 and C6. The final video level is stored on C5 and C6 when V goes low. The video content is then amplified again and sampled by the ADC at the proper time
16
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XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
REV. 1.0.1
4.1.2 4.1.2.1
Clamp/Reference (C/R) DAC Clamp Operation in CCD Mode
In CCD mode a clamp is required to level shift the CCD output signal into XRD9818's input common mode range. The clamp circuitry ensures that the signals present at the analog inputs fall within the operating range of those pins. The clamp operation takes place while BSAMP is active. When BSAMP is active, SW1 is closed connecting the C/R DAC to the analog input pin. This establishes the C/R DAC voltage on the external coupling cap. When SW1 is opened, the C/R DAC voltage is stored on the external coupling cap. This clamping operation will occur while BSAMP is active. The C/R DAC clamp voltage is programmable. This gives the system designer added flexibility to make adjustments for different sensor signal swing and reset pulse characteristics. FIGURE 5. CCD MODE INPUT CLAMP (ALL THREE CHANNELS ARE IDENTICAL)
CCD ouput
CIN
RED+ SW2 RED+ SW1
R CL R
C1 to PGA C2
1nf
CREF 0.1uf
CMN-
SW3
C/R DAC
CL[2] CL[1] CL[0]
Clamp/Reference DAC
The XRD9818 has 2 clamp modes available for used in CCD applications, Line Clamp and Pixel Clamp. Line Clamp mode only performs the clamp when the LCLMP pin is active. The control timing, CL, for SW1 is generated by the "ANDing" of the external timing signals LCLMP & BSAMP and is shown in Figure 6. FIGURE 6. LINE CLAMP MODE TIMING
CCDIN
ADCLK
BSAMP
VSAMP
LCLMP
CL
17
XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
REV. 1.0.1
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Pixel Clamp mode eliminates the gating function of BSAMP with LCLMP. In Pixel Clamp mode the clamping function is performed with every BSAMP, see Figure 7. Selection of the Line Clamp or Pixel Clamp modes is defined by the state of the LC bit (D5) located in the MODE 1 register. FIGURE 7. PIXEL CLAMP MODE TIMING
CCDIN
ADCLK
BSAMP
VSAMP
CL
4.1.2.2
Reference Operation in CIS Mode
In most CIS applications the imager output is connected directly to the inputs. With no external coupling capacitor, there is no need to perform a clamp. Unlike a CCD output signal that has a black reference level for each pixel a CIS output is sampled with respect to a black reference voltage. In CIS mode, the C/R DAC is used to provide that reference as shown below in Figure 8. The reference voltage is programmable to help interface to a variety of CIS imagers. If a CIS imager provides its own reference voltage the C/R DAC can be configured into a "high Z" state so that an external reference can be connected directly to the CMN- pin. See the MODE 1 Register definition of bits C/R[2:0].
FIGURE 8. CIS MODE REFERENCE (INTERNAL OR EXTERNAL)
CIS Signal
C1 to PGA C2 0.1uf CMNCL[2] CL[1] CL[0]
C/R DAC
Clamp/Reference DAC
18
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4.2
XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
REV. 1.0.1
Programmable Offset Adjust
The offset adjustment circuitry of the XRD9818 is designed to compensate for any offsets present in the CCD or CIS output signal and/or overall scanner system. The total range of compensation available is -280mV to +380mV. This is achieved via a 10-bit Offset DAC that applies gain independent offset correction. The 10-bits of control is broken into 2 ranges, course and fine. There are 2 bits of course control that is designed to remove offsets in 100mV increments. The remaining 8-bits determine the fine control and has a range of +/-180mV in 1.4mV increments. Each channel has its own independent offset control. FIGURE 9. XRD9818 CHANNEL OFFSET BLOCK DIAGRAM
VA
9-Bit PGA
VB
Input
CDS SH
16-Bit 3:1 MUX
ADC
Programmable Serial Port
8-Bit
8-Bit Offset DAC Fine Adjust
2-Bit
2-Bit Offset Course Adjust
Offset Block
The offset correction range of both the Course and Fine DAC's are shown in Figure 10. The Course DAC has four settings: 0mv, -100mV, 100mV and 200mV. The 2 msb's, D[9:8], select the desired course offset setting. The Fine DAC has a range of +/-180mV. The Offset registers 8 lsb's, D[7:0], select the desired fine setting. Bits D[6:0] program the magnitude while D[7] selects the polarity of the Fine DAC's compensation. FIGURE 10. OFFSET CORRECTION (COURSE & FINE DAC'S)
Course DAC Settings
COx[1:0] 00 01 10 11 Offset (mV) 0 -100 100 200
150mV 10h Fine DAC Range 00h 0Fh -150mV FFh
Code
As can be seen in the Course Offset DAC's range settings there is more correction range in the positive direction. This allows the system designer to maximize the usable offset correction range of the XRD9818 for a variety of imagers. Positive offset is defined as the normal offset direction found in either a CCD or CIS input signal, as shown in Figure 11. FIGURE 11. SIGNAL OFFSET POLARITY (CCD AND CIS)
CCD
Negative Offset Positive Offset
C IS
Ideal Black CCD Dark Offset
W hite
S ig n a l S ig n a l
W hite Positive Offset Negative Offset Ideal Black
19
XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
REV. 1.0.1
xr
The affect of the XRD9818's offset correction DAC's (Course & Fine) is defined as follows:
VA = VInput - (VOSCourse + VOSFine )
note: positive offset values subtract from the input signal
The course DAC value, VOSCOURSE, is defined in Figure 10 and the Fine DAC value is determined as follows: VOSFine = FBx[7]
Offset Code (FBx[6:0]) 150mV 127
Note : FB[7] = 0 -> (+), FB[7] = 1 -> (-)
The XRD9818 offset adjustment range is designed to maximize the correction range whether being used in a CCD or CIS application. 4.3 Programmable Gain
There are three independent PGA's, one for each input channel: Red, Green and Blue. The individual gain values are controlled by separate Red, Green and Blue gain registers. Each PGA has 9 bits of control for the full gain range. See Figure 12 for the PGA transfer function. The gain increments in a binary fashion from a minimum at code 0 to a maximum at code 511. The PGA has two gain ranges 1x to 5x and 1.5x to 7.5x to help interface to imagers with 3V or 2V outputs respectively. To select the 1x to 5x gain range for an imager that has a 3V single swing the GS bit in the MODE 1 register must be set low, GS=0 (default). To select the 1.5x to 7.5x gain range for use with imagers that have a 2V maximum signal swing the GS bit in the MODE 1 register must be set high, GS=1. FIGURE 12. XRD9818 PGA TRANSFER FUNCTION
8 7 6 Gain (V/V) 5 4 3 2 1 0 0 64 128 192 256 320 384 448 512 PGA Gain Code GS=1 GS=0
The XRD9818 channel gain equations are as follows:
Gain Code 511
G a in 1 to 5 = 4
1
or
G a in 1.5 to 7.5 = 6.0
Gain Code 511
1.5
20
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5.0 SERIAL PORT INTERFACE
XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
REV. 1.0.1
The XRD9818 can be configured through a three pin interface (LOAD, SDI, and SCLK) with the serial port write timing shown below. Each write will include 4 bits of address, two dummy bits and 10 bits of data. To insure a valid write operation, the serial port control must detect minimum of 16 rising SCLK edges. Upon a valid write the XRD9818 will latch the last 16 bits of data presented at the rising edge of LOAD. The register address will be decoded and the 10bits of data will over write the contents of the addressed register. The LOAD setup time "Tls" can be indefinitely long.
FIGURE 13. SERIAL PORT WRITE TIMING
Tls Tds
LOAD SCLK
msb lsb A2 A1 A0 E0 msb D9 D8 D7 D6 D5
Tsclk Tlh Tdh
Tlpw
lsb D4 D3 D2 D1 D0
SDI
E1
A3
D u m m y
Register Address
D u m m y
Write Register Data
LOAD is used to gate the SCLK input into the XRD9818. In order to eliminate any unintended high speed clocks into the part it is recommended that the LOAD signal only be active during the write operation. FIGURE 14. LOAD GATING OF SCLK
LOAD SCLK SCLK (internal)
21
XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
REV. 1.0.1
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6.0 TIMING FIGURE 15. 3-CH CCD MODE SYSTEM TIMING (BYTE & NIBBLE MODES)
Pixel (n) Pixel (n+3) Pixel (n+4)
tcr3 tap
CCDIN
tcp3b
.....
tap
ADCLK BYTE
tcp3n
..... ..... .....
tvfcr
ADCLK NIBBLE
BSAMP
tstl
VSAMP OUTPUT DATA ADCO(7:0) BYTE OUTPUT DATA ADCO(7:4) NIBBLE BYTE Mode A=> Red (DB15-DB8) B=> Red (DB7-DB0) C=> GRN (DB15-DB8)
.....
todv
.....
todv
An
Bn
Cn
Dn
En
Fn
.....
NIBBLE Mode a=> RED (DB15-DB12) b=> RED (DB11-DB8) c=> RED (DB7-DB4) d=> RED (DB3-DB0)
an bn cn dn en fn gn hn in jn kn ln
D=> GRN (DB7-DB0) E=> BLU (DB15-DB8) F=> BLU (DB7-DB0)
e=> GRN (DB15-DB12) f=> GRN(DB11-DB8) g=> GRN (DB7-DB4) h=> GRN (DB3-DB0)
i=> BLU (DB15-DB12) j=> BLU (DB11-DB8) k=> BLU (DB7-DB4) l=> BLU (DB3-DB0)
FIGURE 16. 2-CH CCD MODE SYSTEM TIMING (BYTE & NIBBLE MODES)
Pixel (n) Pixel (n+5) Pixel (n+6)
tcr2 tap
CCDIN
tcp2b
.....
tap
ADCLKBYTE
tcp2n
..... .....
tvfcr
ADCLKNIBBLE
BSAMP
.....
tstl
VSAMP OUTPUT DATA ADCO(7:0)BYTE OUTPUT DATA ADCO(7:4)NIBBLE BYTE Mode An=> 1ST CH (DB15-DB8) Bn=> 1ST CH (DB7-DB0) Cn=> 2ND CH (DB15-DB8) Dn=> 2ND CH (DB7-DB0)
.....
todv
..... .....
a
An
todv
n
Bn
Cn
Dn
bn
cn
dn
en
fn
gn hn
NIBBLE Mode a=> 1ST CH (DB15-DB12) b=> 1ST CH (DB11-DB8) c=> 1ST CH (DB7-DB4) d=> 1ST CH (DB3-DB0)
e=> 2ND CH (DB15-DB12) f=> 2ND CH (DB11-DB8) g=> 2ND CH (DB7-DB4) h=> 2ND CH (DB3-DB0)
22
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XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
REV. 1.0.1
FIGURE 17. 1-CH CCD MODE SYSTEM TIMING (BYTE & NIBBLE MODES)
Pixel (n) Pixel (n+9) Pixel (n+10)
tcr1 tap
CCDIN
tcp1b
.....
tap
ADCLKBYTE
tcp1n
..... .....
tvfcr
ADCLK
BSAMP
.....
tstl
VSAMP OUTPUT DATA ADCO(7:0)BYTE OUTPUT DATA ADCO(7:4)NIBBLE BYTE Mode MSB =>DB(15:8) LSB =>DB(7:0)
.....
todv
..... .....
MSB (n-1)
LSB (n-1)
todv
MSB (n)
LSB (n)
MSB(n+1)
An
Bn
Cn
Dn
NIBBLE Mode A=> DB15-DB12 B=> DB11-DB8 C=> DB7-DB4 D=> DB3-DB0
FIGURE 18. 3-CH CIS MODE SYSTEM TIMING (BYTE & NIBBLE MODES)
Pixel (n) Pixel (n+3) Pixel (n+4)
tcr3 tap tcp3b
CISIN
.....
ADCLK BYTE
tcp3n
.....
tvfcr
ADCLK NIBBLE
.....
tstl
VSAMP OUTPUT DATA ADCO(7:0) BYTE OUTPUT DATA ADCO(7:4) NIBBLE BYTE Mode A=> Red (DB15-DB8) B=> Red (DB7-DB0) C=> GRN (DB15-DB8)
.....
todv
.....
todv
An
Bn
Cn
Dn
En
Fn
.....
NIBBLE Mode a=> RED (DB15-DB12) b=> RED (DB11-DB8) c=> RED (DB7-DB4) d=> RED (DB3-DB0)
an bn cn dn en fn gn hn in jn kn ln
D=> GRN (DB7-DB0) E=> BLU (DB15-DB8) F=> BLU (DB7-DB0)
e=> GRN (DB15-DB12) f=> GRN(DB11-DB8) g=> GRN (DB7-DB4) h=> GRN (DB3-DB0)
i=> BLU (DB15-DB12) j=> BLU (DB11-DB8) k=> BLU (DB7-DB4) l=> BLU (DB3-DB0)
23
XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
REV. 1.0.1
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7.0 APPLICATION HOOK-UP DIAGRAMS
FIGURE 19. TYPICAL HOOK-UP DIAGRAM FOR THE XRD9818 (AC COUPLED, CCD EXAMPLE)
15V
AVDD DVDD
1nf CCD 1nf
RED+
GRN+
AA VV DD DD
1nf
BLU+
D V D ADCO7 D ADCO6 ADCO5 ADCO4 ADCO3 ADCO2 ADCO1 ADCO0
ADC OUTPUT BUS
0.1uf
CMN-
9818
CAPP 0.1uf 2.2uf 2.2uf CAPN 0.1uf CMREF 2.2uf
TG (timing generator)
ADCLK VSAMP BSAMP LCMP LOAD SCLK SDI A G N D A G N D D G N D
0.1uf
2.2uf
0.1uf
0.1uf
It is recommended that each power pin be 1uf decoupled to ground with capacitors placed as close to power pin as possible.
ASIC
24
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8.0 PERFORMANCE DATA
XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
REV. 1.0.1
FIGURE 20. SYSTEM DNL, 3-CH OPERATION
9818 System 3CH DNL
1 0.8 0.6 0.4 0.2 Dnl (lsb) 0 -0.2 -0.4 -0.6 -0.8 -1 0 8192 16384 24576 32768 Code 40960 49152 57344 65536
FIGURE 21. XRD9818 IDD VS TEMPERATURE
XRD9818 IDD vs Temperture
70
60
50
IDD (mA)
40
IAVDD IDVDD IDDTOT
30
20
10
0 -40 -30 -20 -10 0 10 20 Temp 30 40 50 60 70 80
25
XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
REV. 1.0.1
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FIGURE 22. XRD9818 REFERENCE VS TEMPERATURE
XRD9818 Reference vs Temperture
2.5
2
Voltage (V)
1.5
CAPP CAPN CAPP-CAPN VCM
1
0.5
0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperture (C)
26
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PACKAGE DIMENSIONS
XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
REV. 1.0.1
28 LEAD THIN SHRINK SMALL OUTLINE (4.4mm TSSOP)
Rev. 2.00
D
28 15
E1 E
1 Seating Plane
14
C A2
A
L
e
B
A1
SYMBOL A A1 A2 B C D E E1 e L
INCHES MIN MAX 0.033 0.047 0.002 0.006 0.031 0.041 0.007 0.012 0.004 0.008 0.378 0.386 0.248 0.260 0.169 0.177 0.0256 BSC 0.018 0.030 0 8
MILLIMETERS MIN MAX 0.85 1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 9.60 9.80 6.30 6.60 4.30 4.50 0.65 BSC 0.45 0.75 0 8
Note: The control dimension is in millimeter column
27
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XRD9818 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
REV. 1.0.1
REVISION HISTORY
Revision # A1.0.0 A1.0.1 A1.1.0 A1.2.0 A1.3.0 Date 08/20/02 09/26/02 10/17/02 11/13/02 1/30/03 Description
1st release of the XRD9818 advanced data sheet. Modified Serial Port Read/Write timing diagrams, system specs INL, IRNMIN and IRNMAX Changed definition of PGA to 9bit & overall system gain 1x to 5x, redefined serial port timing, added 3-CH & 1-CH timing diagrams for 8bit and 4bit data output modes, Added pin def, updated black diagram including VCMREF pin & removing LCLP pin, updated 8bit 1-CH timing diagram Updated pin def type for CMREF. Updated serial port timing diagram. Added input signal swing, reset pulse, Load pulse width and PGA spec's to elec tables. Added register map & bit definitions. Remove IB spec from CDS-S/H Specifications. Changed data sheet to Preliminary status. Added timing diagrams, functional descriptions and electrical table updates to reflect part performance. Released version. Updated electrical tables & document with char data, some minor text edits to advance description, added performace data and application hook-up diagram.
P1.0.0 1.0.0
11/14/03 1/29/04
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2000 EXAR Corporation Datasheet June 2004.
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