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V436664Z24V 512MB 144-PIN UNBUFFERED SDRAM SODIMM, 64M x 64 3.3 VOLT
PRELIMINARY
Features
JEDEC-standard 144 pin, Small-Outline, Dual in line Memory Module (SODIMM) Serial Presence Detect with E2PROM Nonbuffered Fully Synchronous, All Signals Registered on Positive Edge of System Clock Single +3.3V ( 0.3V) Power Supply All Device Pins are LVTTL Compatible 8192 Refresh Cycles every 64 ms Self-Refresh Mode Internal Pipelined Operation; Column Address can be changed every System Clock Programmable Burst Lengths: 1, 2, 4, 8 Auto Precharge and Piecharge all Banks by A10 Data Mask Function by DQM Mode Register Set Programming Programmable (CAS Latency: 2, 3 Clocks) SOC and WBGA component packaging
CILETIV LESO M
32M x 8
Description
The V436664Z24V memory module is organized 67,108,864 x 64 bits in a 144 pin SODIMM. The 64M x 64 memory module uses 16 Mosel-Vitelic 32M x 8 SDRAM. The x64 modules are ideal for use in high performance computer systems where increased memory density and fast access times are required.
Speed Grade
-75PC, CL=2,3 (133 MHz) -75, CL=3 (133 MHz) -10PC, CL=2 (100 MHz)
Part Number
V436664Z24VXXG-75PC
Configuration
64M x 64
V436664Z24VXXG-75
64M x 64
V436664Z24VXXG-10PC
64M x 64
32M x 8
32M x 8
32M x 8
1
59
61
143
Pin 2 on Backside
Pin 144 on Backside
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Front DQMB1 DQMB5 VDD VDD A0 A3 A1 A4 A2 A5 VSS VSS DQ8 DQ40 DQ9 DQ41 DQ10 DQ42 DQ11 DQ43 VDD VDD DQ12 DQ44 Pin 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Front DQ13 DQ45 DQ14 DQ46 DQ15 DQ47 VSS VSS NC NC NC NC CLK0 CKE0 VDD VDD RAS CAS WE CKE1 CS0 A12 CS1 NC Pin 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Back NC CLK1 VSS VSS NC NC NC NC VDD VDD DQ16 DQ48 DQ17 DQ49 DQ18 DQ50 DQ19 DQ51 VSS VSS DQ20 DQ52 DQ21 DQ53 Pin 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Back DQ22 DQ54 DQ23 DQ55 VDD VDD A6 A7 A8 BA0 VSS VSS A9 BA1 A10 A11 VDD VDD DQMB2 DQMB6 DQMB3 DQMB7 VSS VSS Pin 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Back DQ24 DQ56 DQ25 DQ57 DQ26 DQ58 DQ27 DQ59 VDD VDD DQ28 DQ60 DQ29 DQ61 DQ30 DQ62 DQ31 DQ63 VSS VSS SDA SCL VDD VDD
CILETIV LESO M
Pin Configurations (Front Side/Back Side)
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Front VSS VSS DQ0 DQ32 DQ1 DQ33 DQ2 DQ34 DQ3 DQ35 VDD VDD DQ4 DQ36 DQ5 DQ37 DQ6 DQ38 DQ7 DQ39 VSS VSS DQMB0 DQMB4 Pin 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Note:
1. RAS, CAS, WE CASx, CSx are active low signals.
Pin Names
A0-A12, BA0, BA1 DQ0-DQ63 RAS CAS WE CS0, CS1 DQMB0-DQMB7 CKE0, CKE1 CLK0, CLK1 SDA SCL VDD VSS NC Address, Bank Select Data Inputs/Outputs Row Address Strobes Column Address Strobes Write Enable Chip Select Output Enable Clock Enable Clock Serial Input/Output Serial Clock Power Supply Ground No Connect (Open)
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Part Number Information
V
MOSEL VITELIC MANUFACTURED
4
3
66
64
Z
2
4
V
X
X
G - XX
SDRAM 3.3V WIDTH DEPTH 144 PIN SODIMM X8 COMPONENT REFRESH RATE 8K
SPEED 75PC = PC133 CL2,3 75 = PC133 CL3 10PC = PC100 CL2
LEAD FINISH G = GOLD COMPONENT PACKAGE S=SOC, B=WBGA COMPONENT REV LEVEL A=0.17u, B=0.14u LVTTL 4 BANKS
Block Diagram
Block Diagram
CS0 CS1 CS0 CS0
DQM0 I/O1-I/O8 10 DQM1 I/O9-I/O16 10
CS1 CS3 CS1 CS2
DQM CS I/O1-I/O8 D0 DQM CS I/O1-I/O8 D1
DQM CS I/O1-I/O8 D8 DQM CS I/O1-I/O8 D9
DQM4 I/O33-I/O40 10 DQM5 I/O41-I/O48 10
DQM CS I/O1-I/O8 D4 DQM CS I/O1-I/O8 D5
DQM CS I/O1-I/O8 D12 DQM CS I/O1-I/O8 D13
DQM2 I/O17-I/O24 10 DQM3 I/O25-I/O32 10
CS DQM I/O1-I/O8 D2 DQM I/O1-I/O8 CS D3
CS DQM I/O1-I/O8 D10 DQM I/O1-I/O8 D11 CS
DQM6 I/O49-I/O56 10 DQM7 I/O57-I/O64 10
CS DQM I/O1-I/O8 D6 CS DQM I/O1-I/O8 D7
CS DQM I/O1-I/O8 D14 CS DQM I/O1-I/O8 D15
E2PROM SPD (256 WORD X 8 BIT) SA0 SA1 SA2 SCL SA0 SA1 SA2 SCL SDA
A12-A0, BA0, BA1 VDD C0-C31
D0-D15 D0-D15 D0-D7 D0-D15 D0-D7 VCC 10K
WP
47K
VSS RAS, CAS, WE CKE0
CLOCK WIRING CLK0 CLK1 CLK2 CLK3 16M X 64 84 SDRAM +3.3pF SDRAMS +3.3pF 8 4 SDRAM +3.3pF SDRAMS +3.3pF 4 SDRAM +3.3pF 4 SDRAM +3.3pF
CKE1
D9-D15
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E2PROM device during module production using a serial presence detect protocol (I2C synchronous 2-wire bus)
A serial presence detect storage device - E2PROM is assembled onto the module. Information about the module configuration, speed, etc. is written into the
CILETIV LESO M
Serial Presence Detect Information
SPD-Table for modules:
Byte Number
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Hex Value Function Described
Number of SPD bytes Total bytes in Serial PD Memory Type Number of Row Addresses (without BS bits) Number of Column Addresses (for x8 SDRAM) Number of DIMM Banks Module Data Width Module Data Width (continued) Module Interface Levels SDRAM Cycle Time at CL=3 SDRAM Access Time from Clock at CL=3 Dimm Config (Error Det/Corr.) Refresh Rate/Type SDRAM width, Primary Error Checking SDRAM Data Width Minimum Clock Delay from Back to Back Random Column Address Burst Length Supported Number of SDRAM Banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM Module Attributes SDRAM Device Attributes: General Minimum Clock Cycle Time at CAS Latency = 2
SPD Entry Value
128 256 SDRAM 13 10 2 64 0 LVTTL 7.5 ns/10.0 ns 5.4 ns/10.0ns none Self-Refresh, 7.8 s x8 n/a / x8 tccd = 1 CLK 1, 2, 4 & 8 4 CL = 2 / 3 CS Latency = 0 WL = 0 Non Buffered/Non Reg. Vcc tol 10% 7.5 ns/10.0 ns
-75PC
80 08 04 0D 0A 02 40 00 01 75 54 00 82 08 00 01
-75
80 08 04 0D 0A 02 40 00 01 75 54 00 82 08 00 01
-10PC
80 08 04 0D 0A 02 40 00 01 A0 60 00 82 08 00 01
16 17 18 19 20 21 22 23
0F 04 06 01 01 00 0E 75
0F 04 06 01 01 00 0E A0
0F 04 06 01 01 00 0E A0
24
Maximum Data Access Time from Clock for CL =2 Minimum Clock Cycle Time at CL = 1 Maximum Data Access Time from Clock at CL =1 Minimum Row Precharge Time Minimum Row Active to Row Active Delay tRRD
5.4 ns/6.0 ns
54
60
60
25 26
Not Supported Not Supported
00 00
00 00
00 00
27 28
15 ns / 20 ns 14 ns/15 ns/16 ns
0F 0E
14 0F
14 10
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SPD-Table for modules: (Continued)
Byte Number
29 30 31 64 33 34 35 62-61 62 63 64 65-71 72 73-90 91-92 93 94 95-98
Hex Value Function Described
Minimum RAS to CAS Delay tRCD Minimum RAS Pulse Width tRAS Module Bank Density (Per Bank) SDRAM Input Setup Time SDRAM Input Hold Time SDRAM Data Input Setup Time SDRAM Data Input Hold Time Superset Information (May be used in Future) SPD Revision Checksum for Bytes 0 - 62 Manufacturer's JEDEC ID Code Manufacturer's JEDEC ID Code (cont.) Manufacturing Location Module Part Number (ASCII) PCB Identification Code Assembly Manufacturing Date (Year) Assembly Manufacturing Date (Week) Assembly Serial Number 1 = US, 2 = Taiwan V436664Z24V Current PCB Revision Binary Coded year (BCD) Binary Coded week (BCD) byte 95 = LSB, byte 98 = MSB 00 64 00 64 00 64 Mosel Vitelic Revision 2 / 1.2
SPD Entry Value
15 ns/20 ns 42 ns/45 ns 256 Mbyte 1.5 ns/2.0 ns 0.8 ns/ 1.0 ns 1.5 ns/2.0 ns 0.8 ns/1.0 ns
-75PC
0F 2A 40 15 08 15 08 00 02 FE 40 00
-75
14 2D 40 15 08 15 08 00 02 43 40 00
-10PC
14 2D 40 20 10 20 10 00 12 B1 40 00
99-125 126 127 128+
Reserved Intel Specification for Frequency Supported Frequency Unused Storage Location
00
00
00
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CILETIV LESO M
DC Characteristics
TA = 0C to 70C; VSS = 0 V; VDD, VDDQ = 3.3V 0.3V
Limit Values Symbol
VIH VIL V OH VOL II(L) IO(L)
Parameter
Input High Voltage Input Low Voltage Output High Voltage (IOUT = -4.0 mA) Output Low Voltage (IOUT = 4.0 mA) Input Leakage Current, any input (0 V < VIN < 3.6 V, all other inputs = 0V) Output leakage current (DQ is disabled, 0V < VOUT < VCC)
Min.
2.0 -0.5 2.4 -- -10
Max.
VCC +0.3 0.8 -- 0.4 10
Unit
V V V V A A
-10
10
Capacitance
Symbol
CI1 CI2 CICL CI3 CI4 CSC CIO
TA = 0C to 70C; VDD = 3.3V 0.3V, f = 1 MHz
Parameter
Input Capacitance (A0 to A11, RAS, CAS, WE) Input Capacitance (CS0, CSI) Input Capacitance (CLK0-CLK1) Input Capacitance (CKE0, CKEI) Input Capacitance (DQMB0-DQMB7) Input Capacitance (SCL, SA0-2) Input/Output Capacitance
Limit Values (Max.)
40 25 28 20 10 8 18
Unit
pF pF pF pF pF pF pF
Absolute Maximum Ratings
Parameter
Voltage on VDD Supply Relative to V SS Voltage on Input Relative to VSS Operating Temperature Storage Temperature Power Dissipation
Max.
-1 to 4.6 -1 to 4.6 0 to +70 -55 to 125 12.7
Units
V V C C W
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Symbol
ICC1
CILETIV LESO M
Standby and Refresh Currents1
TA = 0C to 70C, VCC = 3.3V 0.3V
Parameter
Operating Current
Test Conditions
Burst length = 4, CL = 3 tRC> = tRC(min), tCK> = tCK(min), IO = 0 mA 2 Bank Interleave Operation CKE< = VIL(max), tCK> = tCK(min) CKE> = VIH(min), tCK> = tCK(min), Input changed once in 3 cycles
75PC/75
1840
10PC
1360
Unit
mA
Note
1,2
ICC2P ICC2N
Precharged Standby Current in Power Down Mode Precharged Standby Current in Non-Power Down Mode
16
16
mA
320
240
mA
CS = High
ICC3P ICC3N ICC4
Active Standby Current in Power Down Mode
CKE< = VIL(max), tCK> = tCK(min)
160
160
mA
Active Standby Current in Non-Pow- CKE> = VIH(min), tCK> = tCK(min), Iner Down Mode put changed one time Burst Operating Current Burst length = Full Page, tRC = Infinite, CL = 3, tCK> = tCK(min), IO = 0 mA 2 Banks Activated tRC>= tRC(min) CKE = <0,2 V Standard L-Version
400
360
mA
CS = High
1200
800
mA
1, 2
ICC5 ICC6
Auto Refresh Current Self Refresh Current
3840 48 28
3520 48 28
mA mA
1,2 1,2
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CILETIV LESO M
AC Characteristics 3,4
TA = 0 to 70C; VSS = 0V; VCC = 3.3V 0.3V, tT = 1 ns
Limit Values
-75PC # Symbol Parameter Min. Max. Min.
-75 Max.
-10PC Min. Max. Unit Note
Clock and Clock Enable
1 tCK Clock Cycle Time CAS Latency = 3 CAS Latency = 2 System frequency CAS Latency = 3 CAS Latency = 2 Clock Access Time CAS Latency = 3 CAS Latency = 2 Clock High Pulse Width Clock Low Pulse Width Input Setup time Input Hold Time CKE Setup Time (Power down mode) CKE Setup Time (Self Refresh Exit) Transition time (rise and fall) 7.5 7.5 - - - - 2.5 2.5 1.5 0.8 2 8 1 133 133 5.4 6 - - - - - - - 7.5 10 - - - - 2.5 2.5 1.5 0.8 2 8 1 133 100 5.4 6 - - - - - - - 10 10 - - - - 3 3 2 1 2 8 1 100 100 6 6 - - - - - - - ns ns MHz MHz 4,5 ns ns ns ns ns ns ns ns ns 6 6 7 7 8 9
2
fCK
3
tAC
4 5 6 7 8 9 10
tCH tCL tCS tCH tCKSP tCKSR tT
Common Parameters
11 12 13 14 15 16 tRCD tRC tRAS tRP tRRD tCCD RAS to CAS delay Cycle Time Active Command Period Precharge Time Bank to Bank Delay Time CAS to CAS delay time (same bank) 15 70 42 15 14 1 - 120k - - - - 20 70 45 20 15 1 - 120k - - - - 20 70 45 20 20 1 - 120k - - - - ns ns ns ns ns CLK
Refresh Cycle
17 18 tSREX tREF Self Refresh Exit Time Refresh Period (8192 cycles) 10 64 - - 10 64 - - 10 64 - - ns ms 9 8
Read Cycle
19 20 21 22 tOH tLZ tHZ tDQZ Data Out Hold Time Data Out to Low Impedance Time Data Out to High Impedance Time DQM Data Out Disable Latency 3 0 3 2 - - 7.5 - 3 0 3 2 - - 7.5 - 3 0 3 2 - - 8 - ns ns ns CLK 10 4
Write Cycle
23 24 25 tDPL tDAL tDQW Data input to Precharge (write recovery) Data In to Active/refresh DQM Write Mask Latency 1 5 0 - - - 1 5 0 - - - 1 5 0 - - - CLK CLK CLK 11
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CILETIV LESO M
Notes:
1. The specified values are valid when addresses are changed no more than once during tCK(min.) and when No Operation commands are registered on every rising clock edge during tRC(min). Values are shown per module bank. 2. The specified values are valid when data inputs (DQ's) are stable during tRC(min.). 3. All AC characteristics are shown for device level. An initial pause of 100 s is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. 4. AC timing tests have VIL = 0.4V and V IH = 2.4V with the timing referenced to the 1.4V crossover point. The transition time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0V.
tCH 2.4V CLOCK 0.4V
+ 1.4 V 50 Ohm Z=50 Ohm I/O 50 pF
tCL
tSETUP tHOLD
tT
INPUT
1.4V
tAC tLZ tOH
tAC
I/O 50 pF
1.4V
OUTPUT
Measurement conditions for tac and toh
tHZ
5. If clock rising time is longer than 1 ns, a time (tT/2 -0.5) ns has to be added to this parameter. 6. Rated at 1.5V 7. If tT is longer than 1 ns, a time (tT -1) ns has to be added to this parameter. 8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to "wake-up" the device. 9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. 10. 11. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels. tDAL is equivalent to tDPL + tRP.
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CILETIV LESO M
Package Diagram
144 Pin SODIMM
0.039
1.25 0.787
1
59
61
143
Pin 2 on Backside
3.3V 2.661
Pin 144 on Backside
0.140 0.143
NOTE: 1. All dimensions in inches. Tolerances 0.005 unless otherwise specified.
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CILETIV LESO M
Module Label Information
Module Density
MOSEL VITELIC
Part Number Criteria of PC100 or PC133 (refer to MVI datasheet) DIMM manufacture date code
V436664Z24VXXX-XX 512MB CLX PC133U-XXX-542-A XXXX-XXXXXXX Assembly in Taiwan
CAS Latency 2=CL2 3=CL3
PC133 U -XXX
UNBUFFERED DIMM CL= 3 or 2 (CLK) tRCD= 3 or 2 (CLK) tRP= 3 or 2 (CLK)
54 2
A
Gerber file Intel PC100 x8 Based JEDEC SPD Revision 2
tAC = 5.4 ns
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WORLDWIDE OFFICES
U.S.A.
3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952
WEST
3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952
The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC.
CILETIV LESO M
TAIWAN
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(c) Copyright , MOSEL VITELIC Corp.
Printed in U.S.A.
MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications.
V436664Z24V Rev. 1.2 February 2002
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