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RMDA20420
October 2004
RMDA20420 20-42 GHz Broadband Driver Amplifier
General Description
The Fairchild Semiconductor's RMDA20420 is a broadband driver amplifier designed for use in point to point radio, point to multi-point communications, LMDS, SatCom and various communication applications. The RMDA20420 is a fully matched GaAs MMIC utilizing our advanced 0.15m gate length PHEMT process.
Features
* * * * * * Wideband 20-42GHz operation 22dB small signal gain (typ.) 23dBm saturated power output (typ.) Matched to 50 Optional bonding configuration for multiplier applications Chip Size 1.720mm x 0.760mm
Device
Absolute Ratings
Symbol Vd Vg Vdg Id Pin Tc TSTG RJC Parameter Positive DC Voltage (+3.5V Typical) Negative DC Voltage Simultaneous (Vd - Vg) Positive DC Current RF Input Power (from 50 source) Operating Baseplate Temperature Storage Temperature Range Thermal Resistance (Channel to Backside) Ratings +5 -2 +7 600 15 -40 to +85 -55 to +125 57 Units V V V mA dBm C C C/W
(c)2004 Fairchild Semiconductor Corporation
RMDA20420 Rev. D
RMDA20420
Electrical Characteristics1
Parameter Frequency Range Drain Supply Voltage (Vd) Gate Supply Voltage (Vg)2 Small Signal Gain3 (f = 20-22GHz) (f = 22-42GHz) Gain Variation vs.Frequency Power Output at 1dB Compression Power Output Saturated4 Drain Current at P1dB Compression Drain Current at Psat Input Return Loss (Pin = -20dBm) Output Return Loss (Pin = -20dBm) Min 20 2 -2 18 20 Typ 3.5 -0.6 20 22 2.5 21 23 355 362 12 10 Max 42 5 -0.15 Units GHz V V dB dB dB dBm dBm mA mA dB dB
22
Notes: 1. Operated at 25C, 50 system, Vd = +3.5V, quiescent current (Idq) = 350mA. 2. Typical range of the negative gate voltage is -0.9 to -0.15V to set typical Idq of 350mA. 3. Production measurements for small signal gain are made over a frequency range of 20 to 40GHz. 4. Saturated power measurements are not 100% tested, but guaranteed by design.
DRAIN SUPPLY (1st Stage)
DRAIN SUPPLY (2nd-4th Stages)
MMIC Chip
Vd1 Vg2 alt Vd2 Vd3 Vd4
RF IN
RF OUT
Vg1
Vg2
Vg3
Vg4
GATE SUPPLY (1st Stage)
GATE SUPPLY GROUND (2nd-4th Stages) (Back of Chip)
Figure 1. Functional Block Diagram
(c)2004 Fairchild Semiconductor Corporation
RMDA20420 Rev. D
RMDA20420
0.0130" (0.335mm)
0.0275" 0.0365" 0.0465" (0.700mm) (0.930mm) (1.180mm)
0.0575" (1.465mm) 0.0299" (0.760mm)
0.0249" (0.630mm) 0.0189" (0.480mm) 0.013" (0.330mm) 0.0185" (0.465mm) 0.0125" (0.315mm) 0.0065" (0.165mm) 0.004" (0.1mm) 0.0 0.004" (0.1mm) 0.0168" (0.430mm) 0.028" (0.715mm) 0.0475" (1.200mm) 0.0677" (1.70mm) 0.0064" (1.620mm)
0.0
Back of Chip is RF and DC Ground
Figure 2. Chip Layout and Bond Pad Locations Chip Size = 0.0677" x 0.30" x 0.002" (1720m x 760m x 50m)
10,000 pF BOND WIRE Ls
DRAIN SUPPLY (Vd) (Connect to both Vd1 & Vd3) 100 pF
MMIC Chip
Vd1 Vg2 alt Vd2 Vd3 Vd4
RF IN
RF OUT
Vg1
Vg2
Vg3
Vg4
GROUND (Back of Chip) Note: The Input does not have a DC blocking capacitor. It is terminated with a 50 resistor to ground on chip and it is isolated from any DC bias.
100 pF
BOND WIRE Ls 10,000 pF Note: For currents > 370 mA connect all four drain pads to the 100pF capacitor.
GATE SUPPLY (Vg) (VGA and/or VGB)
Figure 3. Schematic of Application Circuit
(c)2004 Fairchild Semiconductor Corporation
RMDA20420 Rev. D
RMDA20420
Vd (Positive) 5 MIL THICK ALUMINA 50 Vd1 10,000pF 100pF Vg2 alt Vd2
INTERCHANGEABLE Vd BOND PADS (Do not use Vd2) Die-Attach 80Au/20Sn Vd3 Vd4 5 MIL THICK ALUMINA 50
RF INPUT RF OUTPUT L<0.015" 4 places Vd1 2 MIL GAP 100pF Vg (Negative) INTERCHANGEABLE Vg BOND PADS L<0.015" 10,000pF Vg2 Vg3 Vg4
Notes: 1. Die-attach with 80Au/20Sn. 2. Use 0.003" x 0.0005" gold ribbon for bonding. 3. RF input and output bonds should be less than 0.015" long with stress relief. 4. For currents > 370 mA connect all drain pads (Vd1, Vd3, & Vd4) to the 100 pF capacitor. 5. Back of chip is DC and RF ground. 6. Do not use Vd2 pad for drain bias connection.
Figure 4. Recommended Assembly and Bonding Diagram
Recommended Procedure (for biasing and operation)
CAUTION: LOSS OF GATE VOLTAGE (Vg) WHILE DRAIN VOLTAGE (Vd) IS PRESENT CAN DAMAGE THE AMPLIFIER. The following sequence must be followed to properly test the amplifier: Step 1: Turn off RF input power. Step 2: Connect the DC supply grounds to the ground of the chip carrier. Slowly apply negative gate bias supply voltage of -1.5V to Vg. Step 3: Slowly apply positive drain bias supply voltage of +3.5V to Vd. Step 4: Adjust gate bias voltage to set the quiescent current of Idq = 350 mA. Step 5: After the bias condition is established, the RF input signal may now be applied at the appropriate frequency band. Step 6: Follow turn-off sequence of: (i) Turn off RF input power, (ii) Turn down and off drain voltage (Vd), (iii) Turn down and off gate bias voltage (Vg).
(c)2004 Fairchild Semiconductor Corporation
RMDA20420 Rev. D
RMDA20420
Application Information
CAUTION: THIS IS AN ESD SENSITIVE DEVICE Chip carrier material should be selected to have GaAs compatible thermal coefficient of expansion and high thermal conductivity such as copper molybdenum or copper tungsten. The chip carrier should be machined, finished flat, plated with gold over nickel and should be capable of withstanding 325C for 15 minutes. Die attachment for power devices should utilize Gold/Tin (80/20) eutectic alloy solder and should avoid hydrogen environment for PHEMT devices. Note that the backside of the chip is gold plated and is used as RF and DC Ground. These GaAs devices should be handled with care and stored in dry nitrogen environment to prevent contamination of bonding surfaces. These are ESD sensitive devices and should be handled with appropriate precaution including the use of wrist-grounding straps. All die attach and wire/ribbon bond equipment must be well grounded to prevent static discharges through the device. Recommended wire bonding uses 3 mils wide and 0.5 mil thick gold ribbon with lengths as short as practical allowing for appropriate stress relief. The RF input and output bonds should be typically 0.012" long corresponding to a typical 2 mil gap between the chip and the substrate material.
(c)2004 Fairchild Semiconductor Corporation
RMDA20420 Rev. D
RMDA20420
Performance Data
Normal Amplifier Configuration
Typical SS Gain vs. Frequency vs. Supply Current Bias Vd = 3.5 Typical Output Power @ 1dB Compression Bias Vd = 3.5V, Id = 350mA
35 30 25 20 15 10 5 0 -5 -10 -15 -20 -25 -30 -35 -40 0
30 25 P1dB (dBm)
300mA 200mA
350mA 400mA
20 15 10 5 0
(dB)
10
20 30 FREQUENCY (GHz)
40
50
20
22
24
26
28 30 32 34 FREQUENCY (GHz)
36
38
40
42
Typical Input Return Loss vs. Frequency Bias Vd = 3.5V, Id = 350mA
0 -10 -20 (dB) -30 -40 -50 -60 0 10 20 30 FREQUENCY (GHz) 40 50 (dB) 0 -5 -10 -15 -20 -25 -30 -35 0
Typical Output Return Loss vs. Frequency Bias Vd = 3.5V, Id = 350mA
10
20 30 FREQUENCY (GHz)
40
50
Typical SS Gain vs. Frequency vs. Supply Voltage Supply Current = 350mA
40 30 20 S21 (dB) 10 (dB) 0 -10 -20 -30 -40 0 10 20 30 FREQUENCY (GHz) 40 50 Vds = 3.5 Vds = 2.0 Vds = 5.0 40 30 20 10 0 -10 -20 -30 0
Typical SS Gain vs. Frequency vs. Base Plate Temperature Bias Vd = 3.5V, Id = 350mA
20 C 90 C
-40 C
10
20 30 FREQUENCY (GHz)
40
50
(c)2004 Fairchild Semiconductor Corporation
RMDA20420 Rev. D
RMDA20420
Performance Data (Continued)
Normal Amplifier Configuration
Gain Compression and PAE vs. Output Power Frequency = 40 GHz, Bias Vd = 3.5V, Id = 350mA
27 25 GAIN (dB) 20% 16% GAIN (dB) 27 25 Gain
Gain Compression and PAE vs. Output Power Frequency = 30 GHz, Bias Vd = 3.5V, Id = 350mA
20% 16%
Gain
PAE (%)
21
8%
21 PAE
8%
19
PAE
4%
19
4%
17 15 17 19 21 OUTPUT POWER (dBm) 23
0%
17 15 17 19 21 OUTPUT POWER (dBm) 23
0%
15 14 13 NOISE FIGURE (dB) 12 11 10 9 8 7 6 5 20
Noise Figure vs. Frequency vs. Supply Current Bias Vd = 3.5 Volts
15 14 13 NOISE FIGURE (dB)
Noise Figure vs. Frequency vs. Supply Voltage Supply Current = 200mA
Idq=100 mA
Idq=350 mA
12 11 10 9 8 7 6 Vd=3.5 Vd=2.0 Vd=5.0 Vd=4.5
Idq=200 mA 22 24 26 28 30 32 34 36 38 40
5 20 22 24 26 28 30 32 34 36 38 40 FREQUENCY (GHz)
FREQUENCY (GHz)
(c)2004 Fairchild Semiconductor Corporation
RMDA20420 Rev. D
PAE (%)
23
12%
23
12%
RMDA20420
Application Information
The RMDA20420 can be used as an even harmonic multiplier or as an odd harmonic multiplier depending on the type of DC biasing arrangement being used. Optimum DC bias is applied to peak the desired harmonic which falls into the 20 to 42GHz passband. The following application information will detail the configuration and procedure for using the RMDA20420 as an even harmonic multiplier and as an odd harmonic multiplier. Typical measured data is provided at selected frequencies within the passband with the RMDA20420 configured as a doubler and as a tripler.
Multiplier Operation
The RMDA20420 is a four stage general purpose MMIC amplifier covering the 20-42GHz passband. The amplifier has a steep gain roll off at the band edges and the input return loss of the amplifier is better than 10dB from 42GHz down to DC. Any multiplier harmonics, which fall in the passband, will get amplified and any harmonics that fall below the passband will get suppressed. A deliberate design feature that makes the RMDA20420 an effective multiplier is the ability to independently bias the first stage. This feature allows freedom to determine the optimum DC bias condition required to peak the desired harmonic and suppressing the unwanted harmonics. Optimum DC bias conditions depend largely on factors such as fundamental frequency, desired harmonic frequency, input power level, output power level and suppression requirements.
Test Set Up
The basic test set uses a source to provide the input signal at the desired frequency and power level. The DUT was biased either as an even harmonic or odd harmonic operation and the output was observed on a spectrum analyzer. The power of the harmonics was measured using the spectrum analyzer with all the cable losses accounted. Figure 5 shows the basic test set used.
RMDA20420 DUT Source Spectrum Analyzer
Figure 5. Basic Test Set Up
Even Harmonic Operation
Even harmonics are generated whenever the symmetry of the input signal waveform is distorted. This is accomplished by biasing the first stage operating point in a region of the I-V curve where the device is near pinch-off. In this condition, the first stage becomes a half wave rectifier where conduction only occurs on positive half cycles of the input waveform. Thus, presenting an asymmetrical waveform consisting mainly of positive half cycles which is rich in even harmonics to the remaining stages of the amplifier. For most even harmonic multiplier operations, the first stage is usually pinched off and the remaining stages are biased as a linear amplifier. As an example, the RMDA20420 was evaluated as a doubler. In the doubler operation, two drain voltages of +3.5V were used: One for first stage (Vd1) and the other (Vd2) for the remaining 3 stages tied together as shown in Figure 6. Independent biasing of the first stage was achieved by using two separate gate voltages. Vg1 was used for stage one and set to Vg1 = -1.0V (near pinch-off). Vg2 was used for the remaining three stages. Vg2 was adjusted until Idq = 330mA.
(c)2004 Fairchild Semiconductor Corporation
RMDA20420 Rev. D
RMDA20420
Vd1
Vd2
Vd1
Vg2 alt
Vd2
Vd3
Vd4
RF IN
RF OUT
Vg1
Vg2
Vg3
Vg4
Vg1
Vg2
Figure 6. RMDA20420 Configured as Doubler
For each input frequency and input power level, Vg1 was adjusted to peak the second harmonic. Small changes in Vg2 and Vd2 at this point help in suppressing odd harmonics. Figure 7 shows the doubler performance over the 20 to 42GHz band for a fixed input power level of +12dBm. The graph shows doubled frequencies with output power levels greater than +16dBm over the 20-42GHz band. The graph also shows the increasing power level of the fundamental at the higher end of the band since the fundamental frequency approaches the lower band edge of the amplifier passband. Based on these measurements the RMDA20420 can be used a doubler to give desired frequencies anywhere in the 20-42GHz band with a conversion gain up to 8dB and second harmonic power levels up to 20dBm.
30 2x Fo Conversion Gain=0 10 Pout (dBm)
20
0 1x Fo -10
-20
-30 20 22 24 26 28 30 32 34 36 38 40 42 Second Harmonic Frequency (GHz)
Figure 7. Measured Doubler Performance
(c)2004 Fairchild Semiconductor Corporation
RMDA20420 Rev. D
RMDA20420
Odd Harmonic Operation
Odd harmonics are generally associated with a square wave. The RMDA20420 is biased in such a way that causes the clipping of the input sine wave to closely approximate a square wave provided a high input drive level is maintained. If biased in a manner, which causes the input waveform to be clipped equally in the positive and negative cycles, then a symmetrical square wave will be approximated which contains odd harmonics. As an example, the RMDA20420 was biased as a tripler over the 20-40GHz band at selected frequencies. In this mode of operation all the drains voltages (Vd1 and Vd2) were tied together and all the gate voltages were tied together as shown in Figure 8. Vd1
Vd1
Vg2 alt
Vd2
Vd3
Vd4
RF IN
RF OUT
Vg1
Vg2
Vg3
Vg4
Vg1
Figure 8. RMDA20420 Configured as Tripler.
The test set up for this mode of operation is as shown in Figure 5.The biasing procedure requires the gate voltage Vg1 to be initially set to -1.0V. Next the drain voltage Vd1 was set to +2.0V. The input frequency was selected to give the desired tripled output and the input drive level was set to +14dBm. The output of the RDMA20420 was observed and the harmonics of the input frequency were visible on the spectrum analyzer display. The gate voltage Vg1 was adjusted gradually to peak the third harmonic. Lowering Vg1 resulted in peaking the third harmonic. Then the drain voltage Vd1 was adjusted to tweak the power level of the third harmonic. Tweaking Vg1 and Vd1 at this point resulted in further optimization of the desired harmonic or suppression of the unwanted harmonic as required. The range for Vg1 was between -0.1 to -0.6V and the range for Vd1 was between +1.1 to +1.8V. The above procedure was repeated for each input frequency tested. Figure 9 shows the tripled output for the RMDA20420 biased as described above. Input frequencies were selected to give tripled frequencies falling in the 21 to 39GHz band. The graph shows tripled output powers greater than +10dBm up to 39GHz. The power levels of the first and second harmonics were also plotted to show the level of suppression of the unwanted harmonics. The graph shows for a tripled frequency of 30GHz the output power was +14dBm, the fundamental (10GHz) power level was -17dBm and the second harmonic (20GHz) power level was +3 dBm. The conversion gain for the tripled output at 30GHz was 0dB. For tripled frequencies between 21 to 39GHz, the conversion gain was better than -4dB.
(c)2004 Fairchild Semiconductor Corporation
RMDA20420 Rev. D
RMDA20420
20 Conversion Gain=0 15 3xFo 10 21GHz 5 Pout (dBm) 39GHz 30GHz
0
2xFo
-5
-10
-15 1xFo -20 20 22 24 26 28 30 Tripled Frequency (GHz) 32 34 36 38 40
Figure 9. Measured Tripler Performance.
(c)2004 Fairchild Semiconductor Corporation
RMDA20420 Rev. D
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Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. I13

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