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OKI Semiconductor MS82V16520A
262,144-Word x 32-Bit x 2-Bank SGRAM
FEDS82V16520A-01
Issue Date:Jun. 25, 2002
GENERAL DESCRIPTION
The MS82V16520A is a 16-Mbit system clock synchronous dynamic random access memory.
FEATURES
* * * * * * * * * 262,144 words x 32 bits x 2 banks memory (1,024 rows x 256 columns x 32 bits x 2 banks) Single 3.3 V 0.3 V power supply LVTTL compatible inputs and outputs Programmable burst length (1, 2, 4, 8 and full page) Programmable CAS latency (2, 3) Power Down operation and Clock Suspend operation 2,048 refresh cycles/32 ms Auto refresh and self refresh capability Package: 100-pin plastic QFP (QFP100-P-1420-0.65-BK4) (MS82V16520A-xGA) x indicates speed rank.
PRODUCT FAMILY
Family MS82V16520A-7 MS82V16520A-8 Max. Operating Frequency 143 MHz 125 MHz Access Time 6 ns 6.5 ns Package 100-pin Plastic QFP
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PIN CONFIGURATION (TOP VIEW)
DQ2 VssQ DQ1 DQ0 Vcc NC NC NC NC NC NC NC NC NC NC Vss DQ31 DQ30 VssQ DQ29
100 97 96 95 94 93 92 91 90 89 88 87 85 84 83
DQ3 VccQ DQ4 DQ5 VssQ DQ6 DQ7 VccQ DQ16 DQ17 VssQ DQ18 DQ19 VccQ Vcc Vss DQ20 DQ21 VssQ DQ22 DQ23 VccQ DQM0 DQM2 WE CAS RAS CS BA(A10) A8
99
98
86
82
81
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 34 35 36 37 38 39 44 47 48 49 33 40 41 42 43 45 46 50
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DQ28 VccQ DQ27 DQ26 VssQ DQ25 DQ24 VccQ DQ15 DQ14 VssQ DQ13 DQ12 VccQ Vss Vcc DQ11 DQ10 VssQ DQ9 DQ8 VccQ NC DQM3 DQM1 CLK CKE NC NC A9
Pin Name A0 to A9 A0 to A7 BA (A10) CLK CKE CS RAS CAS
A0 A1 A2 A3 Vcc NC NC NC NC NC NC NC NC NC NC Vss A4 A5 A6 A7
100-Pin Plastic QFP
Function Row Address Inputs Column Address Inputs Bank Address System Clock Input Clock Enable Chip Select Row Address Strobe Column Address Strobe Pin Name WE DQM0 to DQM3 DQ0 to DQ31 VCC VSS VCCQ VSSQ NC Function Write Enable DQ Mask Enable Data Inputs/outputs Supply Voltage Ground Supply Voltage for DQ Ground for DQ No Connection
Note: The same power supply voltage level must be provided to every VCC pin and VCCQ pin. The same GND voltage level must be provided to every VSS pin and VSSQ pin.
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BLOCK DIAGRAM
CKE CLK CS RAS CAS WE DQM0 to DQM3
I/O Controller Timing Register
Bank Controller
BA
Internal Col. Address Counter
A0 to A9 BA
Column Address Buffers Column Decoders
Input Data Register 32
Input Buffers 32
88
Sense Amplifiers Internal Row Address Counter
32
Read 32 Data Register
Output Buffers
32
DQ0 to DQ31
Row Decoders Row Decoders
Word Drivers Word Drivers
8Mb Memory Cells Bank A 8Mb Memory Cells Bank B
10
Row Address Buffers Sense Amplifiers
8
Column Decoders
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PIN DESCRIPTION
CLK CS Fetches all inputs at the "H" edge. Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE, DQM0, DQM1, DQM2 and DQM3. Masks system clock to deactivate the subsequent CLK operation. If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is deactivated. CKE should be asserted at least one cycle prior to a new command. Row & column multiplexed. Row address: RA0 to RA9, Column address: CA0 to CA7
CKE
Address
BA RAS CAS WE
Selects bank to be activated during row address latch time and selects bank for precharge and read/write during column address latch time. BA = "L": Bank A BA = "H": Bank B Functionality depends on the combination. For details, see the function truth table. Masks the read data of two clocks later when DQM0 to DQM3 are set "H" at the "H" edge of the clock signal. Masks the write data of the same clock when DQM0 to DQM3 are set "H" at the "H" edge of the clock signal. DQM0 controls DQ0 to DQ7, DQM1 controls DQ8 to DQ15, DQM2 controls DQ16 to DQ23, and DQM3 controls DQ24 to DQ31. Data inputs/outputs are multiplexed on the same pin.
DQM0 to DQM3
DQ0 to DQ31
*Notes: 1. When CS is set "High" at a clock transition from "Low" to "High", all inputs except CLK, CKE, DQM0, DQM1, DQM2, and DQM3 are invalid. 2. When issuing an active, read or write command, the bank is selected by BA.
BA 0 1 Active, read or write Bank A Bank B
3. The auto precharge function is enabled or disabled by the A9 input when the read or write command is issued.
A9 0 1 0 1 BA 0 0 1 1 Operation After the end of burst, bank A holds the active status. After the end of burst, bank A is prechaged automatically. After the end of burst, bank B holds the active status. After the end of burst, bank B is prechaged automatically.
4. When issuing a precharge command, the bank to be precharged is selected by the A9 and BA inputs.
A9 0 0 1 BA 0 1 x Operation Bank A is precharged. Bank B is precharged. Both banks are precharged.
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COMMAND OPERATION
Mode Register Set Command (CS, RAS, CAS, WE = "Low") The MS82V16520A has the mode register that defines the operation mode "CAS Latency, Burst Length, Burst Sequence". The Mode Register Set command should be executed just after the MS82V16520A is powered on. Before entering this command, all banks must be precharged. Next command can be issued after tRSC. Auto Refresh Command (CS, RAS, CAS = "Low", WE, CKE = "High") The Auto Refresh command performs refresh automatically by the address counter. The refresh operation must be performed 2,048 times within 32 ms and the next command can be issued after tRC from last Auto Refresh command. Before entering this command, all banks must be precharged. Self Refresh Entry/Exit Command (CS, RAS, CAS, CKE = "Low", WE = "High") The self refresh operation continues after the Self Refresh Entry command is entered, with CKE level left "low". This operation terminates by making CKE level "high". The self refresh operation is performed automatically by the internal address counter on the MS82V16520A chip. In self refresh mode, no external refresh control is required. Before entering self refresh mode, all banks must be precharged. Next command can be issued after tRC. Single Bank Precharge Command (CS, RAS, WE, A9 = "Low", CAS = "High") The Single Bank Precharge command triggers bank precharge operation. Precharge bank is selected by BA. All Bank Precharge Command (CS, RAS, WE = "Low", CAS, A9 = "High") The All Bank Precharge command triggers precharge of both Bank A and Bank B. Bank Active Command (CS, RAS = "Low", CAS, WE = "High") The Bank Active command activates the bank selected by BA. The Bank Active command corresponds to conventional DRAM's RAS falling operation. Row addresses "A0 to A9 and BA" are strobed. Write Command (CS, CAS, WE, A9 = "Low", RAS = "High") The Write command is required to begin burst write operation. Then burst access initial bit column address is strobed. Write with Auto Precharge Command (CS, CAS, WE = "Low", RAS, A9 = "High") The Write with Auto Precharge command is required to begin burst write operation with automatic precharge after the burst write. Any command that interrupts this operation cannot be issued. Read Command (CS, CAS, A9 = "Low", RAS, WE = "High") The Read command is required to begin burst read operation. Then burst access initial bit column address is strobed.
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Read with Auto Precharge Command (CS, CAS = "Low", RAS, WE, A9 = "High") The Read with Auto Precharge command is required to begin burst read operation with automatic precharge after the burst read. Any command that interrupts this operation cannot be issued. No Operation Command (CS = "Low", RAS, CAS, WE = "High") The No Operation command does not trigger any operation. Device Deselect Command (CS = "High") The Device Deselect command disables the RAS, CAS, WE and Address input. This command does not trigger any operation. Data Write/Output Enable Command (DQMi = "Low") The Data Write/Output Enable command enables DQ0 to DQ31 in read or write. The each DQM0, 1, 2 and 3 corresponds to DQ0 to DQ7, DQ8 to DQ15, DQ16 to DQ23 and DQ24 to DQ31 respectively. Data Mask/Output Disable Command (DQMi = "High") The Data Mask/Output Disable command disables DQ0 to DQ31 in read or write. In read cycle output buffers are disabled after 2 clocks . In write cycle input buffers are disabled at the same clock. The each DQM0, 1, 2 and 3 corresponds to DQ0 to DQ7, DQ8 to DQ15, DQ16 to DQ23 and DQ24 to DQ31 respectively. Burst Stop Command (CS, WE = "Low", RAS, CAS = "High") The Burst Stop command stops burst access when the access is in full page. After the Burst Stop command is entered, the output buffer goes into high impedance state.
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TRUTH TABLE
Command Truth Table
Function Device Deselect No Operation Mode Register Set Auto Refresh Bank Activate Read Read with Auto Precharge Write Write with Auto Precharge Precharge Select Bank Precharge All Banks Burst Stop CS H L L L L L L L L L L L RAS x H L L L H H H H L L H CAS x H L L H L L L L H H H WE x H L H H H H L L L L L x BA BA BA BA BA BA x x L H L H L H x Address BA x x A9 x x OP. CODE x RA CA (A7 to A0) CA (A7 to A0) CA (A7 to A0) CA (A7 to A0) x x x x A8 to A0 x x
DQM Truth Table
Function Data Write/Output Enable Data Mask/Output Disable DQMi L H
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Function Truth Table (1/2)
Note 1 Current State Idle CS H L L L L L L L Active (ACT) H L L L L L L Read (RD) H L L L L L L L Write (WT) H L L L L L L L RAS CAS x H H H L L L L x H H H L L L x H H H H L L L x H H H H L L L x H H L H L H L x H L L H H L x H H L L H H L x H H L L H H L WE x H L x H L L H x x H L H L x x H L H L H L x x H L H L H L x BA x x BA BA BA L BA x x x BA BA BA BA x x x x BA BA BA BA x x x x BA BA BA BA x Address x x x CA, A9 RA A9 x x x CA, A9 CA, A9 RA A9 x x x x CA, A9 CA, A9 RA A9 x x x x CA, A9 CA, A9 RA A9 x NOP NOP ILLEGAL ILLEGAL Row Active NOP Auto Refresh/Self refresh NOP NOP Read Write ILLEGAL Precharge ILLEGAL NOP (Continue Row Active after Burst ends) NOP (Continue Row Active after Burst ends) 1,2,4,8 Burst Length : ILLEGAL Full Page Burst : Burst Stop Row Active Term Burst, new Read Term Burst, start Write ILLEGAL Term Burst, execute Precharge ILLEGAL NOP (Continue Row Active after Burst ends) NOP (Continue Row Active after Burst ends) 1,2,4,8 Burst Length : ILLEGAL Full Page Burst : Burst Stop Row Active Term Burst, start Read Term Burst, new Write ILLEGAL Term Burst, execute Precharge ILLEGAL 3 3 2 3 3 3 2 2 4 5 2 2 Action Note
Op-Code Mode Register Write
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Function Truth Table (2/2)
Note 1 Current State Read with Auto Precharge (RAP) CS H L L L L L L L Write with Auto Precharge (WAP) H L L L L L L L Precharging (PRE) H L L L L L Refreshing (REF) H L L L L L L RAS CAS x H H H H L L L x H H H H L L L x H H H L L x H H H L L L x H H L L H H L x H H L L H H L x H H L H H x H H L H H L WE x H L H L H L x x H L H L H L x x H L x H L x H L x H L x BA x x x BA BA BA BA x x x x BA BA BA BA x x x BA BA BA BA x x x BA BA BA x Address x x x CA, A9 CA, A9 RA A9 x x x x CA, A9 CA, A9 RA A9 x x x x CA, A9 A9 x x x x CA, A9 RA A9 x Action NOP (Continue Burst to End and enter Row Precharge) NOP (Continue Burst to End and enter Row Precharge) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP (Continue Burst to End and enter Row Precharge) NOP (Continue Burst to End and enter Row Precharge) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP Idle after tRP NOP Idle after tRP ILLEGAL ILLEGAL ILLEGAL NOP NOP Idle after tRC NOP Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL 2 2 2 4 2 2 2 2 Note
ABBREVIATIONS BA = Bank Address NOP = No Operation command
RA = Row Address
CA = Column Address
Notes: 1. All inputs are enabled when CKE is set high for at least 1 cycle prior to the inputs. 2. Illegal to bank in specified state, but may be legal in some cases depending on the state of bank selection. 3. To avoid bus contention, satisfy tCCD and tDPL. 4. NOP to bank precharging or in idle state. Precharges activated bank by BA or A9. 5. Illegal if any bank is not idle.
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Function Truth Table for CKE
Current State (n) Self Refresh (SREF) CKEn-1 CKEn CS H L L L L L L Power Down (PD) H L L L L L L All Banks Idle (ABI) H H H H H H H H L Any State Other than Listed Above H H L L x H H H H H L x H H H H H L H L L L L L L L L H L H L x H L L L L x x H L L L L x x H L L L L L L x x x x x RAS CAS x x H H H L x x x H H H L x x x H H H L L L x x x x x x x H H L x x x x H H L x x x x H H L H L L x x x x x WE x x H L x x x x x H L x x x x x H L x L H L x x x x x Address x x x x x x x x x x x x x x x x x x x x x x x x x x x INVALID Exit Self Refresh ABI Exit Self Refresh ABI ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self Refresh) INVALID Exit Self Refresh ABI Exit Self Refresh ABI ILLEGAL ILLEGAL ILLEGAL NOP (Continue power down mode) Refer to Truth Table Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Enter Self Refresh ILLEGAL NOP Refer to Truth Table Begin Clock Suspend Next Cycle Enable Clock of Next Cycle Continue Clock Suspension 6 6 6 6 6 6 6 6 6 Action Note
Note:
6. Power-down and self refresh can be entered only when all the banks are in an idle state.
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Mode Set Address Keys
Operation Code A8 A7 0 0 1 1 A9 0 1 0 1 0 1 TM Mode Setting Vender Use Only 0 0 0 0 1 1 1 1 CAS Latency A6 A5 A4 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 CL Reserved Reserved 2 3 Reserved Reserved Reserved Reserved 0 1 Burst Type A3 BT Sequential Interleave A2 A1 A0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Burst Length BT = 0 1 2 4 8 Reserved Reserved Reserved Full Page BT = 1 Reserved Reserved 4 8 Reserved Reserved Reserved Reserved
Write Burst Length Length Burst Single Bit
POWER ON SEQUENCE 1. With CKE = "H", DQM = "H" and the other inputs in NOP state, turn on the power supply and start the system clock. 2. After the VCC voltage has reached the specified level, pause for 200 s or more with the input kept in NOP state. 3. Issue the precharge all bank command. 4. Apply an Auto-refresh 2 or more times. 5. Enter the mode register command.
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Burst Length and Sequence BL = 2
Starting Address (column address A0, binary) 0 1 Sequential Type 0, 1 1, 0 Interleave Type Not supported Not supported
BL = 4
Starting Address (column address A1, A0, binary) 00 01 10 11 Sequential Type 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 Interleave Type 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0
BL = 8
Starting Address (column address A2 to A0, binary) 000 001 010 011 100 101 110 111 Sequential Type 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 0, 1, 2, 3, 4 6, 7, 0, 1, 2, 3, 4, 5 7, 0, 1, 2, 3, 4, 5, 6 Interleave Type 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0
BL = Full: Sequential only
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READ/WRITE COMMAND INTERVAL
Read to Read Command Interval
BL = 4, CL = 2 0 CLK RD-A RD-B Hi-Z 1 2 3 4 5 6 7 8
DQ 1cycle
QA1
QB1
QB2
QB3
QB4
Write to Write Command Interval
BL = 4, CL = 2 0 CLK WT-A WT-B DB1 DB3 Hi-Z 1 2 3 4 5 6 7 8
DQ
DA1
DB2
DB4
1cycle
Write to Read Command Interval
BL = 4 0 CLK WT-A RD-B Hi-Z 1 2 3 4 5 6 7 8
CL = 2 DQ
DA1
QB1
QB2
QB3
QB4
CL = 3 DQ
WT-A RD-B Hi-Z
DA1 1cycle
QB1
QB2
QB3
QB4
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Read to Write Command Interval
BL = 4, CL = 2, 3 0 CLK CL = 2, 3 RD-A WT-B 1 2 3 4 5 6 7 8
DQM Hi-Z
DQ
DB1 1cycle
DB2
DB3
DB4
BL = 4, CL = 2, 3 0 CLK CL = 2 RD-A WT-B 1 2 3 4 5 6 7 8
DQM Hi-Z
DQ
QA1
QA2
CL = 3
RD-A
QA3 DB1 DB2 Hi-Z is necessary WT-B
DQM Hi-Z
DQ
QA1
QA2
DB1 Hi-Z is necessary
DB2
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BURST TERMINATION
Burst Read Termination by Precharging in READ Cycle
BL = 2, 4, 8, Full 0 CLK tRP CL = 2 RD PRE ACT Hi-Z tRP CL = 3 RD PRE ACT Hi-Z 1 2 3 4 5 6 7 8
DQ
Q1
Q2
Q3
Q4
DQ
Q1
Q2
Q3
Q4
Burst Write Termination by Precharging in WRITE Cycle
BL = 2, 4, 8, Full 0 CLK tDPL CL = 2 WT PRE D5 tRP ACT Hi-Z 1 2 3 4 5 6 7 8
DQ
D1
D2
D3
D4
DQM tDPL CL = 3 WT PRE Hi-Z tRP ACT
DQ
D1
D2
D3
D4
D5
DQM
Note: The burst write operation is unfinished, the input data must be masked by means of DQM for assurance of the CLK by tDPL.
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Read Burst Stop Command
BL = Full 0 CLK RD CL = 2 DQ CL = 3 DQ BST Hi-Z 1 2 3 4 5 6 7 8
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Hi-Z
Write Burst Stop Command
BL = Full 0 CLK WT CL = 2, 3 DQ BST Hi-Z 1 2 3 4 5 6 7 8
D1
D2
D3
D4
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AUTO PRECHARGE
Read with Auto Precharge
BL = 4 0 CLK
Auto Precharge Starts
1
2
3
4
5
6
7
8
CL = 2
RAP Hi-Z
DQ
Q1
Q2
Q3
Q4
Auto Precharge Starts
CL = 3
RAP Hi-Z
DQ
Q1
Q2
Q3
Q4
(tRAS is satisfied.)
Write with Auto Precharge
BL = 4 0 CLK
Auto Precharge Starts
1
2
3
4
5
6
7
8
CL = 2
WAP Hi-Z
Auto Precharge Starts
DQ
Q1
Q2
Q3
Q4
CL = 3
WAP Hi-Z
(tRAS is satisfied.)
DQ
Q1
Q2
Q3
Q4
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ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Voltage on Power Supply Pin Relative to GND Voltage on Input Pin Relative to GND Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VCC VIN, VOUT IOS PD* Topr Tstg Rating -0.5 to 4.6 -0.5 to VCC + 0.5 4.6 50 1 0 to 70 -55 to 150 Unit V V mA W C C
*: Ta = 25 C Caution: Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Ratings conditions for extended periods may affect device reliability.
Recommended Operating Conditions
(Ta = 0 to 70C) Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min. 3.0 0 2.0 -0.3 Typ. 3.3 0 -- -- Max. 3.6 0 VCC + 0.3 0.8 Unit V V V V
Capacitance
(VCC = 3.3 V 0.3 V, Ta = 25C, f = 1 MHz) Parameter Input Capacitance (A0 to A9, BA) Input Capacitance (CLK, CKE, CS, RAS, CAS, WE DQM0 to DQM3) Output Capacitance (DQ0 to DQ31) Symbol CIN1
*
Min. -- -- --
Max. 5 5 6
Unit pF pF pF
CIN2* COUT
*
*: This parameter is sampled and not 100% tested.
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DC Characteristics
Parameter Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Operating Current (1 Bank) Precharge Standby Current in Power Down Mode Symbol VOH VOL ILI ILO ICC1 ICC2P ICC2PS ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS ICC4 ICC5 ICC6 Test Condition CKE -- -- -- -- CKE VIH CKE VIL CKE VIL CKE VIH CKE VIH CKE VIL CKE VIL CKE VIH CKE VIH CKE VIH CKE VIH CKE 0.2V Other IOH= -2.0 mA IOL= 2.0 mA -- -- tCK = min. tRC = min. No Burst tCK = min. CLK VIL tCK = CS VIH tCK = min. CLK VIL tCK = tCK = min. CLK VIL tCK = CS VIH tCK = min. CLK VIL tCK = tCK = min. tRC min. --
MS82V16520A-7 MS82V16520A-8
Min. 2.4 -- -10 -10 -- -- -- -- -- -- -- -- -- -- -- --
Max. -- 0.4 10 10 190 2 2 40 20 3 3 50 30 240 170 3
Min. 2.4 -- -10 -10 -- -- -- -- -- -- -- -- -- -- -- --
Max. -- 0.4 10 10 170 2 2 40 20 3 3 50 30 200 150 3
Unit V V A A mA mA mA mA mA mA mA mA mA mA mA mA
Note
1, 2 3 2 2
Precharge Standby Current in Non Power Down Mode
Active Standby Current in Power Down Mode
3 3 3 3 1, 2
Active Standby Current in Non Power Down Mode Operating Current (Burst Mode) Refresh Current Self Refresh Current
Notes 1. The maximum value of power supply current is obtained with the output open. 2. Address and data are changed only one time during one cycle. 3. Address and data are changed only one time during two cycles.
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AC Characteristics Test conditions * AC measurements assume tT = 1 ns. * Reference level for measuring timing of input signals is 1.4 V. Transition times are measured between VIH and VIL. * If tT is longer than 1 ns, reference level for measuring timing of input signals is VIH (MIN.) and VIL (MAX). * An access time is measured at 1.4 V. * Input levels at the AC testing are 2.4 V/0.4 V.
tCK tCH 2.4 V CLK 1.4 V 0.4 V tSetup tHold 2.4 V Input 1.4 V 0.4 V tOH Output 1.4 V 1.4 V tCL
tAC
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Synchronous Characteristics
Parameter Clock Cycle Time Access Time from CLK CLK High Level Width CLK Low Level Width Data-out Hold Time Data-out Low-impedance Time Data-out High-impedance Time Data-in Setup Time Data-in Hold Time Address Setup Time Address Hold Time CKE Setup Time CKE Hold Time Command (CS, RAS, CAS, WE, DQM) Setup Time Command (CS, RAS, CAS, WE, DQM) Hold Time CAS Latency = 3 CAS Latency = 2 CAS Latency = 3 CAS Latency = 2 Symbol tCK3 tCK2 tAC3 tAC2 tCH tCL tOH tLZ tHZ tDS tDH tAS tAH tCKS tCKH tCMS tCMH
MS82V16520A-7 MS82V16520A-8
Min. 7 10 -- -- 2.5 2.5 2 0 -- 2 1 2 1 2 1 2 1
Max. -- -- 6 8 -- -- -- -- 5 -- -- -- -- -- -- -- --
Min. 8 12 -- -- 3 3 2 0 -- 2.5 1 2.5 1 2.5 1 2.5 1
Max. -- -- 6.5 9 -- -- -- -- 6 -- -- -- -- -- -- -- --
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note
1 1
Note 1. Output load.
1.4 V Z = 50 Output 30 pF 50
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Asynchronous Characteristics
Parameter REF to REF/ACT Command Period ACT to PRE Command Period PRE to ACT Command Period Delay Time ACT to READ/WRITE Command ACT (A) to ACT (B) Command Period READ/WRITE to READ/WRITE Command Period Data-in to PRE Command Period Data Output to WRITE Command Input Time Mode Register Set Cycle Time Transition Time Refresh Time Symbol tRC tRAS tRP tRCD tRRD tCCD tDPL tOWD tRSC tT tREF
MS82V16520A-7 MS82V16520A-8
Min. 63 42 21 21 14 7 14 14 14 1 --
Max. -- 120k -- -- -- -- -- -- -- 30 32
Min. 72 48 24 24 16 8 16 16 16 1 --
Max. -- 120k -- -- -- -- -- -- -- 30 32
Unit ns ns ns ns ns ns ns ns ns ns ms
Note
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TIMING WAVEFORM
READ/WRITE Cycle (BL = 2, CL = 3)
0 CLK CKE
tCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
tCKH
17
18
19
tCKS tCH
tCL
tCMS tCMH
CS RAS CAS WE
tAS tAH
BA A9 ADD DQM 0-3 DQ Hi-Z
tRCD tLZ RAa RBa
RAa
CAa tCMS
CAb tCMH
RBa
tAC tOH
tHZ
tDS tDH
DAb1 DAb2
QAa1 QAa2
tOWD tRAS
tDPL tRP
tRC ACT-A RD-A WT-A PRE-A ACT-B
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FEDS82V16520A-01
OKI Semiconductor
MS82V16520A
Mode Register Set
0 CLK CKE CS RAS CAS WE BA A9 ADD DQM 0-3 DQ Hi-Z H 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
PRE-ALL tRP
MRA tRSC
ACT
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FEDS82V16520A-01
OKI Semiconductor
MS82V16520A
Auto Refresh
0 CLK CKE CS RAS CAS WE BA A9 ADD DQM 0-3 DQ L Hi-Z H
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
PRE-ALL tRP
REF tRC
REF tRC
ACT
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FEDS82V16520A-01
OKI Semiconductor
MS82V16520A
Self Refresh (Entry and Exit)
0 CLK CKE CS RAS CAS WE BA A9 ADD DQM 0-3 DQ L Hi-Z H
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
PRE-ALL tRP
SELF Entry
SELF Exit
tRC
SELF Entry
SELF Exit
ACT tRC
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FEDS82V16520A-01
OKI Semiconductor
MS82V16520A
Burst Termination by Precharging (BL = 8, CL = 3)
0 CLK CKE CS RAS CAS WE BA A9 ADD DQM 0-3 DQ L
tDPL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
H
RAa RAa CAa
RAb RAb CAb
Hi-Z
DAa1
QAb1 QAb2 QAb3 QAb4
ACT-A
WT-A
PRE-A
ACT-A
RD-A
PRE-A PRE Command Termination
PRE Command Termination
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FEDS82V16520A-01
OKI Semiconductor
MS82V16520A
Auto Precharge (BL = 4, CL = 3)
0 CLK CKE CS RAS CAS WE BA A9 ADD DQM 0-3 DQ RAa RAa L Hi-Z
QAa1 QAa2 QAa3 QAa4 QBa1 QBa2 QBa3 QBa4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
H
RBa CAa RBa CBa
ACT-A
RAP-A ACT-B
AP-A
WAP-B
AP-B
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FEDS82V16520A-01
OKI Semiconductor
MS82V16520A
Power Down Mode and Clock Suspension (BL = 4, CL = 2)
0 CLK tCKS CKE CS RAS CAS WE BA A9 ADD DQM 0-3 DQ L Hi-Z
QAa1 QAa2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
RAa RAa CAa
QAa3
QAa4
ACT-A PD Entry PD Exit
RD-A Clock Mask Start Clock Mask End
PRE-A PD Entry PD Exit
ACTIVE STANDBY
PRECHARGE STANDBY
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FEDS82V16520A-01
OKI Semiconductor
MS82V16520A
CLOCK Suspend Exit & Power Down Exit
1) Clock Suspend (= Active Power Down) Exit 2) Power Down (= Precharge Power Down) Exit
CLK CKE Internal CLK Command
CLK
Note 3
tCKS
Note 1
CKE Internal CLK RD Command
tCKS
Note 2
NOP ACT
Notes: 1. Active power down: one or both bank active state. 2. Precharge power down: both bank precharge state. 3. NOP should be issued. And new command can be issued after 1 Clock.
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FEDS82V16520A-01
OKI Semiconductor
MS82V16520A
Byte Read/Write Operation (by DQM) (BL = 4, CL = 3)
0 CLK CKE CS RAS CAS WE BA A9 ADD DQM0 DQM1 DQ 0-7 DQ 8 - 15
QBa1 QBa2 QBa3 DBb2 DBb3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
H
RBa RBa CBa CBb
QBa2 QBa3 QBa4
DBb1 DBb2
DBb4
ACT-B
RD-B
Byte of DQ8-15 not Read
WT-B Byte of Byte of DQ8-15 DQ0-7 not Write not Write Byte of Byte of DQ0-7 DQ0-7 not Read not Write
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FEDS82V16520A-01
OKI Semiconductor
MS82V16520A
Burst Read and Single Write (BL = 4, CL = 3)
0 CLK CKE CS RAS CAS WE BA A9 ADD DQM 0-3 DQ H
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
RAa RAa L Hi-Z
QAa1 QAa2 QAa3 QAa4
CAa
CBb
CBb
DBb
DBc
ACT-B
RD-B
Single WT
Single WT
PRE-B
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FEDS82V16520A-01
OKI Semiconductor
MS82V16520A
Random Column Read (Continuous Read of Same Bank) (BL = 4, CL = 3)
0 CLK CKE CS RAS CAS WE BA A9 ADD DQM 0-3 DQ L
QAa1 QAa2 QAa3 QAa4 QAb1 QAb2 QAc1 QAc2 QAc3 QAc4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
H
RAa RAa CAa CAb CAc
RAi RAi
ACT-A
RD-A
RD-A
RD-A
PRE-A
ACT-A
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FEDS82V16520A-01
OKI Semiconductor
MS82V16520A
Random Column Write (Continuous Write of Same Bank) (BL = 4, CL = 3)
0 CLK CKE CS RAS CAS WE BA H
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
A9 ADD DQM 0-3 DQ L
RBa RBa CBa CBb CBc
RBi RBi
DBa1 DBa2 DBa3 DBa4 DBb1 DBb2 DBc1 DBc2 DBc3 DBc4
ACT-B
WT-B
WT-B
WT-B
PRE-B
ACT-B
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FEDS82V16520A-01
OKI Semiconductor
MS82V16520A
Interleaved Column Read (BL = 4, CL = 3)
0 CLK CKE CS RAS CAS WE BA A9 ADD DQM 0-3 DQ L
QAa1 QAa2 QAa3 QAa4 QBa1 QBa2 QBb1 QBc2 QAb1 QAb2 QAb3 QAb4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
H
RAa RAa
RBa CAa RBa CBa CBb CAb
ACT-A
RD-A ACT-B tRCD tRRD
RD-B
RD-B
RD-A
PRE-B
PRE-A
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FEDS82V16520A-01
OKI Semiconductor
MS82V16520A
Interleaved Column Write (BL = 4, CL = 3)
0 CLK CKE CS RAS CAS WE BA A9 ADD DQM 0-3 DQ L H
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
RAa RAa
RBa CAa RBa CBa CBb CAb
DAa1 DAa2 DAa3 DAa4 DBa1 DBa2 DBb1 DBb2 DAb1 DAb2 DAb3 DAb4
ACT-A
WT-A ACT-B tRCD tRRD
WT-B
WT-B
WT-A
PRE-B
PRE-A
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FEDS82V16520A-01
OKI Semiconductor
MS82V16520A
PACKAGE DIMENSIONS
(Unit: mm)
QFP100-P-1420-0.65-BK4
Mirror finish
5
Notes for Mounting the Surface Mount Type Package
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Solder plating (5m) 1.54 TYP. 4/Nov. 28, 1996
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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FEDS82V16520A-01
OKI Semiconductor
MS82V16520A
REVISION HISTORY
Document No.
PEDS82V16520A-01
Date
Nov. 2001
Page Previous Current Edition Edition
- 1 - 1
Description
Preliminary first edition Changed the subtitle from "2262,144-Word x 32-Bit x 2-Bank SDRAM" to "262,144-Word x 32-Bit x 2-Bank SGRAM". Changed the table in "PRODUCT FAMILY" Changed Note 3 to Note 4 and added Note 3. Added symbol "CKE" in headers "Auto Refresh Command" and "Self Refresh Entry/Exit Command". Added Section "Write with Auto Precharge Command (CS, CAS, WE = "Low", RAS, A9 = "High"). Added Sections "Read with Auto Precharge Command (CS, CAS = "Low", RAS, WE, A9 = "High") and "Burst Stop Command (CS, WE = "Low", RAS, CAS = "High"). Added the contents of Functions "Read with Auto Precharge" and "Write with Auto Precharge". Partially changed the contents of Column "Address". Current State "Precharging (PRE)" has been moved to page 9 and changed partially. Added Current States "Read with Auto Precharge (RAP)" and "Write with Auto Precharge (WAP)". Partially changed the content of Column "Address" in Current State "Refreshing (REF)". Partially changed the content of POWER ON SEQUENCE 4. Changed the heading from "Burst Read Termination ---" to "Burst Write Termination ---" and partially changed the timing diagram. Changed the content of Note. Changed "BL = 2, 4, 8, Full" to "BL = Full" in two diagrams. Added Section "AUTO PRECHARGE". Added Sentences shown with "Caution" in the Absolute Maximum Ratings section. Added asterisks "*" in the symbol column in the table of the Capacitance section and added the sentence shown with asterisk "*".
4
4
5
5
6
6
7 8 PEDS82V16520A-02 Apr. 26, 2002 8
7 8 9
9
9
11
11
15
15
16 -
16 17
17
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FEDS82V16520A-01
OKI Semiconductor
MS82V16520A
Document No.
Date
Page Previou Current s Edition Edition
Description
Changed a family device name from MS82V 16520A-10 to MS82V16520A-7 shown in the table and added related values.
18
19
Partially changed Max. values of MS82V 16520A-75 and MS82V16520A-8. Partially changed Test Condition "Other" of Symbols ICC2N, ICC3P, and ICC3N. Added 1 in Column "Note" of Symbol ICC4. Changed a family device name from MS82V 16520A-10 to MS82V16520A-7 shown in the table and added related values. Partially changed Max. and Min. values of MS82V16520A-75 and MS82V16520A-8. Changed a family device name from MS82V 16520A-10 to MS82V16520A-7 shown in the table and added related values. Change the Min. values of Symbol tDPL. Changed timings of DQM and DQ between CLK pulses 4 and 6. Added Section "Auto Prechaged (BL = 4, CL = 3)". First edition Partially changed the table of "PRODUCT FAMILY" Partially changed the content of "Package" in the FEATURES section. Partially changed the tables of "DC Characteristics", "Synchronous Characteristics", and "Asynchronous Characteristics".
PEDS82V16520A-02
Apr. 26, 2002
20
21
21
22
26 - -
27 28 -
FEDS82V16520A-01
Jun. 25, 2002
1
1
19,21,22
19,21,22
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FEDS82V16520A-01
OKI Semiconductor
MS82V16520A
NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2002 Oki Electric Industry Co., Ltd.
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