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OKI Semiconductor ML9209-xx
Vacuum fluorescent display tube controller driver
FEDL9209-01
Issue Date: Oct. 20, 2004
GENERAL DESCRIPTION
The ML9209-xx is an alphanumeric type vacuum fluorescent display (VFD) tube controller driver IC which can display alphanumeric characters, symbols, and bar charts. Vacuum fluorescent display tube drive signals are generated by serial data sent from a micro-controller. A display system is easily realized by internal ROM and RAM for character display. -01 is available as a general-purpose code. Custom codes are provided on customer's request.
FEATURES
* Logic power supply and vacuum fluorescent display tube driving power supply (VDD) : 3.3 V10% or 5.0 V10% * Vacuum fluorescent display tube driving power supply (VFL) : VDD - 20 V to VDD - 42 V * VFD driver output current (VFD driver output can be connected directly to the VFD tube. No pull-down resistor is required.) * Segment driver (SEG1-16) : -6 mA (VFL = VDD - 42 V) * Segment driver (AD1, 2) : -15 mA (VFL = VDD - 42 V) * Grid driver (COM1-16) : -30 mA (VFL = VDD - 42 V) * Content of display * CGROM : 16 segments 240 types (character data) * CGRAM : 16 segments 16 types (character data) * ADRAM : 16 (display digit)x 2 bits (symbol data) * DCRAM : 16 (display digit) x 8 bits (register for character data display) * Display control function * Display digits : 1 to 16 digits * Display duty (brightness adjustment) : 16 stages * All display lights ON/OFF * Four interfaces with microcontroller: DA, CS, CP, RESET * Instruction executable with 1 byte (excluding data write for each RAM) * Built-in oscillation circuit (resistor & capacitor connected externally) * Package options: 44-pin plastic QFP (QFP44-P-910-0.80-2K) (ML9209-xxGA)
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BLOCK DIAGRAM
VDD GND VFL DCRAM 16w x 8b CGROM 240wx16b Segment Driver RESET DA CP CS 8 bit Shift Register CGRAM 16w x 16b ADRAM 16w x 2b SEG16 AD1 AD Driver AD2 SEG1
Address Selector Command Decoder Control Circuit COM1 Grid Driver COM16 Write Address Counter Read Address Counter
Digit Control Duty Control
Timing Generator 1 Timing Generator 2
OSC0
Oscillator
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PIN CONFIGURATION (TOP VIEW)
39 VFL 38 SEG11
44 SEG16 43 SEG15
42 SEG14 41 SEG13 40 SEG12
SEG10
SEG9 SEG8 36 35
37
34 33 SEG6 32 SEG5 31 SEG4 30 SEG3 29 SEG2 28 SEG1 27 AD2 26 AD1 25 VDD 24 DA 23 CP CS 22
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9
1 2 3 4 5 6 7 8 9
COM10 10 COM11 11 COM12 12 COM13 13 COM14 14 COM15 15 COM16 16 VFL 17 VDD 18 OSC0 19 GND 20 RESET 21
44-Pin Plastic QFP
SEG7
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PIN DESCRIPTION
Pin 28-38, 40-44 Symbol SEG1-16 Type O Connects to VFD tube anode electrode VFD tube 1-16 COM1-16 O grid electrode 26, 27 18, 25 20 17,39 AD1-2 O VFD tube anode electrode Description VFD tube anode electrode drive output. Directly connected to the VFD tube and no pull-down resistor is required. IOH > -6 mA VFD tube grid electrode drive output. Directly connected to the VFD tube and no pull-down resistor is required. IOH > -30 mA VFD tube anode electrode drive output. Directly connected to the VFD tube and no pull-down resistor is required. IOH > -15 mA The voltage supply between VDD and GND is for the power supply for the internal logic. The voltage supply between VDD and VFL is for the power supply for driving the VFD tube. Apply power to VDD first, then to VFL. 24 23 22 DA CP CS I I I Microcontroller Microcontroller Microcontroller Serial data input pin (positive logic). Data is input from the LSB. Shift clock input pin. Serial data is shifted in on a rising edge of CP. Chip select input pin. Serial data transfer is disabled when CS pin is "H" level. Reset input. Setting this pin to "Low" initializes all the functions. Initial status is as follows. * Address of each RAM.............. Address "00"H * Data of each RAM ................... Content is undefined * Display digit ............................ 16 digits * Brightness adjustment............. 0/16 * All display lights ON or OFF .... OFF mode * All outputs............................... Low level Pin for RC oscillation. Resistors and capacitors are connected externally and constants vary depending on the VDD voltage used. The target oscillation frequency is 2MHz. 19 OSC0 I/O C1, R1
OSC0
VDD
GND -- VFL Power supply
21
RESET
l
Microcontroller
(RC oscillator circuit)
C1 R1
*Refer to the Application Circuit.
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ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage (1) Supply Voltage (2) Input Voltage Power Dissipation Storage Temperature Output Current Symbol VDD VFL VlN PD TSTG lO1 lO2 IO3 Condition -- -- -- Ta 25C -- COM1-16 AD1-2 SEG1-16 Rating -0.3 to +6.5 VDD - 45 -0.3 to VDD+0.3 541 -55 to +150 -40 to 0.0 -20 to 0.0 -10 to 0.0 Unit V V V mW C mA mA mA
RECOMMENDED OPERATING CONDITIONS-1
* When the unit power supply voltage is 5.0 V (typ.)
Parameter Supply Voltage (1) Supply Voltage (2) High Level Input Voltage Low Level Input Voltage CP frequency Self-oscillation frequency Frame Frequency Operating Temperature Symbol VDD VFL VIH VIL fC fOSC fFR Top Condition -- -- All input pins except OSC0 All input pins except OSC0 -- R1 = 8.2 k5%, C1 = 82 pF5% DIGIT = 1 to16, R1 = 8.2 k5%, C1 = 82 pF5% -- Min. 4.5 VDD -42 0.7 VDD -- -- 1.4 170 -40 Typ. 5.0 -- -- -- -- 2.0 244 -- Max. 5.5 VDD-20 -- 0.3 VDD 2.0 2.6 318 85 Unit V V V V MHz MHz Hz C
RECOMMENDED OPERATING CONDITIONS-2
* When the unit power supply voltage is 3.3 V (typ.)
Parameter Supply Voltage (1) Supply Voltage (2) High Level Input Voltage Low Level Input Voltage CP frequency Self-oscillation frequency Frame Frequency Operating Temperature Symbol VDD VFL VIH VIL fC fOSC fFR Top Condition -- -- All input pins except OSC0 All input pins except OSC0 -- R1 = 6.8 k5%, C1 = 82 pF5% DIGIT = 1 to 16, R1 = 6.8 k5%, C1 = 82 pF5% -- Min. 3.0 VDD-42 0.8 VDD -- -- 1.4 170 -40 Typ. 3.3 -- -- -- -- 2.0 244 -- Max. 3.6 VDD-20 -- 0.2 VDD 2.0 2.6 318 85 Unit V V V V MHz MHz Hz C
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ELECTRICAL CHARACTERISTICS
DC Characteristics-1
(VDD = 5.0 V10%, VFL = VDD - 42 V, Ta = -40 to +85C, unless otherwise specified) Parameter High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Symbol VIH VIL IIH IIL Applied pin CS, CP, DA, RESET CS, CP, DA, RESET CS, CP, DA, RESET CS, CP, DA, RESET COM1-16 AD1-2 SEG1-16 COM1-16 AD1-2 SEG1-16 Condition -- -- VIH = VDD VIL = 0.0 V Min. 0.7 VDD -- -1.0 -1.0 Max. -- 0.3 VDD 1.0 1.0 Unit V V A A
High Level Output Voltage
VOH1 VOH2 VOH3
IOH1 = -30 mA IOH2 = -15 mA IOH3 = -6 mA -- Duty = 15/16 Digit =1-16 All output lights ON Duty = 0/16 Digit = 1-8 All output lights OFF
VDD - 1.5 VDD - 1.5 VDD - 1.5 --
-- -- -- VFL + 1.0
V V V V
Low Level Output Voltage
VOL1
IDD1
--
4
mA
Supply Current
IDD2
VDD
fOSC = 2 MHz, no load
--
3
mA
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DC Characteristics-2
(VDD = 3.3 V10%, VFL = VDD - 42 V, Ta = -40 to +85C, unless otherwise specified) Parameter High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Voltage Low Level Output Voltage Symbol VIH VIL IIH IIL VOH1 VOH2 VOH3 VOL1 Applied pin CS, CP, DA, RESET CS, CP, DA, RESET CS, CP, DA, RESET CS, CP, DA, RESET COM1-16 AD1-2 SEG1-16 COM1-16 AD1-2 SEG1-16 Condition -- -- VIH = VDD VIL = 0.0 V IOH1 = -30 mA IOH2 = -15 mA IOH3 = -6 mA -- Duty = 15/16 Digit =1-16 All output lights ON Duty = 0/16 Digit = 1-8 All output lights OFF Min. 0.8 VDD -- -1.0 -1.0 VDD - 1.5 VDD - 1.5 VDD - 1.5 -- Max. -- 0.2 VDD 1.0 1.0 -- -- -- VFL + 1.0 Unit V V A A V V V V
IDD1
--
3
mA
Supply Current
IDD2
VDD
fOSC = 2 MHz, no load
--
2
mA
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AC Characteristics-1
(VDD = 5.0 V10%, VFL = VDD - 42 V, Ta = -40 to +85C, unless otherwise specified) Parameter CP Frequency CP Pulse Width DA Setup Time DA Hold Time CS Setup Time CS Hold Time CS Wait Time Data Processing Time RESET Pulse Width RESET Time DA Wait Time All Driver Output Slew Rate Symbol fC tCW tDS tDH tCSS tCSH tCSW tDOFF tWRES tRSON tRSOFF tR tF Condition -- -- -- -- -- R1 = 8.2 k5%, C1 = 82 pF5% -- R1 = 8.2 k5%, C1 = 82 pF5% -- -- -- Cl = 100 pF tR = 20 to 80% tF = 80 to 20% Min. -- 250 250 250 250 16 250 8 250 250 250 -- -- Max. 2.0 -- -- -- -- -- -- -- -- -- -- 2.0 2.0 Unit MHz ns ns ns ns s ns s ns ns ns s s
AC Characteristics-2
(VDD = 3.3 V10%, VFL = VDD - 42 V, Ta = -40 to +85C, unless otherwise specified) Parameter CP Frequency CP Pulse Width DA Setup Time DA Hold Time CS Setup Time CS Hold Time CS Wait Time Data Processing Time RESET Pulse Width RESET Execution Time DA Wait Time All Driver Output Slew Rate Symbol fC tCW tDS tDH tCSS tCSH tCSW tDOFF tWRES tRSON tRSOFF tR tF Condition -- -- -- -- -- R1 = 6.8 k5%, C1 = 82 pF5% -- R1 = 6.8 k5%, C1 = 82 pF5% -- -- -- Cl = 100 pF tR = 20 to 80% tF = 80 to 20% Min. -- 250 250 250 250 16 250 8 250 250 250 -- -- Max. 2.0 -- -- -- -- -- -- -- -- -- -- 2.0 2.0 Unit MHz ns ns ns ns s ns s ns ns ns s s
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TIMING DIAGRAMS
1) Data Input Timing
Symbol VIH VIL
tCSS
VDD = 3.3 V 10% 0.8 VDD 0.2 VDD
VDD = 5.0 V 10% 0.7 VDD 0.3 VDD
VIH VIL fC tCSH tCW VIH VIL VIH VIL
CS
tDOFF tDS DA VALID VALID tDH VALID VALID tCW
tCSW
CP
2) Data Input Timing
0.8 VDD 0.0 V tWRES tRSOFF VIH 0.5 VDD VIL VIH VIL
VDD
tRSON
RESET
DA
3) Output Timing
tR tF 0.8 VDD 0.2 VFL
All driver outputs
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4) Digit Output Timing (16-Digit, 15/16-Duty)
T=8x 1 fOSC
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 AD1-2 SEG1-16
Frame cycle t1 = 1024T (fosc = 2.0 MHz, t1= 4.096 ms) Display timing t2 = 60T (fosc = 2.0 MHz, t2 = 240 s) (fosc = 2.0 MHz, t3 = 16 s) Blank timing t3 = 4T
VDD VFL
VDD VFL
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FUNCTIONAL DESCRIPTION
Command List
Command 1 DCRAM data write 2 CGRAM data write 3 ADRAM data write
LSB
First byte MSB LSB Second byte B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 X0 X1 X2 X3 1 0 0 0 C0 C1 C2 C3 C4 C5 C0 C1 C2 C3 C4 C5 X0 X1 X2 X3 0 1 0 0 C8 C9 C10 C11 C12 C13 1 1 0 1 1 0 1 1 0 1 1 1 0 0 0 0 C0 C1 *
Xn Cn Dn Kn H L
MSB
B6 C6 C6
B7 C7 C7
2nd byte
C14 C15 3rd byte * *
XXXX 0123 5 Display duty set D0 D1 D2 D3 6 Number of digits set K0 K1 K2 K3 All display lights 7 LH* * ON/OFF Others (test mode)
*
*
*
*
: Don't care : Address setting for each RAM : Character code setting for each RAM : Display duty setting : Setting of the number of display digits : All display lights ON setting : All display lights OFF setting
When data is written to RAM (DCRAM, CGRAM, and ADRAM) continuously, addresses are internally incremented automatically. Therefore it is not necessary to specify the 1st byte to write RAM data for the 2nd and subsequent bytes. Note: The test mode is used for inspection before shipment. It is not a user function.
Positional Relationship Between SEGn and ADn (one digit)
C0 SEG1 C7 SEG8 C15 SEG16 C8 SEG9 C1 SEG2 C9 SEG10 C2 SEG3 C3 SEG4
C14 SEG15 C6 SEG7 C13 SEG14 C12 SEG13
C10 SEG11 C11 SEG12 C4 SEG5
C5 SEG6
C0-7: Corresponds to the 2nd byte of the CGRAM data write command.
C8-15: Corresponds to the 3rd byte of the CGRAM data write command.
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Data Transfer Method and Command Write Method Display control command and data are written by an 8-bit serial transfer. Write timing is shown in the figure below. Setting the CS pin to "Low" level enables a data transfer. Data is 8 bits and is sequentially input into the DA pin from LSB (LSB first). As shown in the figure below, data is read by the shift register at the rising edge of the shift clock, which is input into the CP pin. If 8-bit data is input, internal load signals are automatically generated and data is written to each register and RAM. Therefore it is not necessary to input load signals from the outside. Setting the CS pin to "High" disables data transfer. Data input from the point when the CS pin changes from "High" to "Low" is recognized in 8-bit units.
CS CP
tDOFF
tCSH
B0 B1B2 B3 B4 B5 B6 B7 DA LSB
When data is written to DCRAM(*1)
B0 B1B2 B3 B4 B5 B6 B7 LSB 2nd byte MSB
B0 B1B2 B3 B4 B5 B6 B7 LSB 3rd byte MSB
1st byte
MSB
Command and address data
Character code data
Character code data of the next address
*1 When data is written to RAM (DCRAM, CGRAM, ADRAM) continuously, addresses are internally incremented automatically. Therefore it is not necessary to specify the 1st byte to write RAM data for the 2nd and subsequent bytes.
Reset Function Reset is executed when the RESET pin is set to "L", (when turning power on, for example) and initializes all functions. Initial status is as follows. * * * * * * * Address of each RAM ..................... Address 00H Data of each RAM .......................... All contents are undefined. Number of display digits ................. 16 digits Brightness adjustment..................... 0/16 All display lights ON or OFF .......... OFF mode Segment output ............................... All segment outputs go "Low." AD output....................................... All AD outputs go "Low."
Be sure to execute the reset operation when turning power on and set again according to "Setting Flowchart" after reset.
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Description of Commands and Functions 1. "DCRAM data write" command (Specifies the address of DCRAM and writes the character code of CGROM and CGRAM.) DCRAM (Data Control RAM) has a 4-bit address to store character codes of CGROM and CGRAM. A character code specified by DCRAM is converted to an alphanumeric character pattern via CGROM or CGRAM. The DCRAM can store 16 characters worth of character codes.
[Command format]
LSB MSB B0 B1 B2 B3 B4 B5 B6 B7 1st byte (1st) X0 X1 X2 X3 1 0 0 0 : Setup and DCRAM address in the write mode of DCRAM data are specified. LSB MSB B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (2nd) C0 C1 C2 C3 C4 C5 C6 C7 (Example: Specify DCRAM address 0H.) : Specify character code of CGROM and CGRAM. (It is written into DCRAM address 00H.)
To specify the character code of CGROM and CGRAM to the next address continuously, specify only character code as follows. Since the address of DCRAM is automatically incremented, address specification is unnecessary.
LSB MSB B0 B1 B2 B3 B4 B5 B6 B7 2nd byte C0 C1 C2 C3 C4 C5 C6 C7 : (3rd) LSB MSB B0 B1 B2 B3 B4 B5 B6 B7 2nd byte C0 C1 C2 C3 C4 C5 C6 C7 : (4th) LSB MSB B0 B1 B2 B3 B4 B5 B6 B7 2nd byte C0 C1 C2 C3 C4 C5 C6 C7 : (17th) LSB MSB B0 B1 B2 B3 B4 B5 B6 B7 2nd byte C0 C1 C2 C3 C4 C5 C6 C7 : (18th) Specify character code of CGROM and CGRAM. (It is written into DCRAM address FH.) Specify character code of CGROM and CGRAM. (It is written into DCRAM address 1H.)
Specify character code of CGROM and CGRAM. (It is written into DCRAM address 2H.)
Specify character code of CGROM and CGRAM. (It is rewritten into DCRAM address 0H.)
X0 (LSB) to X3 (MSB): DCRAM address (4 bits: 16 characters worth) C0 (LSB) to C7 (MSB): Character code of CGROM and CGRAM (8 bits: 256 characters worth)
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[Relationship between DCRAM addresses setup and COM positions]
HEX 0 1 2 3 4 5 6 7 X0 0 1 0 1 0 1 0 1 X1 0 0 1 1 0 0 1 1 X2 0 0 0 1 1 1 1 1 X3 0 0 0 0 0 0 0 0 COM position COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 HEX 8 9 A B C D E F X0 0 1 0 1 0 1 0 1 X1 0 0 1 1 0 0 1 1 X2 0 0 0 0 1 1 1 1 X3 1 1 1 1 1 1 1 1 COM position COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16
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2. "CGRAM data write" command (Specifies the address of CGRAM and writes character pattern data.) CGRAM (Character Generator RAM) has a 4-bit address to store alphanumeric character patterns. A character pattern stored in CGRAM can be displayed by specifying the character code (address) by DCRAM. The addresses of CGRAM are assigned to 00H to 0FH (All the other addresses are the CGROM addresses). The CGRAM can store 16 types of character patterns. [Command format]
LSB MSB B0 B1 B2 B3 B4 B5 B6 B7 : Setup and CGRAM address in the write-in mode of CGRAM data are specified. LSB MSB (Example: Specify CGRAM address 00H.) B0 B1 B2 B3 B4 B5 B6 B7 2nd byte C0 C1 C2 C3 C4 C5 C6 C7 : Specify 1st-column data. (2nd) (It is written into CGRAM address 00H.) 0 1 0 0 LSB MSB B0 B1 B2 B3 B4 B5 B6 B7 3rd byte C8 C9 C10C11 C12 C13 C14C15 : Specify 2nd-column data. (3rd) (It is written into CGRAM address 00H.) 1st byte X0 X1 X2 X3 (1st)
To specify character pattern data continuously to the next address, specify only character pattern data as follows. Since the address of CGRAM is automatically incremented, address specification is unnecessary. Data from the 2nd to 6th byte (character pattern) is regarded as one data item taken together, so 250 ns is sufficient for tDOFF time between bytes.
LSB MSB B0 B1 B2 B3 B4 B5 B6 B7 2nd byte C0 C1 C2 C3 C4 C5 C6 C7 : Specify 1st-column data. (4th) (It is written into CGRAM address 01H.) LSB MSB B0 B1 B2 B3 B4 B5 B6 B7 3rd byte C8 C9 C10 C11C12 C13 C14C15 : Specify 2nd-column data. (5th) (It is written into CGRAM address 01H.)
X0 (LSB) to X3 (MSB): CGRAM address (4 bits: 16 characters worth) C0 (LSB) to C15 (MSB): Character data of CGRAM (16 bits: 16 outputs per digit)
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[Positional relationship between CGRAM addresses setup and CGROM addresses]
HEX 0 1 2 3 4 5 6 7 X0 0 1 0 1 0 1 0 1 X1 0 0 1 1 0 0 1 1 X2 0 0 0 1 1 1 1 1 X3 0 0 0 0 0 0 0 0 CGROM address RAM00 RAM01 RAM02 RAM03 RAM04 RAM05 RAM06 RAM07 HEX 8 9 A B C D E F X0 0 1 0 1 0 1 0 1 X1 0 0 1 1 0 0 1 1 X2 0 0 0 0 1 1 1 1 X3 1 1 1 1 1 1 1 1 CGROM address RAM08 RAM09 RAM0A RAM0B RAM0C RAM0D RAM0E RAM0F
Refer to the ROM Code Tables attached later in this document.
Positional Relationship Between CGROM and CGRAM outputs
C0 SEG1 C7 SEG8 C8 SEG9 C15 SEG16 C1 SEG2 C9 SEG10 C10 SEG11 C12 SEG13 C11 SEG12 C4 SEG5 C3 SEG4 C2 SEG3
C14 SEG15 C6 SEG7 C13 SEG14 C5 SEG6
C0-7: Corresponds to the 2nd byte of the CGRAM data write command.
C8-15: Corresponds to the 3rd byte of the CGRAM data write commnad.
*On CGROM A CGROM (Character Generator ROM) has an 8-bit address to generate alphanumeric type matrix character patterns. It has a capacity of 240 x 16 bits and can store 240 types of character patterns.
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3. "ADRAM data write" command (Specifies the address of ADRAM and writes symbol data) ADRAM (Additional Data RAM) has a 2-bit address to store symbol data. Symbol data specified by ADRAM is directly output without CGROM and CGRAM. (The ADRAM can store two types of symbol patterns for each digit.) The terminal to which the contents of ADRAM are output can be used as a cursor. [Command format]
LSB MSB B0 B1 B2 B3 B4 B5 B6 B7 1st byte : Setup and DCRAM address in the write-in mode of X0 X1 X2 X3 1 1 0 0 (1st) DCRAM data are specified. LSB MSB (Example: Specify ADRAM address 0H.) B0 B1 B2 B3 B4 B5 B6 B7 2nd byte : Specify symbol data. C0 C1 * * * * * * (2nd) (Example: Specify ADRAM address 0H.)
To specify symbol data continuously to the next address, specify only symbol data as follows. Since the address of ADRAM is automatically incremented, address specification is unnecessary.
LSB B0 B1 B2 B3 B4 B5 B6 2nd byte C0 C1 * * * ** (3rd) LSB B0 B1 B2 B3 B4 B5 B6 2nd byte C0 C1 * * * ** (4th) LSB B0 B1 B2 B3 B4 B5 B6 2nd byte C0 C1 * * * ** (17th) LSB B0 B1 B2 B3 B4 B5 B6 2nd byte C0 C1 * * * ** (18th) MSB B7 * MSB B7 * MSB B7 * MSB B7 * : Specify symbol data. (It is rewritten into ADRAM address 0H.) : Specify symbol data. (It is written into ADRAM address FH.) : Specify symbol data. (It is written into ADRAM address 2H.) : Specify symbol data. (It is written into ADRAM address 1H.)
X0 (LSB) to X3 (MSB) : ADRAM address (4 bits: 16 characters worth) C0 (LSB) to C1 (MSB) : Symbol data (2 bits: 2 symbols per digit) * : Don't care
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[Relationship between ADRAM addresses setup and COM positions]
HEX 0 1 2 3 4 5 6 7 X0 0 1 0 1 0 1 0 1 X1 0 0 1 1 0 0 1 1 X2 0 0 0 1 1 1 1 1 X3 0 0 0 0 0 0 0 0 COM positions COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 HEX 8 9 A B C D E F X0 0 1 0 1 0 1 0 1 X1 0 0 1 1 0 0 1 1 X2 0 0 0 0 1 1 1 1 X3 1 1 1 1 1 1 1 1 COM positions COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16
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5. "Display duty set" command (Writes display duty value into the duty cycle register.) For display duty, brightness can be adjusted in 16 stages using 4-bit data. When power is turned on or when the RESET signal is input, the duty cycle register value is "0". execute this command before turning the display on, then set a desired duty value. [Command format]
LSB MSB B0 B1 B2 B3 B4 B5 B6 B7 1st byte D0 D1 D2 D3 1 0 1 0 : setup and duty value in display duty specification mode are specified.
Always
D0 (LSB) to D3 (MSB) : Display duty data (4 bits: 16 stages worth)
[Relation between setup data and controlled COM duty]
HEX 0 1 2 3 4 5 6 7 D0 0 1 0 1 0 1 0 1 D1 0 0 1 1 0 0 1 1 D2 0 0 0 0 1 1 1 1 D3 0 0 0 0 0 0 0 0 COM duty 0/16 1/16 2/16 3/16 4/16 5/16 6/16 7/16 HEX 0 1 2 3 4 5 6 7 D0 0 1 0 1 0 1 0 1 D1 0 0 1 1 0 0 1 1 D2 0 0 0 0 1 1 1 1 D3 1 1 1 1 1 1 1 1 COM duty 8/16 9/16 10/16 11/16 12/16 13/16 14/16 15/16
* The state when power is turned on or when the RESET signal is input.
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6. "Number of display digits set" command (Writes the number of display digits into the number-of-display-digits register.) For the number of display digits, 1 to 16 digits can be specified using 4-bit data. When power is turned on or when a RESET signal is input, the number-of-display-digits register value is "0". Always execute this command before turning the display on, then set a desired value. [Command format]
LSB MSB B0 B1 B2 B3 B4 B5 B6 B7 1st byte K0 K1 K2 K3 0 1 1 0 : Setup in display digits specification mode and digits value is specified.
K0 (LSB) to K3 (MSB) : Data of the number of display digits (4 bits: 16 digits worth)
[Relation between data to be set and the number of digits of COM to be controlled]
HEX 0 1 2 3 4 5 6 7 D0 0 1 0 1 0 1 0 1 D1 0 0 1 1 0 0 1 1 D2 0 0 0 0 1 1 1 1 D3 0 0 0 0 0 0 0 0 No. of digits of COM COM1-16 COM1 COM1-2 COM1-3 COM1-4 COM1-5 COM1-6 COM1-7 HEX 0 1 2 3 4 5 6 7 D0 0 1 0 1 0 1 0 1 D1 0 0 1 1 0 0 1 1 D2 0 0 0 0 1 1 1 1 D3 1 1 1 1 1 1 1 1 No. of digits of COM COM1-18 COM1-9 COM1-10 COM1-11 COM1-12 COM1-13 COM1-14 COM1-15
* The state when power is turned on or when the RESET signal is input.
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7. "All display lights ON" and "All display lights OFF" commands (Turns the entire display ON and OFF, respectively.) All display lights ON is used primarily for display testing. All display lights OFF is primarily used for display blink and to prevent false display upon power-on.
[Command format]
LSB MSB B0 B1 B2 B3 B4 B5 B6 B7 LH**1110 : Select all display lights ON or OFF and specify their operation. L: All display lights OFF H: All display lights ON * : Don't Care
1st byte
[Data to be setup and display state of SEG and AD]
L 0 1 0 1 H 0 0 1 1 Display state of SEG and AD Normal display Sets all outputs to Low Sets all outputs to High Sets all outputs to High
* The state when power is turned on or when RESET signal is input * Priority is given to the All display lights ON command.
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Setting Flowchart (Power applying included)
Apply VDD
Apply VFL
All display lights OFF
* Status of all outputs by RESET signal input
Setup of the number display digits
Setup of display duty * Select a RAM to be used.
DCRAM data write mode (including address setting)
Address is incremented automatically
CGRAM data write mode (including address setting)
Address is incremented automatically
ADRAM data write mode (including address setting)
Address is incremented automatically
DCRAM character code
CGRAM character code
ADRAM character code
NO
DCRAM character code write ended? YES
NO
CGRAM character code write ended? YES
NO
ADRAM character code write ended? YES
YES
Another RAM to be set? NO
Release all display lights OFF mode
* Display operation active
End of Setting
Power-off Flowchart
Display operation active
Turn off VFL
Turn off VDD
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NOTE ON APPLYING POWER
To prevent the IC from malfunctioning, turn on the logic power supply first, and then turn on the driver power supply when applying power. Also, for power-off, turn off the driver power supply first, then turn off the logic power supply.
5V or 3.3V
VDD
2.0s max.
2.0s max.
VFL
VDD - 42V
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APPLICATION CIRCUIT
Heater transformer Alphanumeric fluorescent display tubes
ANODE ANODE GRID (SEGMENT) (SEGMENT) (DIGIT) VDD 2 VDD Microcontroller Output port C4 GND RESET CS CP DA VDD AD1-2 16 16 SEG1-16 COM1-16
VDD
C2
ML9209-01
GND VFL
OSC0 R1 C1 GND
VDD
VFL
C3
GND ZD
R2
Notes: 1. The VDD voltage depends on the power supply voltage of the microcontroller used. constants R1 and C1 to the power supply voltage used. 2. The VFLvoltage depends on the vacuum fluorescent display tube used. and ZD to the voltage used.
Adjust the value of the
Adjust the value of the constants R2
Reference data Shown below is a chart showing the VFL voltage vs. output current of each driver. Care must be taken that the entire power consumption will not exceed the power dissipation.
-30 -25 Output Current (mA) -20 -15
COM1-COM16 (Condition: VOH = VDD - 1.5 V)
AD1-AD2 -10 -5 0 -17 (Condition: VOH = VDD - 1.5 V) SEG1-SEG16 (Condition: VOH = VDD - 1.5 V) -22 -27 -32 -37 -42 (V)
VFL Voltage (VDD - n)
VFL Voltage vs. Output Current of Each Driver
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ML9209-01 ROM CODE
*ROM CODE_A is the character set for SEGA1 to SEGA16. *00000000b(00h) to 00001111b(0Fh) are the CGRAM_A addresses
MSB LSB
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
RAM
0001
RAM
0010
RAM
0011
RAM
0100
RAM
0101
RAM
0110
RAM
0111
RAM
1000
RAM
1001
RAM
1010
RAM
1011
RAM
1100
RAM
1101
RAM
1110
RAM
1111
RAM
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16 Segment design
MSB LSB
14 Segment design 0010 0011 0100 0101 0110 0111 0001 0010 0011 0100
7 Segment design 0111
0000
0001
0000
RAM
0001
RAM
0010
RAM
0011
RAM
0100
RAM
0101
RAM
0110 RAM
0111 RAM
1000
RAM
1001
RAM
1010
RAM
1011
RAM
1100
RAM
1101
RAM
1110 RAM
1111 RAM
SEG1
SEG8 SEG9
SEG2
SEG8
SEG1
SEG9 SEG3 SEG6 SEG3
SEG1
SEG2
SEG16 SEG15
SEG10 SEG11
SEG16 SEG15
SEG10 SEG11
SEG7
SEG4 SEG5 SEG3
SEG13
SEG7
SEG14 SEG6
SEG12 SEG5
SEG14
SEG13
SEG4
SEG7
SEG12
SEG6
SEG4
16 Segment
14 Segment
7 Segment
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PACKAGE DIMENSIONS
(Unit: mm)
QFP44-P-910-0.80-2K
5
Notes for Mounting the Surface Mount Type Package
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Sn/Pb 0.41 TYP. 5/Nov. 20, 2002
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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REVISION HISTORY
Document No.
FEDL9209-01
Date
Oct. 20, 2004
Page Previous Current Edition Edition
Final edition 1
Description
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NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2004 Oki Electric Industry Co., Ltd.
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