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OKI Semiconductor ML9042-xx
DOT MATRIX LCD CONTROLLER DRIVER
FEDL9042-01
Issue Date: Nov. 19, 2003
GENERAL DESCRIPTION
The ML9042 used in combination with an 8-bit or 4-bit microcontroller controls the operation of a character type dot matrix LCD.
FEATURES
* * * * * * * * * * * * * * * * * Easy interfacing with an 8-bit or 4-bit microcontroller Switchable between serial and parallel interfaces Dot-matrix LCD controller driver for a 5 x 8 dot font Built-in circuit allowing automatic resetting at power-on Built-in 17 common signal drivers and 100 segment signal drivers Two built-in character generator ROMs each capable of generating 240 characters (5 x 8 dots) The character generator ROM can be selected by bank switching (ROM1S) pin. Creation of character patterns by programming: up to 8 character patterns (5 x 8 dots) Built-in RC oscillation circuit using external or internal resistors Program-selectable duties When ABE bit is "L": 1/8 duty (1 line: 5 x 8 dots), or 1/16 duty (2 lines: 5 x 8 dots) When ABE bit is "H": 1/9 duty (1 line: 5 x 8 dots + arbitrator), or 1/17 duty (2 lines: 5 x 8 dots + arbitrator) Cursor display Built-in bias dividing resistors to drive the LCD Bi-directional transfer of segment outputs Bi-directional transfer of common outputs 100-dot arbitrator display Line display shifting Built-in voltage multiplier circuit Gold Bump Chip ML9042-xx CVWA/DVWA *xx indicates a character generator ROM code number. *01, 11 and 21 indicate general character generator ROM code numbers. CVWA indicates a bump chip with high hardness, and DVWA indicates a bump chip with low hardness.
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VDD GND
OSC1
OSCR3 7
17-bit
OKI Semiconductor
OSCR5 COM1 COM17
bi-directional shift register
Timing generator Cursor blink controller Common signal driver
BLOCK DIAGRAM
OSC2
RS1 8 Parallelserial converter
8
RS0/CSB RW/SI E/SHTB SP
Instruction register (IR)
Instruction decoder (ID)
Character generator
5 RAM (CG RAM) 5 8
I/O Buffer
SEG1
DB0(SO) to DB3 8 Address counter (ADC) Display data RAM (DD RAM) 5 Arbitrator RAM (AB RAM) 8 ROM (CG ROM)
4
8
DB4 to DB7
4
Data register (DR)
Character generator
100-bit latch
T1 T2
Test circuit
Segment Signal driver
T3
8
Busy flag (BF) 8 Expansion instruction register (ED)
100-bit bi-directional shift register
V4 V3B V3A V2 V1
LCD bias voltage dividing circuit
Expansion instruction register (ER)
SEG100
V0
Voltage multiplier circuit
VOUT VIN BE
ROM1S
FEDL9042-01
ML9042-xx
VCC VC
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I/O CIRCUITS
VDD
VDD
VDD P
P N
N
Applied to pins T1, T2, and T3
Applied to pins RW/SI, RS1, and RS0/CSB
Applied to pins E/SHTB, SP, ROM1S, and BE
VDD
VDD
P
P VDD N P
N Output Enable signal Applied to pins DB0(SO) to DB7
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PIN DESCRIPTIONS
Symbol
Description The input pin with a pull-up resistor to select Read ("H") or Write ("L") in the Parallel I/F Mode. The pin to input data in the Serial l/F Mode. Each instruction code and each data are read in by the rising edge of the E/SHTB signal. The input pins with a pull-up resistor to select a register in the Parallel l/F Mode. RS1 H RS0/CSB H L L Name of register Data register Instruction register Expansion Instruction register
RW/SI
RS0/CSB, RS1
H L
The RSo/CSB pin is configured as a chip enable input in the Serial I/F Mode. Setting the RSo/CSB pin to "L" allows the I/F to be provided. The input pin for data input/output between the CPU and the ML9042 and for activating instructions in the Parallel l/F Mode. E/SHTB This pin is configured as a shift clock input in the Serial I/F Mode. The data input to the PW/SI pin is synchronized to the rising edge of the clock, and the data output from the DB0(SO) pin is synchronized to the falling edge of the shift clock. The input/output pins to transfer data of lower-order 4 bits between the CPU and the ML9042 in the Parallel l/F Mode. The pins are not used for the 4-bit interface. DB0(SO) to DB3 Only the DB0(SO) pin is configured as a data output in the Serial I/F Mode. Busy flag & address and data are output synchronized to the falling edge of the E/SHTB signal. These pins remain pulled up when data is not output. Each pin is equipped with a pull-up resistor, so this pin should be open when not used. The input/output pins to transfer data of upper 4 bits between the CPU and the ML9042 in the Parallel l/F Mode. The pins are not used for the serial interface. Each pin is equipped with a pull-up resistor, so this pin should be open in the Serial I/F Mode when not used. The clock oscillation pins required for LCD drive signals and the operation of the ML9042 by instructions sent from the CPU. To input external clock, the OSC1 pin should be used. The OSCR3, OSCR5, and OSC2 pins should be open. OSC1 OSC2 OSCR3 OSCR5 To start oscillation with an external resistor, the resistor should be connected between the OSC1 and OSC2 pins. The OSCR3 and OSCR5 pins should be open. To start oscillation at 5 V using an internal resistor, the OSC2 and OSCR5 pins should be short-circuited outside the ML9042. The OSC1 and OSCR3 pins should be open. To start oscillation at 3 V using an internal resistor, the OSC2 and OSCR3 pins should be short-circuited outside the ML9042. The OSC1 and OSCR5 pins should be open. (The OSC2, OSCR3, and OSCR5 pins can also be short-circuited outside the ML9042, and the OSC1 pin can be open.) The LCD common signal output pins. COM1 to COM17 For 1/8 duty, non-selectable voltage waveforms are output via COM9 to COM17. For 1/9 duty, non-selectable voltage waveforms are output via COM10 to COM17. For 1/16 duty, a non-selectable voltage waveform is output via COM17. The LCD segment signal output pins.
DB4 to DB7
SEG1 to SEG100
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Symbol ROM1S
Description The input pin to switch the ROM bank. "H" selects ROM1 and "L" selects ROM0. Switching after power-on is prohibited. The pins to output bias voltages to the LCD. For 1/4 bias : The V2 and V3B pins are shorted. For 1/5 bias : The V3A and V3B pins are shorted. The input pin to enable or disable the voltage multiplier circuit. "L" disables the voltage multiplier circuit. "H" enables the voltage multiplier circuit. The voltage multiplier circuit doubles the input voltage between the VIN pin and the GND pin, and the multiplied voltage referenced to the GND is output to the VOUT pin. The voltage multiplier circuit can be used only when generating a level higher than the VDD. The input pin for test circuits. Normally connect this pin to VDD. The output pin for the test circuits. Normally leave this pin open. The pin to input voltage to the voltage multiplier. The pins to supply the LCD drive voltage. The same potential as the VDD potential is supplied to the VOUT and V0 pins when the voltage multiplier is not used (BE = "0" or BE = "1", and the capacitor is not connected to the VC and VCC pins) When the voltage multiplier is used (BE = "1"), the multiplied voltage is output to the VOUT pin, so that the VOUT pin and V0 pin should be connected. Capacitors for the voltage multiplier should be connected between the GND and the VOUT pin.
V1 , V2, V3A, V3B, V4
BE
TESTIN TESTOUT VIN
V0, VOUT
VC VCC T 1, T 2, T 3 VDD GND SP
The pin to connect the negative pin of the capacitor for the voltage multiplier. Leave the pin open when the voltage multiplier circuit is not used. The pin to connect the positive pin of the capacitor used for the voltage multiplier. Leave the pin open when the voltage multiplier circuit is not used. The input pins for test circuits (normally open). Each of these pins is equipped with a pull-down resistor, so this pin should be left open. The power supply pin. The ground level input pin. The input pin to select the serial or parallel interface. "L" selects the parallel interface. "H" selects the serial interface. The output pin to fix the adjacent input pin to the VDD level. Use this pin only for this purpose. The output pin to fix the adjacent input pin to the GND level. Use this pin only for this purpose. NC (No Connection) pin.
DUMMYVDD DUMMYGND DUMMY
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ABSOLUTE MAXIMUM RATINGS
(GND = 0 V) Parameter Supply Voltage LCD Driving Voltage Symbol VDD V0, V1, V2, V3, V4, Condition Ta = 25C Ta = 25C Rating -0.3 to +6.5 -0.3 to +6.5 Unit V V Applicable pins VDD VOUT, V0, V1, V2, V3A, V3B, V4, GND RW/SI, E/SHTB, SP, RS0/CSB, RS1, BE, ROM1S, T1 to T3, DB0(SO) to DB7, VIN --
Input Voltage
VI
Ta = 25C
-0.3 to VDD+0.3
V C
Storage Temperature
TSTG
--
-55 to +150
RECOMMENDED OPERATING CONDITIONS
(GND = 0 V) Parameter Supply Voltage LCD Driving Voltage Voltage Multipler Input Voltage Operating Temperature Symbol VDD V0 (See Note) VMUL Top Condition -- -- BE = "1" -- Range 2.7 to 5.5 2.7 to 5.5 1.8 to 2.75 -40 to +85 Unit V V V C Applicable pins VDD VOUT, V0 VIN --
Note:
This voltage should be applied across V0 and GND. The following voltages are output to the V1, V2, V3A (V3B) and V4 pins: * 1/4 bias (V2 and V3B are short-circuited) V1 =3 V0/4 0.15 V V2 = V3B = V0/2 0.15 V V4 = V0/4 0.15 V * 1/5 bias (V3A and V3B are short-circuited) V1 = 4 V0/5 0.15 V V2 = 3 V0/5 0.15 V V3A = V3B = 2 V0/5 0.15 V V4 = V0/5 0.15 V The voltages at the V0, V1, V2, V3A (V3B), V4 and GND pins should satisfy V0 > V1 > V2 > V3A (V3B) > V4 > GND (Higher Lower) * If the chip is attached on a substrate using COG technology, the chip tends to be susceptible to electrical characteristics of the chip due to trace resistance on the glass substrate. It is recommended to use the chip by confirming that it operates on the glass substrate properly. Trace resistance, especially, VDD and VSS trace resistance, between the chip on the LCD panel and the flexible cable should be designed as low as possible. Trace resistance that cannot be very well decreased, larger size of the LCD panel, or greater trace capacitance between the microcontroller and the ML9042 device can cause device malfunction. In order to avoid the device malfunction, power noise should be reduced by serial interfacing of the microcontroller and the ML9042 device. * Do not apply short-circuiting across output pins and across an output pin and an input/output pin or the power supply pin in the output mode.
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ELECTRICAL CHARACTERISTICS
DC Characteristics
(GND = 0 V, VDD = 2.7 to 5.5 V, Ta = -40 to +85C) Parameter "H" Input Voltage Symbol VIH -- "L" Input Voltage VIL 0 -- 0.2VDD Condition Min. 0.8VDD Typ. -- Max. VDD V Unit Applicable pin RW/SI, RS0/CSB, RS1, E/SHTB, DB0(SO) to DB7, SP, OSC1, BE, ROM1S DB0(SO) to DB7 OSC2
"H" Output Voltage 1 "L" Output Voltage 1 "H" Output Voltage 2 "L" Output Voltage 2
VOH1 VOL1 VOH2 VOL2 VCH VCMH
IOH = -0.1 mA IOL = +0.1 mA IOH = -13 A IOL = +13 A lOCH = -4 A lOCMH = 4 A lOCML = 4 A lOCL = +4 A lOSH = -4 A lOSMH = 4 A lOSML = 4 A lOSL = +4 A VDD = 5 V, VI = 5 V or 0 V VDD = 5 V, VI = GND
V0 -GND = 5 V V0 -GND = 5 V
0.9VDD -- 0.9VDD -- V0-0.3 V1-0.3 V4-0.3 GND V0-0.3 V2-0.3 V3-0.3 GND -- 10 -- 15 -- -- 175
-- -- -- --
V0- 0.012 V1 0.012 V4 0.012 GND+ 0.012 V0- 0.012 V2 0.012 V3 0.012 GND+ 0.012
-- 0.1VDD -- 0.1VDD V0 V1+0.3
V V
COM Voltage Drop VCML VCL VSH VSMH SEG Voltage Drop VSML VSL Input Leakage Current | IIL |
Note 1
V V4+0.3
GND+0.3
COM1 to COM17
V0 V2+0.3 V V3+0.3
GND+0.3
Note 1
SEG1 to SEG100
-- 25 -- 45 -- -- 270
1.0 61 2.0 105 2.0 1.2 400
A
E/SHTB, BE, SP, VIN RW/SI, RS0/CSB, RS1, DB0(SO) to DB7
Input Current 1
| II1 |
VDD = 5 V, VI = VDD, Excluding current flowing through the pull-up resistor and the output driving MOS VDD = 5 V, VI = VDD VDD = 5 V, VI = GND Excluding current flowing through the pull-down resistor VDD = 5 V Note 2 Rf = 85 k2% Note 3
A
Input Current 2
| II2 |
A
T 1, T 2, T 3
Supply Current Oscillation Frequency of External Resistor Rf
lDD fosc1
mA
VDD-GND
kHz OSC1, OSC2
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Oscillation Frequency of Internal Resistor Rf
fosc2
External Clock
Clock Input Frequency Input Clock Duty Input Clock Rise Time Input Clock Fall Time
fin fduty frf fff
VDD = 4.0 to 5.5 V Ta = -20 to 75C OSC1 and OSCR3: Open OSC2 and OSCR5: Short-circuited Note 4 VDD = 2.7 to 3.6 V Ta = -20 to 75C OSC1 and OSCR5: Open OSC2 and OSCR3: Short-circuited Note 4 OSC2, OSCR: Open Input from OSC1 Note 5 Note 6 Note 6 -0x code
200
270
351
kHz
OSC1, OSC2, OSCR5
200
280
364
kHz
OSC1, OSC2, OSCR3
175 45 -- -- 1.4 2.8 7.0
-- 50 -- -- 2.0 4.0 10.0
400 55 0.2 0.2 2.6 5.2 13.0
kHz % s s k k k V0, V1, V2, V3A, V3B, V4, GND V0, V1, V2, V3A, V3B, V4, GND V0, V1, V2, V3A, V3B, V4, GND OSC1
LCD Bias Resistor
RLB
-1x code -2x code
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(GND = 0 V, VDD = 2.7 to 5.5 V, Ta = -40 to +85C) Parameter Voltage Multiplier Input Voltage Symbol VMUL Note 7 VDD = 2.7 V, VIN = 2.25 V f = 175 kHz A capacitor for the voltage multiplier = 1 to 4.7 F VOUT VOUT load current = 54 A BE = "H" Applied to LCD bias resistance of 10 k (TYP) only Bias Voltage for Driving LCD VLCD1 V0-GND VLCD2 Note 8 1/4 bias 4.3 -- (VDD-VIN) x2 V VOUT 1/5 bias Condition Min. 1.8 Typ. -- Max. 2.75 (VDD-VIN) x2 Unit V Applicable pins VIN
4.3
--
Voltage Multiplier Output Voltage
1/5 bias 1/4 bias
2.7 2.7
-- --
5.5 V 5.5 V0
Note 1:
Applied to the voltage drop occurring between any of the V0, V1, V4 and GND pins and any of the common pins (COM1 to COM17) when the current of 4 A flows in or flows out at one common pin. Also applied to the voltage drop occurring between any of the V0, V2, V3A (V3B) and GND pins and any of the segment pins (SEG1 to SEG100) when the current of 4 A flows in or flows out at one segment pin. The current of 4 A flows out when the output level is VDD or flows in when the output level is V5.
Note 2:
Applied to the current flowing into the VDD pin when the external clock (fOSC2 = fin = 270 kHz) is fed to the internal Rf oscillation or OSC1 under the following conditions: VDD = V0 = 5 V GND = 0 V, V1, V2, V3A (V3B) and V4: Open E/SHTB and BE: "L" (fixed) Other input pins: "L" or "H" (fixed) Other output pins: No load
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Note 3:
OSC1 OSC1 OSCR3 OSCR5 OSC2 Rf = 85 k2% OSCR3 OSCR5 OSC2
Note 4:
OSC1 OSCR3 OSCR5 OSC2
The wire between OSC1 and Rf and the wire between The wire between OSCR3 and OSC2, or between OSCR5 OSC2 and Rf should be as short as possible. and OSC2 should be as short as possible. Keep open Keep OSCR3 and OSCR5 open. between OSC1 and OSCR3, or between OSC1 and OSCR5.
Note 5:
tHW tLW
VDD 2 fIN waveform
VDD 2
VDD 2
Applied to the pulses entering from the OSC1 pin fduty = tHW /(tHW + tLW ) x100 (%)
Note 6:
0.8VDD 0.2VDD
0.8VDD 0.2VDD
trf
tff
Applied to the pulses entering from the OSC1 pin
Note 7:
The maximum value of the voltage multiplier input voltage should be set at 2.75 V, and the minimum value of the voltage multiplier input voltage should be set by monitoring the voltage of V0 in actual use so that the voltage multiplier output voltage meets the specification for the bias voltage for driving LCD after contrast adjustment.
Note 8:
For 1/4 bias, V2 and V3B pins are short-circuited. V3A pin is open. For 1/5 bias, V3A and V3B pins are short-circuited. V2 pin is open.
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I/O Characteristics * Parallel Interface Mode The timing for the input from the CPU and the timing for the output to the CPU are as shown below: 1) WRITE MODE (Timing for input from the CPU)
(VDD = 2.7 to 4.5 V, Ta = -40 to +85C) Parameter RW/SI, RS0/CSB, RS1 Setup Time E/SHTB Pulse Width RW/SI, RS0/CSB, RS1 Hold Time E/SHTB Rise Time E/SHTB Fall Time E/SHTB Pulse Width E/SHTB Cycle Time DB0(SO) to DB7 Input Data Setup Time DB0(SO) to DB7 Input Data Hold Time Symbol tB tW tA tr tf tL tC tI tH Min. 40 450 10 -- -- 430 1000 195 10 Typ. -- -- -- -- -- -- -- -- -- Max. -- -- -- 125 125 -- -- -- -- Unit ns ns ns ns ns ns ns ns ns
(VDD = 4.5 to 5.5 V, Ta = -40 to +85C) Parameter RW/SI, RS0/CSB, RS1 Setup Time E/SHTB Pulse Width RW/SI, RS0/CSB, RS1 Hold Time E/SHTB Rise Time E/SHTB Fall Time E/SHTB Pulse Width E/SHTB Cycle Time DB0(SO) to DB7 Input Data Setup Time DB0(SO) to DB7 Input Data Hold Time Symbol tB tW tA tr tf tL tC tI tH Min. 40 220 10 -- -- 220 500 60 10 Typ. -- -- -- -- -- -- -- -- -- Max. -- -- -- 125 125 -- -- -- -- Unit ns ns ns ns ns ns ns ns ns
RS1, RS0/CSB
VIH VIL
VIH VIL
RW/SI
VIL tB tL tr VIH VIL tI tW tf VIH VIL tH Input Data
VIL tA
E/SHTB
VIL
DB0(SO) to DB7 tC
VIH VIL
VIH VIL
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2) READ MODE (Timing for output to the CPU)
(VDD = 2.7 to 4.5 V, Ta = -40 to +85C) Parameter RW/SI, RS1, RS0/CSB Setup Time E/SHTB Pulse Width RW/SI, RS1, RS0/CSB Hold Time E/SHTB Rise Time E/SHTB Fall Time E/SHTB Pulse Width E/SHTB Cycle Time DB0(SO) to DB7 Output Data Delay Time DB0(SO) to DB7 Output Data Hold Time Symbol tB tW tA tr tf tL tC tD tO Min. 40 450 10 -- -- 430 1000 -- 20 Typ. -- -- -- -- -- -- -- -- -- Max. -- -- -- 125 125 -- -- 350 -- Unit ns ns ns ns ns ns ns ns ns
Note: A load capacitance of each of DB0(SO) to DB7 must be 50 pF or less.
(VDD = 4.5 to 5.5 V, Ta = -40 to +85C) Parameter RW/SI, RS1, RS0/CSB Setup Time E/SHTB Pulse Width RW/SI, RS1, RS0/CSB Hold Time E/SHTB Rise Time E/SHTB Fall Time E/SHTB Pulse Width E/SHTB Cycle Time DB0(SO) to DB7 Output Data Delay Time DB0(SO) to DB7 Output Data Hold Time Symbol tB tW tA tr tf tL tC tD tO Min. 40 220 10 -- -- 220 500 -- 20 Typ. -- -- -- -- -- -- -- -- -- Max. -- -- -- 125 125 -- -- 250 -- Unit ns ns ns ns ns ns ns ns ns
Note: A load capacitance of each of DB0(SO) to DB7 must be 50 pF or less.
RS1, RS0/CSB
VIH VIL
VIH VIL
RW/SI
VIH tB tL tr VIH VIL tD
0.8VDD Output 0.2VDD Data
VIH tW tf VIH VIL tO
0.8VDD 0.2VDD
tA
E/SHTB
VIL
DB0(SO) to DB7 tC
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* Serial Interface Mode
(VDD = 2.7 to 5.5 V, Ta = -40 to +85C) Parameter E/SHTB Cycle Time RS0/CSB Setup Time RS0/CSB Hold Time RS0/CSB "H" Pulse Width E/SHTB Setup Time E/SHTB Hold Time E/SHTB "H" Pulse Width E/SHTB "L" Pulse Width E/SHTB Rise Time E/SHTB Fall Time RW/Sl Setup Time RW/Sl Hold Time DB0(SO) Output Data Delay Time DB0(SO) Output Data Hold Time Symbol tSCY tCSU tCH tCSWH tSSU tSH tSWH tSWL tSR tSF tDISU tDIH tDOD tCDH Min. 500 100 100 200 60 200 200 200 -- -- 100 100 -- 0 Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. -- -- -- -- -- -- -- -- 125 125 -- -- 160 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tSCY RS0/CSB VIH VIL tSSU VIH tSWL tSR tSWH VIH tDIH VIH VIL tDOD VOH tCDH VIH tSF tSH VIH VIL VIH tCH
tCSWH VIH
tCSU E/SHTB
VIL tDISU VIH VIL tDOD
VIL
VIH
RW/SI
DB0(SO)
VOL
VOH
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FUNCTIONAL DESCRIPTION
Instruction Register (IR), Data Register (DR), and Expansion Instruction Register (ER) These registers are selected by setting the level of the Register Selection input pins RS0/CSB and RS1. The DR is selected when both RS0/CSB and RS1 are "H". The IR is selected when RS0/CSB is "L" and RS1 is "H". The ER is selected when both RS0/CSB and RS1 are "L". (When RS0/CSB is "H" and RS1 is "L", the ML9042 is not selected.) The IR stores an instruction code and sets the address code of the display data RAM (DDRAM) or the character generator RAM (CGRAM). The microcontroller (CPU) can write but cannot read the instruction code. The ER sets the display positions of the arbitrator and the address code of the arbitrator RAM (ABRAM). The CPU can write but cannot read the display positions of the arbitrator. The DR stores data to be written in the DDRAM, ABRAM and CGRAM and also stores data read from the DDRAM, ABRAM and CGRAM. The data written in the DR by the CPU is automatically written in the DDRAM, ABRAM or CGRAM. When an address code is written in the IR or ER, the data of the specified address is automatically transferred from the DDRAM, ABRAM or CGRAM to the DR. The data of the DDRAM, ABRAM and CGRAM can be checked by allowing the CPU to read the data stored in the DR. After the CPU writes data in the DR, the data of the next address in the DDRAM, ABRAM or CGRAM is selected to be ready for the next writing by the CPU. Similarly, after the CPU reads the data in the DR, the data of the next address in the DDRAM, ABRAM or CGRAM is set in the DR to be ready for the next reading by the CPU. Writing in or reading from these 3 registers is controlled by changing the status of the RW/SI pin. Table 1 RW/SI pin status and register operation
RW/SI L H L H L H L H RS0/CSB L L H H L L H H RS1 H H H H L L L L Writing in the IR Reading the Busy flag (BF) and the address counter (ADC) Writing in the DR Reading from the DR Writing in the ER Disabled (Not in a busy state, not performing the reads. Note that the data bus goes into a high impedance state.) Disabled (Not in a busy state, not performing the writes) Disabled (Not in a busy state, not performing the reads. Note that the data bus goes into a high impedance state.) Operation
Busy Flag (BF) The status "1" of the Busy Flag (BF) indicates that the ML9042 is carrying out internal operation. When the BF is "1", any new instruction is ignored. When RW/SI = "H", RS0/CSB = "L" and RS1 = "H", the data in the BF is output to the DB7. New instructions should be input when the BF is "0". When the BF is "1", the output code of the address counter (ADC) is undefined.
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Address Counter (ADC) The address counter provides a read/write address for the DDRAM, ABRAM or CGRAM and also provides a cursor display address. When an instruction code specifying DDRAM, ABRAM or CGRAM address setting is input to the pre-defined register, the register selects the specified DDRAM, ABRAM or CGRAM and transfers the address code to the ADC. The address data in the ADC is automatically incremented (or decremented) by 1 after the display data is written in or read from the DDRAM, ABRAM or CGRAM. The data in the ADC is output to DB0(SO) to DB6 when RW/SI = "H", RS0/CSB = "L", RS1 = "H" and BF = "0". Timing Generator The timing generator generates timing signals for the internal operation of the ML9042 activated by the instruction sent from the CPU or for the operation of the internal circuits of the ML9042 such as DDRAM, ABRAM, CGRAM and CGROM. Timing signals are generated so that the internal operation carried out for LCD displaying will not be interfered by the internal operation initiated by accessing from the CPU. For example, when the CPU writes data in the DDRAM, the display of the LCD not corresponding to the written data is not affected.
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Display Data RAM (DDRAM) This RAM stores the 8-bit character codes (see Table 2). The DDRAM addresses correspond to the display positions (digits) of the LCD as shown below. The DDRAM addresses (to be set in the ADC) are represented in hexadecimal.
DB6 DB5 DB4 DB3 DB2 DB1 DB0 ADC
MSB
LSB Hexadecimal
Hexadecimal (Example) Representation of DDRAM address = 12 ADC 0 0 1 1 0
0 2
1
0
1) Relationship between DDRAM addresses and display positions (1-line display mode)
Digit 12 34 5 19 20 12 13 Right end Display position DD RAM address (hexadecimal)
00 01 02 03 04 Left end
In the 1-line display mode, the ML9042 can display up to 20 characters from digit 1 to digit 20. While the DDRAM has addresses "00" to "4F" for up to 80 character codes, the area not used for display can be used as a RAM area for general data. When the display is shifted by instruction, the relationship between the LCD display position and the DDRAM address changes as shown below:
Digit 12
34
19 20 11 12
(Display shifted to the right) 4F 00 01 02
Digit 12
34
5
19 20 13 14
(Display shifted to the left) 01 02 03 04 05
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2) Relationship between DDRAM addresses and display positions (2-line display mode) In the 2-line mode, the ML9042 can display up to 40 characters (20 characters per line) from digit 1 to digit 20.
Digit 12345 Line 1 00 01 02 03 04 Line 2 40 41 42 43 44 19 20 12 13 52 53 Display position DD RAM address (hexadecimal)
Note: The DDRAM address at digit 20 in the first line is not consecutive to the DDRAM address at digit 1 in the second line. When the display is shifted by instruction, the relationship between the LCD display position and the DDRAM address changes as shown below:
Digit 12345 Line 1 27 00 01 02 03 Line 2 67 40 41 42 43 Digit 12345 Line 1 01 02 03 04 05 Line 2 41 42 43 44 45 19 20 11 12 51 52
(Display shifted to the right)
(Display shifted to the left)
19 20 13 14 53 54
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Character Generator ROM (CGROM) The CGROM generates character patterns (5 x 8 dots, 240 patterns) from the 8-bit character code signals in the DDRAM. The bank switching pin (ROM1S) can switch to the other ROM that generates character patterns (5 x 8 dots, 240 patterns), allowing a total of 480 characters to be controlled. When the 8-bit character code corresponding to a character pattern in the CGROM is written in the DDRAM, the character pattern is displayed in the display position specified by the DDRAM address. Character codes 10 to FF are contained in the ROM area in the CG ROM. The general character generator ROM codes are 01/11/21. The relationship between character codes and general purpose character patterns in Bank0 (ROM0) and Bank1 (ROM1) are indicated in Table 2-1 and Table 2-2, respectively.
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Character Generator RAM (CGRAM) The CGRAM is used to generate user-specific character patterns that are not in the CGROM. CGRAM (64 bytes = 512 bits) can store up to 8 character patterns (5 x 8 dots) . When displaying a character pattern stored in the CGRAM, write an 8-bit character code (00 to 07 or 08 to 0F; hex.) to the DDRAM. This enables outputting the character pattern to the LCD display position corresponding to the DDRAM address. The cursor or blink is also displayed even when a CGRAM or ABRAM address is set in the ADC. Therefore, the cursor or blink display should be inhibited while the ADC is holding a CGRAM or ABRAM address. The following describes how character patterns are written in and read from the CGRAM. (See Tables 2-1 and 2-2.)
(1) A method of writing character patterns to the CGRAM from the CPU The three CGRAM address bit weights 0 to 2 select one of the lines constituting a character pattern. First, set the mode to increment or decrement from the CPU, and then input the CGRAM address. Write each line of the character pattern in the CGRAM through DB0(SO) to DB7. The data lines DB0(SO) to DB7 correspond to the CGRAM data bit weights 0 to 7, respectively (see Table 3-1). Input data "1" represents the ON status of an LCD dot and "0" represents the OFF status. Since the ADC is automatically incremented or decremented by 1 after the data is written to the CGRAM, it is not necessary to set the CGRAM address again. The bottom line of a character pattern (the CGRAM address bit weights 0 to 2 are all "1", which means 7 in hexadecimal) is the cursor line. The ON/OFF pattern of this line is ORed with the cursor pattern for displaying on the LCD. Therefore, the pattern data for the cursor position should be all zeros to display the cursor. Whereas the data given by the CGRAM data bit weights 0 to 4 is output to the LCD as display data, the data given by the CGRAM data bit weights 5 to 7 is not. Therefore, the CGRAM data bit weights 5 to 7 can be used as a RAM area. (2) A method of displaying CGRAM character patterns on the LCD The CGRAM is selected when the higher-order 4 bits of a character code are all zeros. Since bit weight 3 of a character code is not used, the character pattern "0" in Table 3-1 can be selected using the character code "00" or "08" in hexadecimal. When the 8-bit character code corresponding to a character pattern in the CGRAM is written to the DDRAM, the character pattern is displayed in the display position specified by the DDRAM address. (The DDRAM data bit weights 0 to 2 correspond to the CGRAM address bit weights 3 to 5, respectively.)
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Arbitrator RAM (ABRAM) The arbitrator RAM (ABRAM) stores arbitrator display data. 100 dots can be displayed in both 1-line and 2-line display modes. The arbitrator RAM has the addresses (hexadecimal) from "00" to "1F" and the valid display address area is from 00 to 19 (0H to 13H). The area of 20 to 31 (14H to 1FH) not used for display can be used as a data RAM area for general data. Even if the display is shifted by instruction, the arbitrator display is not shifted. A capacity of 8 bits by 32 addresses (= 256 bits) is available for data write. First set the mode to increment or decrement from the CPU, and then input the ABRAM address. Write Display-ON data in the ABRAM through DB0(SO) to DB7. DB0(SO) to DB7 correspond to the ABRAM data bit weights 0 to 7 respectively. Input data "1" represents the ON status of an LCD dot and "0" represents the OFF status. Since ADC is automatically incremented or decremented by 1 after the data is written to the ABRAM, it is not necessary to set the ABRAM address again. Whereas ABRAM data bit weights 0 to 4 are output as display data to the LCD, the ABRAM data bit weights 5 to 7 are not. These bits can be used as a RAM area. The cursor or blink is also displayed even when a CGRAM or ABRAM address is set in the ADC. Therefore, the cursor or blink display should be inhibited while the ADC is holding a CGRAM or ABRAM address.
DB6 DB5 DB4 DB3 DB2 DB1 DB0 ADC
MSB LSB
Hexadecimal
Hexadecimal
The arbitrator RAM can store a maximum of 100 dots of the arbitrator Display-ON data in units of 5 dots. The relationship with the LCD display positions is shown below.
Configuration of input display data Input data DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 * * * E4 E3 E2 E1 E0 Display - ON data E4 E0 Sn = ABRAM address (0 to 19) * Don't Care Relationship between display-ON data and segment pins 5XSn+1 5XSn+5
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Note: The same CGRAM character patterns are displayed in Bank0 and Bank1.
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Table 3-1
Relationship between CGRAM address bits, CGRAM data bits (character pattern) and DDRAM data bits (character code) in 5 x 7 dot character mode. (Examples)
CG RAM CG RAM data DD RAM data address (Character pattern) (Character code) 5 4 3 2 1 0 76543210 76543210 MSB LSB MSB LSB MSB LSB 0 0 0 0 0 0 xxx 0 1 1 1 0 10001 001 10001 010 10001 011 100 10001 0000x000 101 10001 110 01110 111 00000 xxx 1 0 0 0 1 001000 10010 001 10100 010 11000 011 10100 0000x001 100 10010 101 110 10001 111 00000 1110 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 xxx 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 1 1 1 1 1 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
0000x111
x: Don't Care
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Cursor/Blink Control Circuit This circuit generates the cursor and blink of the LCD. The operation of this circuit is controlled by the program of the CPU. The cursor/blink display is carried out in the position corresponding to the DDRAM address set in the ADC (Address Counter). For example, when the ADC stores a value of "07" (hexadecimal), the cursor or blink is displayed as follows:
DB6 ADC 0 00 0 Digit 12 In 1-line display mode 34 0 DB0 111 7 567 8 9 19 20 12 13
00 01 02 03 04 05 06 07 08
Cursor/blink position Digit 12 In 2-line display mode First line
34
567
8
9
19 20 12 13 52 53
00 01 02 03 04 05 06 07 08
Second line 40 41 42 43 44 45 46 47 48
Cursor/blink position
Note:
The cursor or blink is also displayed even when a CGRAM or ABRAM address is set in the ADC. Therefore, the cursor or blink display should be inhibited while the ADC is holding a CGRAM or ABRAM address.
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LCD Display Circuit (COM1 to COM17, SEG1 to SEG100, SSR and CSR) The ML9042 has 17 common signal outputs and 100 segment signal outputs to display 20 characters (in the 1-line display mode) or 40 characters (in the 2-line display mode). The character pattern is converted into serial data and transferred in series through the shift register. The transfer direction of serial data is determined by the SSR bit. The shift direction of common signals is determined by the CSR bit. The following tables show the transfer and shift directions:
SSR bit L H ABE bit L L L L L L L L H H H H H H H H CSR bit L L L L H H H H L L L L H H H H duty 1/8 1/8 1/16 1/16 1/8 1/8 1/16 1/16 1/9 1/9 1/17 1/17 1/9 1/9 1/17 1/17
Transfer direction SEG1 SEG100 SEG100 SEG1 AS bit L H L H L H L H L H L H L H L H Shift Direction COM1COM8 COM1COM8 COM1COM16 COM1COM16 COM8COM1 COM8COM1 COM16COM1 COM16COM1 COM1COM9 COM1COM9 COM1COM17 COM1COM17 COM9COM1 COM9COM1 COM17COM1 COM17COM1 Arbitrator's common pin None None None None None None None None COM9 COM1 COM17 COM1 COM1 COM9 COM1 COM17
* Refer to the Expansion Instruction Codes section about the ABE bit, SSR bit, CSR bit, and AS bit. Signals to be input to the SSR bit, CSR bit, ABE bit, and AS bit should be initially determined at power-on and be kept unchanged.
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Built-in Reset Circuit The ML9042 is automatically initialized when the power is turned on. During initialization, the Busy Flag (BF) is "1" and the ML9042 does not accept any instruction from the CPU (other than the Read BF instruction). The Busy Flag is "1" for about 15 ms after the VDD becomes 2.7 V or higher. During this initialization, the ML9042 performs the following instructions: 1) 2) 3) 4) 5) 6) 7) 8) 9) 10) 11) 12) Display clearing CPU interface data length = 8 bits 1-line LCD display ADC counting = Increment Display shifting = None Display = Off Cursor = Off Blinking = Off Arbitrator = Displayed in the lower line Arbitrator = Not displayed Segment shift direction = SEG1 SEG100 Common shift direction = COM1 COM17
(DL = "1") (N = "0") (I/D = "1") (S = "0") (D = "0") (C = "0") (B = "0") (AS = "0") (ABE = "0") (SSR = "0") (CSR = "0")
To use the built-in reset circuit, the power supply conditions shown below should be satisfied. Otherwise, the built-in reset circuit may not work properly. In such a case, initialize the ML9042 with the instructions from the CPU. The use of a battery always requires such initialization from the CPU. (See "Initial Setting of Instructions")
2.7 V
0.2 V tON 0.1 ms tON 100 ms
0.2 V tOFF 1 ms tOFF
0.2 V
Figure 1 Power-on and Power-off Waveform
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I/F with CPU Parallel interface mode The ML9042 can transfer either 8 bits once or 4 bits twice on the data bus for interfacing with any 8-bit or 4-bit microcontroller (CPU). 1) 8-bit interface data length The ML9042 uses all of the 8 data bus lines DB0(SO) to DB7 at a time to transfer data to and from the CPU. 2) 4-bit interface data length The ML9042 uses only the higher-order 4 data bus lines DB4 to DB7 twice to transfer 8-bit data to and from the CPU. The ML9042 first transfers the higher-order 4 bits of 8-bit data (DB4 to DB7 in the case of 8-bit interface data length) and then the lower-order 4 bits of the data (DB0(SO) to DB3 in the case of 8-bit interface data length). The lower-order 4 bits of data should always be transferred even when only the transfer of the higher-order 4 bits of data is required. (Example: Reading the Busy Flag) Two transfers of 4 bits of data complete the transfer of a set of 8-bit data. Therefore, when only one access is made, the following data transfer cannot be completed properly.
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RS1 RS0/CSB RWB/SI E/SHTB Busy (Internal operation) DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0/(SO)
IR7 IR6 IR5 IR4 IR3 IR2 IR1 IR0 Busy No Busy
ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0
DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0
Writing In IR (Instruction Register)
Reading BF (Busy Flag) and ADC (Address Counter)
Writing In DR (Data Register)
Figure 2 8-Bit Data Transfer
RS1 RS0/CSB RWB/SI E/SHTB Busy (Internal operation) DB7 DB6 DB5 DB4
IR7 IR6 IR5 IR4
IR3 IR2 IR1 IR0
Busy
No Busy
ADC6 ADC5 ADC4
ADC3 ADC2 ADC1 ADC0
DR7 DR6 DR5 DR4
DR3 DR2 DR1 DR0
Writing In IR (Instruction Register)
Reading BF (Busy Flag) and ADC (Address Counter)
Writing In DR (Data Register)
Figure 3 4-Bit Data Transfer
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Serial Interface Mode In the Serial I/F Mode, the ML9042 interfaces with the CPU via the RS0/CSB, E/SHTB, RW/SI, and DB0(SO) pins. Writing and reading operations are executed in units of 16 bits after the RS0/CSB signal falls down. If the RS0/CSB signal rises up before the completion of 16-bit unit access, this access is ignored. When the BF bit is "1", the ML9042 cannot accept any other instructions. Before inputting a new instruction, check that the BF bit is "0". Any access when the BF bit is "1" is ignored. Data format is LSB-first. Examples of Access in the Serial I/F Mode
1) WRITE MODE RS0/CSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1
E/SHTB BUSY (Internal operation) RWB/SI DB(SO)
1 1 1 1 1 R/W RS0 RS1 D0 D1 D2 D3 D4 D5 D6 D7 1
2) READ MODE RS0/CSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1
E/SHTB BUSY (Internal operation) RWB/SI DB(SO)
1 1 1 1 1 R/W RS0 RS1 1
D0
D1
D2
D3
D4
D5
D6
D7
Note 1: Higher 5 bits of each instruction must be input at a "H" level. Note 2: Lower 8 bits are "don't care" when the instructions in the READ MODE are set. Note 3: After one instruction is input, the next instruction must be input after the RS0/CSB pin is pulled at a "H" level.
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Instruction Codes Table of Instruction Codes
Instruction Code DB0 RS0/ RW/ DB7 DB6 DB5 DB4 DB3 DB2 DB1 RS1 CSB SI (SO) 1 0 0 0 0 0 0 0 0 0 1 Function Execution Time f = 270 kHz
Display Clear
Cursor Home
1
0
0
0
0
0
Entry Mode Setting
1
0
0
0
0
0
Display 1 ON/OFF Control Cursor/Display Shift 1
0
0
0
0
0
0
0
0
0
0
Function Setting 1
0
0
0
0
1
CGRAM Address Setting DDRAM Address Setting Busy Flag/ Address Read
1
0
0
0
1
1
0
0
1
1
0 1 1 0 0
1 0 1 0 0
BF
RAM Data Write 1 RAM Data Read 1 Arbitrator 0 Display Line Set ABRAM Address Setting 0
Clears all the displayed digits of the LCD and sets the DDRAM address 00 1.52 ms in the address counter. The arbitrator data is cleared. Sets the DDRAM address 00 in the address counter and shifts the display 0 0 0 1 X 1.52 ms back to the original. The content of the DDRAM remains unchanged. Determines the direction of movement of the cursor and whether or not to shift 37 s 0 0 1 I/D S the display. This instruction is executed when data is written or read. Sets LCD display ON/OFF (D), cursor 37 s 0 1 D C B ON/OFF (C) or cursor-position character blinking ON/OFF (B). Moves the cursor or shifts the display 1 S/C R/L X X without changing the content of the 37 s DDRAM. Sets the interface data length (DL), the number of display lines (N), the 37 s DL N ABE SSR CSR arbitrator display (ABE), the segment data shift direction (SSR), or the common data shift direction (CSR). Sets on CGRAM address. After that, 37 s ACG CGRAM data is transferred to and from the CPU. Sets a DDRAM address. After that, ADD DDRAM data is transferred to and from 37 s the CPU. Reads the Busy Flag (indicating that 0 s ADC the ML9042 is operating) and the content of the address counter. Writes data in DDRAM, ABRAM or WRITE DATA 37 s CGRAM. Reads data from DDRAM, ABRAM or READ DATA 37 s CGRAM. 0 0 0 AAB 1 AS Sets the arbitrator display line. Sets an ABRAM address. After that, ABRAM data is transferred to and from the CPU. 37 s 37 s
0 0
0 1
0 1
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--
I/D = "1" (Increment) I/D = "0" (Decrement) S = "1" (Shifts the display.) S/C = "1" (Shifts display.) S/C = "0" (Moves the cursor.) R/L = "1" (Right shift) R/L = "0" (Left shift) D/L = "1" (8-bit data) DL = "0" (4-bit data) N = "1" (2 lines) N = "0" (1 line) ABE = "1" (Arbitrator displayed) ABE = "0" (Arbitrator not displayed) SSR = "1" (Transfer direction: SEG100 SEG1) SSR = "0" (Transfer direction: SEG1 SEG100) CSR = "1" (Transfer direction: COMn COM1) CSR = "0" (Transfer direction: COM1 COMn) BF = "1" (Busy) BF = "0" (Ready to accept an instruction) B = "1" (Enables blinking) C = "1" (Displays the cursor.) D = "1" (Displays a character pattern.) AS = "1" (Arbitrator Displays AS = "0" (Arbitrator Displays arbitrator on the arbitrator on the upper line) lower line)
DD RAM: CG RAM: ABRAM: ACG: ADD:
AAB: ADC:
Display data RAM Character generator RAM Arbitrator data RAM CGRAM address DDRAM address (Corresponds to the cursor address) ABRAM address Address counter (Used by DDRAM, ABRAM and CGRAM)
The execution time is dependent upon frequencies.
x: Don't Care
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Instruction Codes An instruction code is a signal sent from the CPU to access the ML9042. The ML9042 starts operation as instructed by the code received. The busy status of the ML9042 is rather longer than the cycle time of the CPU, since the internal processing of the ML9042 starts at a timing which does not affect the display on the LCD. In the busy status (Busy Flag is "1"), the ML9042 cannot input the Busy Flag Read instruction only. Therefore, the CPU should ensure that the Busy Flag is "0" before sending an instruction code to the ML9042. 1) Display Clear
RS1 RS0 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 1
Instruction Code:
1
When this instruction is executed, the LCD display including arbitrator display is cleared and the I/D entry mode is set to "Increment". The value of "S" (Display shifting) remains unchanged. The position of the cursor or blink being displayed moves to the left end of the LCD (or the left end of the line 1 in the 2-line display mode). Note: All DDRAM and ABRAM data turn to "20" and "00" in hexadecimal, respectively. The value of the address counter (ADC) turns to the one corresponding to the address "00" (hexadecimal) of the DDRAM. The execution time of this instruction is 1.52 ms (maximum) at an oscillation frequency of 270 kHz.
2) Cursor Home
RS1 RS0 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 1 DB0
Instruction code:
1
x
x: Don't Care
When this instruction is executed, the cursor or blink position moves to the left end of the LCD (or the left end of line 1 in the 2-line display mode). If the display has been shifted, the display returns to the original display position before shifting. Note: The value of the address counter (ADC) goes to the one corresponding to the address "00" (hexadecimal) of the DDRAM). The execution time of this instruction is 1.52 ms (maximum) at an oscillation frequency of 270 kHz.
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3) Entry Mode Setting
RS1 RS0 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 1 DB1 I/D DB0 S
Instruction code:
1
(1) When the I/D is set, the cursor or blink shifts to the right by 1 character position (ID= "1"; increment) or to the left by 1 character position (I/D= "0"; decrement) after an 8-bit character code is written to or read from the DDRAM. At the same time, the address counter (ADC) is also incremented by 1 (when I/D = "1"; increment) or decremented by 1 (when I/D = "0"; decrement). After a character pattern is written to or read from the CGRAM, the address counter (ADC) is incremented by 1 (when I/D = "1"; increment) or decremented by 1 (when I/D = "0"; decrement). Also after data is written to or read from the ABRAM, the address counter (ADC) is incremented by 1 (when I/D = "1"; increment) or decremented by 1 (when I/D = "0"; decrement). (2) When S = "1", the cursor or blink stops and the entire display shifts to the left (I/D = "1") or to the right (I/D = "0") by 1 character position after a character code is written to the DDRAM. In the case of S = "1", when a character code is read from the DDRAM, when a character pattern is written to or read from the CGRAM or when data is written to or read from the ABRAM, normal read/write is carried out without shifting of the entire display. (The entire display does not shift, but the cursor or blink shifts to the right (I/D = "1") or to the left (I/D = "0") by 1 character position.) When S = "0", the display does not shift, but normal write/read is performed. Note: The execution time of this instruction is 37 s (maximum) at an oscillation frequency of 270 kHz.
4) Display ON/OFF Control
RS1 RS0 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 D DB1 C DB0 B
Instruction code:
1
(1) The "D" bit (DB2) of this instruction determines whether or not to display character patterns on the LCD. When the "D" bit is "1", character patterns are displayed on the LCD. When the "D" bit is "0", character patterns are not displayed on the LCD and the cursor/blinking also disappear. Note: Unlike the Display Clear instruction, this instruction does not change the character code in the DDRAM .
(2) When the "C" bit (DB1) is "0", the cursor turns off. When both the "C" and "D" bits are "1", the cursor turns on. (3) When the "B" bit (DB0) is "0", blinking is canceled. When both the "B" and "D" bits are "1", blinking is performed. In the Blinking mode, all dots including those of the cursor, the character pattern and the cursor are alternately displayed. Note: The execution time of this instruction is 37 s (maximum) at an oscillation frequency of 270 kHz.
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5) Cursor/Display Shift
RS1 RS0 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 1 DB3 S/C DB2 R/L DB1 DB0
Instruction code:
1
x
x
x: Don't Care
S/C = "0", R/L = "0" S/C = "0", R/L = "1" S/C = "1", R/L = "0"
S/C = "1", R/L = "1"
This instruction shifts left the cursor and blink positions by 1 (decrements the content of the ADC by 1). This instruction shifts right the cursor and blink positions by 1 (increments the content of the ADC by 1). This instruction shifts left the entire display by 1 character position. The cursor and blink positions move to the left together with the entire display. The Arbitrator display is not shifted. (The content of the ADC remains unchanged.) This instruction shifts right the entire display by 1 character position. The cursor and blink positions move to the right together with the entire display. The Arbitrator display is not shifted. (The content of the ADC remains unchanged.)
In the 2-line mode, the cursor or blink moves from the first line to the second line when the cursor at digit 40 (27; hex) of the first line is shifted right. When the entire display is shifted, the character pattern, cursor or blink will not move between the lines (from line 1 to line 2 or vice versa). Note: The execution time of this instruction is 37 s at an oscillation frequency (OSC) of 270 kHz.
6) Function Setting
RS1 RS0 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 DL DB3 N DB2 ABE DB1 SSR DB0 CSR
Instruction code:
1
x: Don't Care
(1) When the "DL" bit (DB4) of this instruction is "1", the data transfer to and from the CPU is performed once by the use of 8 bits DB7 to DB0. When the "DL" bit (DB4) of this instruction is "0", the data transfer to and from the CPU is performed twice by the use of 4 bits DB7 to DB4. (2) The 2-line display mode is selected when the "N" bit (DB3) of this instruction is "1". The 1-line display mode is selected when the "N" bit is "0". The arbitrator is displayed when the "ABE" bit (DB2) of this instruction is "1". The arbitrator is not displayed when the "ABE" bit (DB2) of this instruction is "0". (3) The transfer direction of the segment signal output data is controlled. When the "SSR" bit (DB1) of this instruction is "1", the data is transferred from SEG100 to SEG1. When the "SSR" bit (DB1) of this instruction is "0", the data is transferred from SEG1 to SEG100. The transfer direction of the common signal output data is controlled. At 1/n duty, When the "CSR" bit (DB0) of this instruction is "1", the data is transferred from COMn to COM1. When the "CSR" bit (DB0) of this instruction is "0", the data is transferred from COM1 to COMn. After the ML9042 is powered on, this function setting should be carried out before execution of any instruction except the Busy Flag Read. After this function setting, no instructions other than the DL Set instruction can be executed. In the Serial I/F Mode, DL setting is ignored.
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N 0 0 1 1
ABE 0 1 0 1
Number of display lines 1 1 2 2
Font size 5x8 5x8 5x8 5x8
Duty 1/8 1/9 1/16 1/17
Number of biases 4 4 5 5
Number of common signals 8 9 16 17
Note:
The execution time of this instruction is 37 s at an oscillation frequency (OSC) of 270 kHz.
7) CGRAM Address Setting
RS1 RS0 0 R/W 0 DB7 0 DB6 1 DB5 C5 DB4 C4 DB3 C3 DB2 C2 DB1 C1 DB0 C0
Instruction code:
1
This instruction sets the CGRAM address to the data represented by the bits C5 to C0 (binary). The CGRAM addresses are valid until DDRAM or ABRAM addresses are set. The CPU writes or reads character patterns starting from the one represented by the CGRAM address bits C5 to C0 set in the instruction code at that time. Note: The execution time of this instruction is 37 s at an oscillation frequency (OSC) of 270 kHz. 8) DDRAM Address Setting
RS1 RS0 0 R/W 0 DB7 1 DB6 D6 DB5 D5 DB4 D4 DB3 D3 DB2 D2 DB1 D1 DB0 D0
Instruction code:
1
This instruction sets the DDRAM address to the data represented by the bits D6 to D0 (binary). The DDRAM addresses are valid until CGRAM or ABRAM addresses are set. The CPU writes or reads character codes starting from the one represented by the DDRAM address bits D6 to D0 set in the instruction code at that time. In the 1-line mode (the "N" bit is "0"), the DDRAM address represented by bits D6 to D0 (binary) should be in the range "00" to "4F" in hexadecimal. In the 2-line mode (the "N" bit is "1"), the DDRAM address represented by bits D6 to D0 (binary) should be in the range "00" to "27" or "40" to "67" in hexadecimal. If an address other than above is input, the ML9042 cannot properly write a character code in or read it from the DDRAM. Note: The execution time of this instruction is 37 s at an oscillation frequency (OSC) of 270 kHz. 9) DDRAM/ABRAM/CGRAM Data Write
RS1 RS0 1 R/W 0 DB7 E7 DB6 E6 DB5 E5 DB4 E4 DB3 E3 DB2 E2 DB1 E1 DB0 E0
Instruction code:
1
A character code (E7 to E0) is written to the DDRAM, Display-ON data (E7 to E0) to the ABRAM or a character pattern (E7 to E0) to the CGRAM. The DDRAM, ABRAM or CGRAM is selected at the preceding address setting. After data is written, the address counter (ADC) is incremented or decremented as set by the Entry Mode Setting instruction (see 3). Note: The execution time of this instruction is 37 s at an oscillation frequency (OSC) of 270 kHz.
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10) Busy Flag/Address Counter Read (Execution time: 0 s)
RS1 RS0 0 R/W 1 DB7 BF DB6 O6 DB5 O5 DB4 O4 DB3 O3 DB2 O2 DB1 O1 DB0 O0
Instruction code:
1
The "BF" bit (DB7) of this instruction tells whether the ML9042 is busy in internal operation (BF = "1") or not (BF = "0"). When the "BF" bit is "1", the ML9042 cannot accept any other instructions. Before inputting a new instruction, check that the "BF" bit is "0". When the "BF" bit is "0", the ML9042 outputs the correct value of the address counter. The value of the address counter is equal to the DDRAM, ABRAM or CGRAM address. Which of the DDRAM, ABRAM and CGRAM addresses is set in the counter is determined by the preceding address setting. When the "BF" bit is "1", the value of the address counter is not always correct because it may have been incremented or decremented by 1 during internal operation. 11) DDRAM/ABRAM/CGRAM Data Read
RS1 RS0 1 R/W 1 DB7 P7 DB6 P6 DB5 P5 DB4 P4 DB3 P3 DB2 P2 DB1 P1 DB0 P0
Instruction code:
1
A character code (P7 to P0) is read from the DDRAM, Display-ON data (P7 to P0) from the ABRAM or a character pattern (P7 to P0) from the CGRAM. The DDRAM, ABRAM or CGRAM is selected at the preceding address setting. After data is read, the address counter (ADC) is incremented or decremented as set by the Entry Mode Setting instruction (see 3). Note: Conditions for reading correct data (1) The DDRAM, ABRAM or CGRAM Setting instruction is input before this data read instruction is input. (2) When reading a character code from the DDRAM, the Cursor/Display Shift instruction (see 5) is input before this Data Read instruction is input. (3) When two or more consecutive RAM Data Read instructions are executed, the following read data is correct. Correct data is not output under conditions other than the cases (1), (2) and (3) above. Note: The execution time of this instruction is 37 s at an oscillation frequency (OSC) of 270 kHz.
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Expansion Instruction Codes The busy status of the ML9042 is rather longer than the cycle time of the CPU, since the internal processing of the ML9042 starts at a timing which does not affect the display on the LCD. In the busy status (Busy Flag is "1"), the ML9042 executes the Busy Flag Read instruction only. Therefore, the CPU should ensure that the Busy Flag is "0" before sending an expansion instruction code to the ML9042. 1) Arbitrator Display Line Set
RS1 Expansion instruction code: 0 RS0 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 1 DB0 AS
This expansion instruction code sets the Arbitrator display line. The relationship between the status of this bit and the common outputs is as follows: For display examples, refer to LCD Drive Waveforms section.
ABE bit L L L L L L L L H H H H H H H H CSR bit L L L L H H H H L L L L H H H H duty 1/8 1/8 1/16 1/16 1/8 1/8 1/16 1/16 1/9 1/9 1/17 1/17 1/9 1/9 1/17 1/17 AS bit L H L H L H L H L H L H L H L H Shift direction COM1COM8 COM1COM8 COM1COM16 COM1COM16 COM8COM1 COM8COM1 COM16COM1 COM16COM1 COM1COM9 COM1COM9 COM1COM17 COM1COM17 COM9COM1 COM9COM1 COM17COM1 COM17COM1 Arbitrator's common pin None None None None None None None None COM9 COM1 COM17 COM1 COM1 COM9 COM1 COM17
Note:
The execution time of this instruction is 37 s at an oscillation frequency (OSC) of 270 kHz.
2) ABRAM Address Setting
RS1 Expansion instruction code: 0 RS0 0 R/W 1 DB7 0 DB6 1 DB5 1 DB4 H4 DB3 H3 DB2 H2 DB1 H1 DB0 H0
This instruction sets the ABRAM address to the data represented by the bits H4 to H0 (binary). The ABRAM addresses are valid until CGRAM or DDRAM addresses are set. The CPU writes or reads the Display-ON data starting from the one represented by the ABRAM address bits H4 to H0 set in the instruction code at that time. When the ABRAM address represented by bits H4 to H0 (binary) is in the range "00" to "13" in hexadecimal, data is output to the LCD as the arbitrator. Note: The execution time of this instruction is 37 s at an oscillation frequency (OSC) of 270 kHz.
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Examples of Combinations of ML9042 and LCD Panel (1) Driving the LCD of one 20-character line under the conditions of the 1-line display mode and no arbitrator display (1/8 duty, ABE = "0", AS = "0" or "1", CSR = "0", SSR = "1")
COM1 Character COM8
SEG100
SEG1
ML9042
* COM9 to COM17 output Display-OFF common signals. (1/8 duty, ABE = "0", AS = "0" or "1", CSR = "1", SSR = "0")
ML9042
SEG1 SEG100
COM8 Character COM1
* COM9 to COM17 output Display-OFF common signals.
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(2) Driving the LCD of one 20-character line under the conditions of the 1-line display mode and the arbitrator display (1/9 duty, ABE = "1", AS = "0", CSR = "0", SSH = "1")
COM1 Character COM8 COM9 Arbitrator SEG100 SEG1
ML9042
* COM10 to COM17 output Display-OFF common signals. (1/9 duty, ABE = "1", AS = "1", CSR = "0", SSR = "1")
COM1 COM2 Arbitrator
Character COM9
SEG100
SEG1
ML9042
* COM10 to COM17 output Display-OFF common signals.
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(1/9 duty, ABE = "1", AS = "0", CSR = "1", SSR = "0")
ML9042
SEG1 SEG100
COM9 Character COM2 Arbitrator COM1
* COM10 to COM17 output Display-OFF common signals. (1/9 duty, ABE = "1", AS = "1", CSR = "1", SSR = "0")
ML9042
SEG1 SEG100
Arbitrator
COM9 COM8
Character COM1
* COM10 to COM17 output Display-OFF common signals.
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(3) Driving the LCD of two 20-character lines under the conditions of the 2-line display mode and no arbitrator display (1/16 duty, ABE = "0", AS = "0" or "1", CSR = "0", SSR = "1")
COM1 Character COM8
COM9 Character COM16
SEG100
SEG1
ML9042
* COM17 outputs Display-OFF common signal. (1/16 duty, ABE = "0", AS = "0" or "1", CSR = "1", SSR = "0")
ML9042
SEG1 SEG100
COM16 Character COM9
COM8 Character COM1
* COM17 outputs Display-OFF common signal.
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(4) Driving the LCD of two 20-character lines under the conditions of the 2-line display mode and the arbitrator display (1/17 duty, ABE = "1", AS = "0", CSR = "0", SSR = "1")
COM1 Character COM8
COM9 Character COM16 COM17 Arbitrator
SEG100
SEG1
ML9042
(1/17 duty, ABE = "1", AS = "1", CSR = "0", SSR = "1")
COM1 COM2 Arbitrator Character COM9
COM10 Character COM17
SEG100
SEG1
ML9042
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(1/17 duty, ABE = "1", AS = "0", CSR = "1", SSR = "0")
ML9042
SEG1 SEG100
COM17 Character COM10 COM9 Character COM2 Arbitrator COM1
(1/17 duty, ABE = "1", AS = "1", CSR = "1", SSR = "0")
ML9042
SEG1 SEG100
Arbitrator Character
COM17 COM16
COM9
COM8 Character COM1
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EXAMPLES OF VLCD GENERATION CIRCUITS
* With 1/4 bias, a voltage multiplier
VDD
BE VIN VC VCC VOUT V0 V1 V2 V3A V3B V4 GND
Reference potential for voltage multiplier +
ML9042
+
* With 1/4 bias, no voltage multiplier 1) Apply VDD to VOUT and V0. 2) Apply VDD to VOUT, and apply the V0 level to V0 externally.
VDD
BE VIN VC VCC VOUT V0 V1 V2 V3A V3B V4 GND V0 level
ML9042
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* With 1/5 bias, a voltage multiplier
VDD
BE VIN VC VCC VOUT V0 V1 V2 V3A V3B V4 GND
Reference potential for voltage multiplier +
ML9042
+
* With 1/5 bias, no voltage multiplier 1) Apply VDD to VOUT and V0. 2) Apply VDD to VOUT, and apply the V0 level to V0 externally.
VDD
BE VIN VC VCC VOUT V0 V1 V2 V3A V3B V4 GND V0 level
ML9042
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LCD Drive Waveforms The COM and SEG waveforms (AC signal waveforms for display) vary according to the duty (1/9 and 1/17 duties). See 1) and 2) below. The relationship between the duty ratio and the frame frequency is as follows:
Duty ratio 1/8 1/9 1/16 1/17
Frame Frequency 84.4 Hz 75.0 Hz 84.4 Hz 79.4 Hz
Note: At an oscillation frequency (OSC) of 270 kHz
1) COM and SEG Waveforms on 1/9 Duty (ABE = "1")
CSR="H" COM1 (CSR = "L", AS = "L") COM2 (CSR = "L", AS = "H") COM9 (CSR = "H", AS = "L") COM8 (CSR = "H", AS = "H") (first character line) CSR="L" V0 V1 V2, V3B V4 V5 2 1 9 8 7 6 *** 3 2 1 9 8 7 6 *** 3 2 1 9 8 8 9 1 2 3 4 *** 7 8 9 1 2 3 4 *** 7 8 9 1 2
1 frame COM2 (CSR = "L", AS = "L") COM3 (CSR = "L", AS = "H") COM8 (CSR = "H", AS = "L") COM7 (CSR = "H", AS = "H") (second character line) V0 V1 V2, V3B V4 V5
COM8 (CSR = "L", AS = "L") COM9 (CSR = "L", AS = "H") COM2 (CSR = "H", AS = "L") COM1 (CSR = "H", AS = "H") (eighth character line)
V0 V1 V2, V3B V4 V5
COM9 (CSR = "L", AS = "L") COM1 (CSR = "L", AS = "H") COM1 (CSR = "H", AS = "L") COM9 (CSR = "H", AS = "H") (arbitrator line)
V0 V1 V2, V3B V4 V5
COM10 to COM17
V0 V1 V2, V3B V4 V5 Display turning-off waveform V0 V1 V2, V3B V4 V5 Display turning-on waveform
SEG
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2) COM and SEG Waveforms on 1/17 Duty (ABE = "1")
CSR="H" COM1 (CSR = "L", AS = "L") COM2 (CSR = "L", AS = "H") COM17 (CSR = "H", AS = "L") COM16 (CSR = "H", AS = "H") (first character line) 2 1 17 16 15 14 13 12 11 10 9 8 7 6 5 *** 2 1 17 16 15 14
CSR="L" 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 *** 16 17 1 2 3 4 V0 V1 V2 V3A (V3B) V4 V5 1 frame
COM2 (CSR = "L", AS = "L") COM3 (CSR = "L", AS = "H") COM16 (CSR = "H", AS = "L") COM15 (CSR = "H", AS = "H") (second character line)
V0 V1 V2 V3A (V3B) V4 V5
COM16 (CSR = "L", AS = "L") COM17 (CSR = "L", AS = "H") COM2 (CSR = "H", AS = "L") COM1 (CSR = "H", AS = "H") (sixteenth character line)
V0 V1 V2 V3A (V3B) V4 V5
COM17 (CSR = "L", AS = "L") COM1 (CSR = "L", AS = "H") COM1 (CSR = "H", AS = "L") COM17 (CSR = "H", AS = "H") (arbitrator line)
V0 V1 V2 V3A (V3B) V4 V5 Display turning-off waveform V0 V1 V2 V3A (V3B) V4 V5 Display turning-on waveform
SEG
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Initial Setting of Instructions (a) Data transfer from and to the CPU using 8 bits of DB0 to DB7 1) Turn on the power. 2) Wait for 15 ms or more after VDD has reached 2.7 V or higher. 3) Set "8 bits" with the Function Setting instruction. 4) Wait for 4.1 ms or more. 5) Set "8 bits" with the Function Setting instruction. 6) Wait for 100 s or more. 7) Set "8 bits" with the Function Setting instruction. 8) Check the Busy Flag for No Busy (or wait for 100 s or more). 9) Set "8 bits", "Number of LCD lines" and "Font size" with the Function Setting instruction. (After this, the number of LCD lines and the font size cannot be changed.) 10) Check the Busy Flag for No Busy. 11) Execute the Display ON/OFF control Instruction, Display Clear Instruction, Entry Mode Setting instruction and Arbitrator Display Line Setting Instruction. 12) Check the Busy Flag for No Busy. 13) Initialization is completed. An example of instruction code for 3), 5) and 7)
RS1 1 RS0 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 1 DB3 x DB2 x DB1 x DB0 x
x: Don't Care
(b) Data transfer from and to the CPU using 4 bits of DB4 to DB7 1) Turn on the power. 2) Wait for 15 ms or more after VDD has reached 2.7 V or higher. 3) Set "8 bits" with the Function Setting instruction. 4) Wait for 4.1 ms or more. 5) Set "8 bits" with the Function Setting instruction. 6) Wait for 100 s or more. 7) Set "8 bits" with the Function Setting instruction. 8) Check the Busy Flag for No Busy (or wait for 100 s or longer). 9) Set "4 bits" with the Function Setting instruction. 10) Wait for 100 s or longer. 11) Set "4 bits", "Number of LCD lines" and "Font size" with the Function Setting instruction. (After this, the number of LCD lines and the font size cannot be changed.) 12) Check the Busy Flag for No Busy. 13) Execute the Display ON/OFF control Instruction, Display Clear Instruction, Entry Mode Setting instruction and Arbitrator Display Line Setting Instruction. 14) Check the Busy Flag for No Busy. 15) Initialization is completed. An example of instruction code for 3), 5) and 7)
RS1 1 RS0 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 1
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An example of instruction code for 9)
RS1 1 RS0 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 0
*: From 11), input data twice by the use of 4-bit data. *: In 13), check the Busy Flag for No Busy before executing each instruction. (c) Data transfer from and to the CPU using the serial I/F 1) Turn on the power. 2) Wait for 15 ms or more after VDD has reached 2.7 V or higher. 3) Check the busy flag for No Busy. 4) Set "Number of LCD lines" and "Font size" with the Function Setting Instruction. (After this, the number of LCD lines and the font size cannot be changed.) 5) Check the busy flag for No Busy. 6) Execute the Display ON/OFF control Instruction, the Display Clear Instruction, the Entry Mode Instruction and the Arbitrator Display Line Setting Instruction. 7) Check the busy flag for No Busy. 8) Initialization is completed. *: In 6), check the Busy Flag for No Busy before executing each instruction.
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ML9042-xx CVWA/DVWA PAD CONFIGURATION
Pad Layout Chip Size: Chip Thickness: Bump Size: 7.8 x 1.8 mm 62520 m 100 x 44 m
Y
220 221
115 114 X
233 1 100
101
Pad Coordinates
Pad 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol DUMMY OSC2 OSCR5 OSCR3 OSC1
DUMMYGND
X (m) -3750 -3675 -3600 -3525 -3450 -3375 -3300 -3225 -3150 -3075 -3000 -2925 -2850 -2775 -2700 -2625 -2550 -2475 -2400 -2325
Y (m) -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750
Pad 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Symbol DUMMY E/SHTB E/SHTB DUMMY DUMMY DB0/SO DB0/SO DUMMY DUMMY DB1 DB1 DUMMY DUMMY DB2 DB2 DUMMY DUMMY DB3 DB3 DUMMY
X (m) -2250 -2175 -2100 -2025 -1950 -1875 -1800 -1725 -1650 -1575 -1500 -1425 -1350 -1275 -1200 -1125 -1050 -975 -900 -825
Y (m) -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750
T1 T2 T3 ROM1S DUMMYVDD RS1 RS1 RSO/CSB RSO/CSB DUMMY DUMMY RW/SI RW/SI DUMMY
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Pad 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Symbol DUMMY DB4 DB4 DUMMY DUMMY DB5 DB5 DUMMY DUMMY DB6 DB6 DUMMY DUMMY DB7 DB7
DUMMYVDD
X (m) -750 -675 -600 -525 -450 -375 -300 -225 -150 -75 0 75 150 225 300 375 450 525 600 675 750 825 900 975 1050 1125 1200 1275 1350 1425 1500 1575 1650 1725 1800 1875 1950 2025 2100 2175
Y (m) -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750
Pad 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
Symbol V0 V0 V0 V0 V1 V2 V2 V3A V3A V3B V3B V4 VC VC VC VC VCC VCC VCC DUMMY DUMMY COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY SEG100 SEG99 SEG98
X (m) 2250 2325 2400 2475 2550 2625 2700 2775 2850 2925 3000 3075 3150 3225 3300 3375 3450 3525 3600 3675 3750 3750 3750 3750 3750 3750 3750 3750 3750 3750 3750 3750 3750 3750 3675 3605 3535 3465 3395 3325
Y (m) -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -750 -462 -392 -322 -252 -182 -112 -42 28 98 168 238 308 378 448 750 750 750 750 750 750
SP GND GND GND GND GND GND BE VDD VDD VDD VDD VDD VDD TESTIN TESTIN TESTOUT TESTOUT VIN VIN VOUT VOUT V0 V0
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Pad 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
Symbol SEG97 SEG96 SEG95 SEG94 SEG93 SEG92 SEG91 SEG90 SEG89 SEG88 SEG87 SEG86 SEG85 SEG84 SEG83 SEG82 SEG81 SEG80 SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG72 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58
X (m) 3255 3185 3115 3045 2975 2905 2835 2765 2695 2625 2555 2485 2415 2345 2275 2205 2135 2065 1995 1925 1855 1785 1715 1645 1575 1505 1435 1365 1295 1225 1155 1085 1015 945 875 805 735 665 595 525
Y (m) 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750
Pad 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200
Symbol SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18
X (m) 455 385 315 245 175 105 35 -35 -105 -175 -245 -315 -385 -455 -525 -595 -665 -735 -805 -875 -945 -1015 -1085 -1155 -1225 -1295 -1365 -1435 -1505 -1575 -1645 -1715 -1785 -1855 -1925 -1995 -2065 -2135 -2205 -2275
Y (m) 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750
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Pad 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233
Symbol SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 DUMMY
X (m) -2345 -2415 -2485 -2555 -2625 -2695 -2765 -2835 -2905 -2975 -3045 -3115 -3185 -3255 -3325 -3395 -3465 -3535 -3605 -3675 -3750 -3750 -3750 -3750 -3750 -3750 -3750 -3750 -3750 -3750 -3750 -3750 -3750
Y (m) 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 750 448 378 308 238 168 98 28 -42 -112 -182 -252 -322 -392
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ML9042-xx CVWA/DVWA ALIGNMENT MARK SPECIFICATION
Alignment Mark Coordinates
Y A .................................................................................................... : : : : B
(0, 0) ....................................................................................................
X C
Alignment Mark A B C
X (m) -3770 3770 3770
Y (m) 770 770 -770
The coordinates (X, Y) indicate the distances to the center of an alignment mark (the center of the maximum outline of the L shape). Alignment Mark Layer Gold bump Alignment Mark Gold Bump Specification
Symbol Parameter Alignment Mark Width Alignment Mark Size Mark A, B, C A, B, C Size (m) 30 80
a b
b
a
+
b
a
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ML9042-xx CVWA GOLD BUMP SPECIFICATION (HIGH HARDNESS)
Gold Bump Specification
(Unit: m) MAX -- 48 104 30 84 34 2 20 4 5 --
Symbol A B C D E F G H I J K
Parameter Bump Pitch (I/O Section: Pitch Direction) Bump Size (I/O Section: Pitch Direction) Bump Size (I/O Section: Depth Direction) Bump-to-Bump Distance (I/O Section: Pitch Direction) Bump Size (L-mark Section: Length) Bump Size (L-mark Section: Width) Sliding of Total Bump Pitches Bump Height Bump Height Dispersion Inside Chip (Range) Bump Edge Height Shear Strength (g) Bump Hardness (Hv: 25 g load)
MIN 70 40 96 22 76 26 -- 10 -- -- 27
TYP -- 44 100 26 80 30 -- 15 -- -- --
50 90 130 Wafer Thickness; 625 20 m Chip Size; 7.80 mm x 1.80 mm
Top View and Cross Section View
A
B I C E D [I/O Section] [L-Alignment Mark] [Cross Section View] F H
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ML9042-xx CVWA GOLD BUMP SPECIFICATION (LOW HARDNESS)
Gold Bump Specification
(Unit: m) MAX -- 48 104 30 84 34 2 20 4 5 --
Symbol A B C D E F G H I J K
Parameter Bump Pitch (I/O Section: Pitch Direction) Bump Size (I/O Section: Pitch Direction) Bump Size (I/O Section: Depth Direction) Bump-to-Bump Distance (I/O Section: Pitch Direction) Bump Size (L-mark Section: Length) Bump Size (L-mark Section: Width) Sliding of Total Bump Pitches Bump Height Bump Height Dispersion Inside Chip (Range) Bump Edge Height Shear Strength (g) Bump Hardness (Hv: 25 g load)
MIN 70 40 96 22 76 26 -- 10 -- -- 27
TYP -- 44 100 26 80 30 -- 15 -- -- --
30 -- 80 Wafer Thickness; 625 20 m Chip Size; 7.80 mm x 1.80 mm
Top View and Cross Section View
A
B I C E D [I/O Section] [L-Alignment Mark] [Cross Section View] F H
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REVISION HISTORY
Document No.
PEDL9042-01
Date
Jun. 16, 2003
Page Previous Current Edition Edition
- 5 - 5
Description
Preliminary first edition Changed descriptions of Symbols VC and VCC Changed DC Characteristics Condition VDD = 4.5 to 5.5VVDD = 4.0 to 5.5V Ta = 25CTa =- 20 to 75C Spec Min. 175 Typ. 270 Max. 365 Min. 200 Typ. 270 Max. 351 Min. 175 Typ. 270 Max. 365 Min. 200 Typ. 280 Max. 364 Added of table Partially changed figure of generation circuits (VC+)(VCC+) and V2,V3A,V3B Partially changed figure of generation circuits (VC+)(VCC+)
8 FEDL9042-01 Nov. 19, 2003
8
25 44 45
25 44 45
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OKI Semiconductor
ML9042-xx
NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2003 Oki Electric Industry Co., Ltd.
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