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DATA PROCESSOR
KD16903
1. BLOCK DIAGRAM
1.1 SYSTEM BLOCK DIAGRAM
CKIN
RESB SCL SDA VOCODER DIN FS MCLK
VIP
DOUT
VOICE CODEC
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KD16903
DATA PROCESSOR
1.2 CHIP BLOCK DIAGRAM
SRAM 256 MSM VOCODER I2C I/F
SRAM 256
SSP1611
Digital I/F CODEC P.ROM 2K
VIP NOTE: Not Scaled
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DATA PROCESSOR
KD16903
1.3 FUNCTIONAL BLOCK DIAGRAM
Voice Intelligibility Proces
DIN
PCM INPUT I/F
BPF (Center: 300HZ) BPF (Center: 600HZ)
DOUT
PCM OUTPUT I/F
+ BPF (Center: 1.2kHZ) HPF (Cutoff: 2.4kHZ)
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KD16903
DATA PROCESSOR
2. PIN ASSIGNMENTS
TSHFTDR
TSEKDR0
TSELDR1
TUPDDR
TCLKDR
GND3
VDD3 18 8 RESB
TIDR
25 VDD4 26 TODR 27 GPO3 28 GPO2 29 DOUT 30 GND4 31 GPO1 32 1 GPO0
24
23
22
21
20
19
17 16 SCL 15 SDA 14 GND2
KA16903 32BCC (Top View)
13 CKIN 12 VDD2 11 MCLK 10 DIN
2 VDD1
3 GPI0
4 GPI1
5 GPI2
6 GPI3
7 GND1
4
FS
SAS 9
DATA PROCESSOR
KD16903
3. PIN DESCRIPTION
Related Block HIU PIN NAME RESB SDA SCL SAS DIN CIU DOUT FS MCLK System CKIN GPI0 GPI1 GPI2 GPI3 TSELDR0 TSELDR1 TEST TUPDDR TSHFTDR TIDR TCLKDR TODR GPO0 GPO1 GPO2 GPO3 Power Ground VDD1, VDD2 VDD3, VDD4 GND1, GND2 GND3, GND4 PIN NO. 8 15 16 17 10 30 9 11 13 3 4 5 6 19 20 21 23 24 25 27 1 32 29 28 2, 12, 18, 26 7, 14, 22, 31 I/O I I/O I I I O I I I I I I I I I I I I I O O O O O P G I2C Serial Data I2C Serial Clock I2C Address Selection 16 Bit PCM Serial Data In 16 Bit PCM Serial Data Out PCM Data Frame Sync. PCM Data Bit Clock System Clock (9.84MHz) Test Pin0 (Host INT. Indicator) Test Pin1(0:No Fade, 1:Fade) Test Pin2 (0:RAM Test) Test Pin3 (0:Codec Bypass) Test Pin for JTAG Test Pin for JTAG Test Pin for JTAG Test Pin for JTAG Test Pin for JTAG Test Pin for JTAG Test Pin for JTAG Host Ack. Pin Host Test Output Host Test Output Host Test Output Digital Power (+3.0V) Digital GND Description Reset: Active Low with CKIN(Min 10 cycle)
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KD16903
DATA PROCESSOR
4. DSP PORT ASSIGNMENT FOR I/F WITH PERIPHERALS
I/F HIU Read/ Write Read Write CIU Read Write Port EXT1 EXT1 EXT0 EXT0 Interrupt
INT1 INT0
5. HARDWARE SPECIFICATION
5.1 CODEC INTERFACE UNIT (CIU) - Time Diagram
FS
MCLK
DIN
1
2
3
4
5
6
7
~ ~
15
16
DOUT
1
2
3
4
5
6
7
~ ~
15
16
Important!: During FS (Frame Sync. Clock) high, the falling edge of MCLK (PCM Bit Clock) should exist one time.
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~ ~
DATA PROCESSOR
KD16903
5.2 HOST INTERFACE UNIT (HIU) - I2C Bus Interface The VIP can be controlled by a microcontroller via the 2-line I2C bus, SDA (Serial Data Line) and SCL (Serial Clock Line). Both lines must be connected to a positive supply via pull-up resistor. Data transfer may be initiated only when the bus is not busy. When the bus is free, both lines are high. The data on the SDA line must be stable during the high period of clock, SCL. When the SCL is low, the SDA can change. Every byte transferred through the SDA line must contain 8 bits including programmable slave address and read/write direction control bit. Each byte must be followed by acknowledge bit which is sent back to the microcontroller by the VIP by pulling down the SDA line. The MSB is transferred first.
- I2C bus interface start and stop condition The start condition is high to low transition of the SDA line while the SCL is high. The stop condition is low to high transition of the SDA line while SCL is high.
SDA
SCL Data Valid
Change of data Allowed
SDA
SCL
S Start Condition
P Stop Condition
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KD16903
DATA PROCESSOR
- I2C Bus Interface Acknowledge The acknowledge related clock pulse is generated by a microcontroller. The transmitter releases the SDA line (high) during the acknowledge clock pulse. The receiver must pull down the SDA line during the acknowledge clock pulse so that it remains stable low during the high period of this clock pulse. The slave-transmitter generates negative acknowledge when read operation processes. The negative acknowledge is generated by a master (microcontroller).
I2C Bus Interface Format-Write Operation Chip Address MSB LSB Function Address MSB LSB A MSB DATA LSB AP
S 1 0 0 0 0 0 A0 W A
SCL
SDA S
1 0000 0 0 0
P
I2C Bus Interface Format-Read Operation Chip Address MSB LSB Function Address MSB LSB A MSB DATA LSB
N/ A
S 1 0 0 0 0 0 A0 R A
P
SCL
SDA S
1 0000 0 0 1
P
- Relationship between the I2C Bus Interface signal SCL/SDA and main clock of KD16903(CKIN)
Commands are sent from MSM to KD16903 via the I2C (SDA/SCL) bus, triggered by the input signal CKIN. To achieve immunity towards noise, the glitch protection circuitry must be put into operation, thereby meeting the I2C specification. Thus CKIN should be input with the SDA/SCL. Another issue is, at least 100 clock(CKIN) cycles are needed to execute the command completely by the KD16903. Even as the end condition of the I2C interface is met, the MSM must supply KD16903 with CKIN, as
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DATA PROCESSOR
KD16903
long as the command is being processed.
SCL SDA
STOP Condition
CKIN
more than 100 clock cycles
RESET Mechanism
RESB should be held "LOW" for more than 10 cycles.
CKIN RESB
more than 10 clock cycles
CKIN becomes valid at this point
Using RESB The KD16903 consists of an DSP Unit, Host Interface, and a Codec Interface. And between these internal units, information is exchanged via the interrupt mechanism. None of the internally exchanged informations are available outside the KD16903. On the handphone, signals FS, MCLK, CKIN are controlable by the MSM. However, it is also likely that the KD16903 may fall into a state of deadlock, since none of these signals are monitorable externally.
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KD16903
DATA PROCESSOR
Furthermore trying to escape from the deadlock state by resupplying the FSK, MCLK, CKIN may not guarantee nominal operation. One way to escape from this deadlock state is to use the external reset mechanism. However, it is a good practice using the internal reset mechanism, supplied at a every new CKIN set, hence avoiding this deadlock state altogether.
To avoid deadlock, Rest must be used for following three cases. 1. Initialization to enter stable state of KD16903. 2. When changing CKIN(CHIPX8) from Hold to Running. 3. When start running Vocoder. Please note that the corresponding commands for the functions (VIP/EQ) must be downloaded after the Reset.
- Hardware Recommendation for Reset
Separate GPIO port must be assigned for RESB.
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DATA PROCESSOR
KD16903
6. COMMAND
6.1 SUMMARY IC Address 80H 80H 80H 80H 80H 80H 80H 80H 80H Command 01H 02H 03H 04H 05H 06H 07H 08H 09H Bit[7:5] 000B 80H 0AH 001B 010B 011B 80H 0BH Bit [7:4] 0H 80H 0CH ... 9H 80H 80H 0DH 01H 0H - CH 0H - CH **H Bit [3:0] 0H - CH VIP Filter1 Gain Control Bit [3:0] = 0H: +12dB, Bit [3:0] = CH: 0dB, 1dB Step VIP Filter10 Gain Control Noise Level Selection Return Current Status followed by IC Read Address 0x81, [7:4] = Unused, [3:2] = VIP Level, [1] = Working Mode(0:VIP, 1:EQ), [0] = Bypass Flag (0: DSP ON, 1: DSP OFF) Return Band1 Tone Level Status followed by IC Read Address 0x81 (00H: -12dB - 18H: + 12dB) Return Band2 Tone Level Status followed by IC Read Address 0x81 Return Band3 Tone Level Status followed by IC Read Address 0x81 Return Band4 Tone Level Status followed by IC Read Address 0x81 00000H 11000H Data 00H 01H 02H Bit[4:0] Band1 Gain Control Band2 Gain Control Band3 Gain Control Band4 Gain Control Host Test Mode (Return **H). Read after IC Read Address 0x81 VIP Equalizer Equalizer Flat Equalizer Mode1 Equalizer Mode2 Equalizer Mode3 Equalizer Mode4 VIP Level 100% VIP Level 80% VIP Level 60% Description Bypass (Default, DSP OFF)
00H - FFH
80H 80H 80H 80H 0EH
01H 02H 03H 04H
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KD16903
DATA PROCESSOR
6.2 DESCRIPTION - Bypass Mode * Format Command Code (Hex) 01 * Description Command Name Bypass
In bypass mode, DIN (PCM input data line) is directly connected to DOUT (PCM output data line) and the DSP is in stop mode. - VIP Mode * Format Command Code (Hex) 02 * Description Command Name VIP
This one byte command selects VIP mode.
- Equalizer Mode * Format Command Code (Hex) 03 Command Name EQ
*
Description
This one byte command selects Equalizer mode. Default tone levels are dipicted in
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DATA PROCESSOR
KD16903
10
0
-10
-20
-30 102 103
Figure 1: Default Tone Level (Band1: + 4dB, Band2: 0dB, Band3: 0dB, Band4: +1dB) - VIP Level Select * Format Command Code (Hex) 09 Data (Hex) 00 01 02 * Description VIP Level Command Name Description 100% (Max.) 80% (Mid.) 60% (Min.)
When the current mode is the VIP, its level can be changed using incoming data byte after the command. The default VIP level is 80%.
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KD16903
DATA PROCESSOR
- EQ Mode Select * Format Command Code (Hex) 04 05 06 07 08 * Command Name EQ Flat EQ Mode1 EQ Mode2 EQ Mode3 EQ Mode4 Description All Bands are set to 0dB Band1: +3dB, Band2: -1dB, Band3: -1dB, Band4: +1dB Band1: +3dB, Band2: 0dB, Band3: 0dB, Band4: +3dB Band1: +5dB, Band2: 0dB, Band3: 0dB, Band4: 0dB Band1: +5dB, Band2: 0dB, Band3: 0dB, Band4: +1dB
Description
Although equalizer can control all four bands, it assigns five preset tone level modes. - EQ Tone Select * Format Command Code (Hex) Data [7:5] 00 01 10 11 [4:0] 0A 00000 00001 ... 01100 ... 10111 11000 * Description -11dB -12dB 0dB Description Band1 Select Band2 Select Band3 Select Band4 Select +12dB +11dB Tone Control Command Name
The equalizer controls four different frequency bands. The gain for each frequency band can be controlled between -12dB and +12dB. The [7:5] in data byte after the command determines the frequency band to be controlled and [4:0] determines gain level.
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DATA PROCESSOR
KD16903
- VIP Filter Gain Selection * Format Command Code (Hex) Data (Hex) 0 1 2 3 [7:4] 0B 4 5 6 7 8 9 0 [3:0] 1 C Description 150Hz Filter Gain to Servo 300Hz Filter Gain to Servo 150Hz & 300 Hz Sum Gain 600Hz Filter Gain to Servo 1.2kHz Filter Gain to Summer 1.2kHz Filter Gain to Servo 2.4kHz Filter Gain to Summer 2.4kHz Filter Gain to Servo 4.8kHz Filter Gain to Summer 4.8kHz Filter Gain to Servo + 12dB + 11dB ... 0dB VIP Filter Gain Control Command Name
*
Description
These commands select the gains of filter outputs in the VIP mode. The detailed description of filter structure can be found in "VIP specification" published by SRS Labs.
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KD16903
DATA PROCESSOR
- Noise Level Selection * Format Command Code (Hex) 0D Data (Hex) 00 - FF Description Assume the value in data as noise level Command Name Noise Level Select
*
Description
When the input from ADC has small noise, this noise can incresed in VIP or EQ mode since the specific frequency levels are increased. To avoid this problem in mute, the input data is tested for 25ms. If the absolute values of input data are less than noise level specified in Data and stay for 25ms, then the input is considered as zeros and are processed. Default noise level is set to 0x1F.
- Current Status * Format Command Code (Hex) 0E Data (Hex) 01 Description Command Name
Return current status register contents Current Status
*
Description
It returns the contents of the current status register as: Status [7:4] = unused Status [3:2] = VIP Level (00: 100%, 01: 80%, 10: 60%) Status [1] = Working Mode (0: VIP, 1:EQ) Status [0] = DSP On/Off (0: DSP On, 1: DSP Off)
- EQ Tone Level Status * Format Command Code (Hex) 0E Data (Hex) 02 03 04 05 Description Return current band1 tone level Return current band2 tone level Return current band3 tone level Return current band4 tone level Current Tone Level Status Command Name
*
Description
These commands return the current tone levels in EQ mode. Returned byte value is between 0x00 (-12dB) and 0x18 (+12dB).
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DATA PROCESSOR
KD16903
7. MEMORY SIZE AND REQUIRED MIPS
7.1 MEMORY SIZE Memory Data Bank 0 Bank 1 VIP 4band EQ Program Test Others Total * word = 16 bit Size (word*) 256 256 800 500 400 100 1860
7.2 MIPS Routines VIP 4band EQ Others No. of Cycles 650 400 80 MIPS 5.2 3.2 0.64 Remark Working only when VIP is OFF -
Total (VIP ON) = 650 + 70 + 80 = 800 (6.4 MIPS)
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KD16903
DATA PROCESSOR
8. ELECTRICAL CHARACTERISTICS
(Unless otherwise specified, Vcc = 2.7V to 3.3V, TA = -30C to 85C ; typical characteristic are specified at Vcc = 3.0V, TA = 25C; all signals are referenced to GND) 8.1 DIGITAL INTERFACES Symbol VIL VIH VOL Parameter Input Low Voltage Input High Voltage IOL = 1uA Output Low Voltage IOL = 4mA (see Note1) IOL = 8mA (see Note 2) IOH = -1uA VOH IIL IIH IOZ Output High Voltage Input Low Current Input High Current Output Current in High impedance (Tri-state) IOH = -4mA (see Note1) IOH = -8mA (see Note2) VIN = Vss VIN = VSS (see Note3) VIN = VDD VIN = VDD (see Note4) VOUT = VSS or VDD -10 -60 -10 60 -5 30 -30 10 -10 10 10 5 uA uA uA uA uA VDD-0.05 2.4 V V Test Condition Min. 0.8 1.9 0.05 0.4 Typ. Max. Unit V V V V
NOTES: 1. Normal Output Pin 2. SDA ,SCL Output Pin 3. Input Buffer with pull -up (3, 4, 5, 6, 8 Pin) 4. Input Buffer with pull -down (17, 19, 20, 21, 23, 24, 25 Pin)
8.2 POWER DISSIPATION (@3.3V) Symbol ICC0 ICC1 ICC2 Parameter Operation Current Bypass Current Static Current Test Condition VIP or EQ Operation Mode Bypass Operation Mode No Operation (Sleep Mode) Min. Typ. 3 100 10 Max. 4 150 Unit mA uA uA
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DATA PROCESSOR
KD16903
9. PACKAGE DIMENSION
9.1 32 BCC TYPE
0.15 0.03 0.40 + 0.10 0.15 0.03
CAB C
CAB C
4.20
PIN CD.2
0.50 + 0.10 4.15
0.50
+ 0.10
0.45 + 0.10
0.50 + 0.10
0.60 MAX B
5.00 + 0.10
0.75 INDEX ???? MARKING TYPES
+ 0.025
4X A 0.15 / / 0.20 C
0.15
C
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KD16903
DATA PROCESSOR
9.00 + 0.30 7.00 + 0.20
9.00 + 0.30
7.00 + 0.20 #32
#1 0.80 0.30 + 0.10 0.10 MAX 1.40 + 0.10 170 MAX
(0.70)
+ 0.10 0.127 - 0.05
0-8
0.10 MAX 0.05 MIN 0.50 + 0.20
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