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| K5T6432YT(B)M Document Title Multi-Chip Package MEMORY 64M Bit (4Mx16) Four Bank NOR Flash Memory / 32M Bit (2Mx16) UtRAM MCP MEMORY Revision History Revision No. History 1.0 Final Specification Draft Date Remark November 27, 2001 Final The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices. -1- Revision 1.0 November 2001 K5T6432YT(B)M Multi-Chip Package MEMORY 64M Bit (4Mx16) Four Bank NOR Flash Memory / 32M Bit (2Mx16) UtRAM MCP MEMORY FEATURES * Power Supply voltage : 2.7 to 3.3 V * Organization - Flash : 4,194,304 x 16 bit - UtRAM : 2,097,152 x 16 bit * Access Time (@2.7V) - Flash : 85 ns, UtRAM : 100 ns * Power Consumption (typical value) - Flash Read Current : 20 mA (@5MHz) Sequential Page Read Current : 5 mA (@5MHz) Program/Erase Current : 35 mA (Max.) Standby mode/Deep Power mode : 0.1 A - UtRAM Operating Current : 18 mA Standby Current :120 A Deep Power Down : 5 A * Secode(Security Code) Block : Extra 32KW Block (Flash) * Block Group Protection / Unprotection (Flash) * 128 words Page Program (Flash) * Flash Bank Size : 4Mb / 4Mb / 28Mb / 28Mb * Flash Endurance : 100,000 Program/Erase Cycles * Ambient Temperature : -25C ~ 85C * Endurance : 100,000 Program/Erase Cycles * Package :81 - ball TBGA Type - 10.8 x 10.4 mm, 0.8 mm pitch GENERAL DESCRIPTION The K5T6432YT(B)M featuring single 3.0V power supply is a Multi Chip Package Memory which combines 64Mbit Four Bank Flash and 32Mbit UtRAM. The 64Mbit Flash memory is organized as 4M x16 bit and 32Mbit UtRAM is organized as 2M x16 bit. The 64Mbit Flash memory is the high performance non-volatile memory fabricated by CMOS technology for peripheral circuit and DINOR IV(Diveded bit-line NOR IV) architecture for the memory cell. All memory blocks are locked and can be programmed or erased, when F-WP is low. Using Software Lock Release function, program erase operation can be executed. The 32Mbit UtRAM is fabricated by SAMSUNG' advanced s CMOS technology using one transistor memory cell. The device also supports deep power down mode for low standby current. The K5T6432YT(B)M is suitable for use in program and data memory of mobile communication system to reduce mount area. This device is available in 81-ball TBGA Type package. BALL CONFIGURATION 1 A B C D E F G H J K L M N.C N.C N.C N.C N.C N.C N.C N.C BALL DESCRIPTION 8 9 10 N.C N.C 2 N.C N.C 3 N.C N.C 4 5 6 7 11 12 N.C N.C N.C N.C Ball Name A0 to A20 A21 DQ0 to DQ15 F-RP Description Address Input Balls (Common) Address Input Ball (Flash Memory) Data Input/Output Balls (Common) Hardware Reset (Flash Memory) Write Protect (Flash Memory) Power Supply (Flash Memory) Power Supply (UtRAM)) Ground (Common) Upper Byte Enable (UtRAM) Lower Byte Enable (UtRAM) Chip Enable (Flash Memory) Deep Power Down (UtRAM) Write Enable (Common) Output Enable (Common) Ready/Busy (Flash memory) No Connection N.C A7 LB F-WP WE ZZ A8 A19 A11 A15 A3 A2 A1 A6 A5 UB F-RP A12 F-WP F-Vcc Vcc A18 A17 F-RY/BY A20 A9 A13 A21 A4 A10 A14 N.C Vss UB LB F-CE ZZ A0 F-CE VSS OE DQ1 DQ9 DQ3 DQ4 DQ6 N.C A16 F-Vcc DQ13 DQ15 CS DQ0 DQ10 F-Vcc Vcc DQ12 DQ7 Vss DQ8 DQ2 DQ11 N.C DQ5 DQ14 WE N.C N.C N.C N.C N.C N.C OE F-RY/BY N.C 81 Ball TBGA , 0.8mm Pitch Top View (Ball Down) SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. -2- Revision 1.0 November 2001 K5T6432YT(B)M ORDERING INFORMATION MCP MEMORY K 5 T 64 32 Y T M - T 3 10 Samsung MCP Memory Device Type Mitsubishi NOR Flash + UtRAM UtRAM Access Time 10 = 100 ns Flash Access Time 3 = 85 ns Package T = 81 TBGA Version M = 1st Generation NOR Flash Density (Organization) , (BankSize) 64 : 64Mbit (x16 Selectable) (4Mb, 4Mb, 28Mb,2 8Mb) UtRAM Density , Organization 32Mbit , x16 Selectable Operating Voltage Range 2.7V to 3.3V Block Architecture T = Top Boot Block B = Bottom Boot Block -3- Revision 1.0 November 2001 K5T6432YT(B)M Flash Memory Part MCP MEMORY 128-word Page Buffer Main Block 134 32K-word A21 A20 A19 A18 A17 Address Input A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Bank1 15 blocks Bank2 8 blocks Bank3 56 blocks Main Block 79 32K-word Main Block 78 32K-word Bank4 56 blocks F-Vcc Vss X-decorder Main Block 23 32K-word Main Block 22 32K-word Main Block 15 32K-word Main Block 14 32K-word Main Block 8 32K-word Parameter Block 7 4K-word Parameter Block 2 4K-word Boot Block 1 4K-word Bppt Block 0 4K-word Y-Decorder Y-Gate / Sense Amp. Status/ ID Register Multi Plexer Chip Enable F-CE Output Enable Write Enable OE WE Command User Interface Write State Machine I/O Buffer Write Protect F-WP Reset F-RP /PowerDown DQ15 DQ14 Data I/O DQ1 DQ0 FUNCTIONAL BLOCK DIAGRAM (64Mbit Flash Memory) -4- Revision 1.0 November 2001 K5T6432YT(B)M Table 1. Flash Memory Top Boot Block Address (K5T6432YT) MCP MEMORY Address Range K5T6432YT Block BA134 BA133 BA132 BA131 BA130 BA129 Block Size Word Mode (x16) 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 3FF000H-3FFFFFH 3FE000H-3FEFFFH 3FD000H-3FDFFFH 3FC000H-3FCFFFH 3FB000H-3FBFFFH 3FA000H-3FAFFFH 3F9000H-3F9FFFH 3F8000H-3F8FFFH 3F0000H-3F7FFFH 3E8000H-3EFFFFH 3E0000H-3E7FFFH 3D8000H-3DFFFFH 3D0000H-3D7FFFH 3C8000H-3CFFFFH 3C0000H-3C7FFFH 3B8000H-3BFFFFH 3B0000H-3B7FFFH 3A8000H-3AFFFFH 3A0000H-3A7FFFH 398000H-39FFFFH 390000H-397FFFH 388000H-38FFFFH 380000H-387FFFH 378000H-37FFFFH 370000H-377FFFH 368000H-36FFFFH 360000H-367FFFH 358000H-35FFFFH 350000H-357FFFH 348000H-34FFFFH 340000H-347FFFH 338000H-33FFFFH 330000H-337FFFH 328000H-32FFFFH 320000H-327FFFH 318000H-31FFFFH 310000H-317FFFH 208000H-20FFFFH 300000H-307FFFH 2F8000H-2FFFFFH 2F0000H-2F7FFFH 2E8000H-2EFFFFH 2E0000H-2E7FFFH 2D8000H-2DFFFFH 2D0000H-2D7FFFH Bank4 BA128 BA127 BA126 BA125 BA124 BA123 BA122 BA121 BA120 BA119 BA118 BA117 BA116 Bank3 BA115 BA114 BA113 BA112 BA111 BA110 BA109 BA108 BA107 BA106 BA105 BA104 BA103 BA102 BA101 Bank2 BA100 BA99 BA98 BA97 BA96 BA95 BA94 BA93 BA92 BA91 BA90 -5- Revision 1.0 November 2001 K5T6432YT(B)M Table 1. Flash Memory Top Boot Block Address (K5T6432YT) MCP MEMORY Address Range K5T6432YT Block BA89 BA88 BA87 BA86 BA85 BA84 BA83 BA82 BA81 BA80 BA79 BA78 BA77 Block Size Word Mode (x16) 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 2C8000H-2CFFFFH 2C0000H-2C7FFFH 2B8000H-2BFFFFH 2B0000H-2B7FFFH 2A8000H-2AFFFFH 2A0000H-2A7FFFH 298000H-29FFFFH 290000H-297FFFH 288000H-28FFFFH 280000H-287FFFH 278000H-27FFFFH 270000H-277FFFH 268000H-26FFFFH 260000H-267FFFH 258000H-25FFFFH 250000H-257FFFH 248000H-24FFFFH 240000H-247FFFH 238000H-23FFFFH 230000H-237FFFH 228000H-22FFFFH 220000H-227FFFH 218000H-21FFFFH 210000H-217FFFH 208000H-20FFFFH 200000H-207FFFH 1F8000H-1FFFFFH 1F0000H-1F7FFFH 1E8000H-1EFFFFH 1E0000H-1E7FFFH 1D8000H-1DFFFFH 1D0000H-1D7FFFH 1C8000H-1CFFFFH 1C0000H-1C7FFFH 1B8000H-1BFFFFH 1B0000H-1B7FFFH 1A8000H-1AFFFFH 1A0000H-1A7FFFH 198000H-19FFFFH 190000H-197FFFH 188000H-18FFFFH 180000H-187FFFH 178000H-17FFFFH 170000H-177FFFH 168000H-16FFFFH Bank2 BA76 BA75 BA74 BA73 BA72 BA71 BA70 BA69 BA68 BA67 BA66 BA65 BA64 BA63 BA62 BA61 BA60 BA59 BA58 BA57 BA56 BA55 BA54 BA53 BA52 BA51 Bank1 BA50 BA49 BA48 BA47 BA46 BA45 -6- Revision 1.0 November 2001 K5T6432YT(B)M Table 1. Flash Memory Top Boot Block Address (K5T6432YT) MCP MEMORY Address Range K5T6432YT Block BA44 BA43 BA42 BA41 BA40 BA39 BA38 BA37 BA36 BA35 BA34 BA33 BA32 BA31 BA30 BA29 BA28 BA27 BA26 Block Size Word Mode (x16) 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 160000H-167FFFH 158000H-15FFFFH 150000H-157FFFH 148000H-14FFFFH 140000H-147FFFH 138000H-13FFFFH 130000H-137FFFH 128000H-12FFFFH 120000H-127FFFH 118000H-11FFFFH 110000H-117FFFH 108000H-10FFFFH 100000H-107FFFH F8000H-FFFFFH F0000H-F7FFFH E8000H-EFFFFH E0000H-E7FFFH D8000H-DFFFFH D0000H-D7FFFH C8000H-CFFFFH C0000H-C7FFFH B8000H-BFFFFH B0000H-B7FFFH A8000H-AFFFFH A0000H-A7FFFH 98000H-9FFFFH 90000H-97FFFH 88000H-8FFFFH 80000H-87FFFH 78000H-7FFFFH 70000H-77FFFH 68000H-6FFFFH 60000H-67FFFH 58000H-5FFFFH 50000H-57FFFH 48000H-4FFFFH 40000H-47FFFH 38000H-3FFFFH 30000H-37FFFH 28000H-2FFFFH 20000H-27FFFH 18000H-1FFFFH 10000H-17FFFH 08000H-0FFFFH 00000H-07FFFH Bank1 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16 BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8 BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0 -7- Revision 1.0 November 2001 K5T6432YT(B)M Table 2. Flash Memory Bottom Boot Block Address (K5T6432YB) MCP MEMORY Address Range K5T6432YB Block BA134 BA133 BA132 BA131 BA130 BA129 BA128 BA127 BA126 BA125 BA124 BA123 BA122 BA121 BA120 BA119 BA118 BA117 BA116 BA115 BA114 Block Size Word Mode (x16) 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 3F8000H-3FFFFFH 3F0000H-3F7FFFH 3E8000H-3EFFFFH 3E0000H-3E7FFFH 3D8000H-3DFFFFH 3D0000H-3D7FFFH 3C8000H-3CFFFFH 3C0000H-3C7FFFH 3B8000H-3BFFFFH 3B0000H-3B7FFFH 3A8000H-3AFFFFH 3A0000H-3A7FFFH 398000H-39FFFFH 390000H-397FFFH 388000H-38FFFFH 380000H-387FFFH 378000H-37FFFFH 370000H-377FFFH 368000H-36FFFFH 360000H-367FFFH 358000H-35FFFFH 350000H-357FFFH 348000H-34FFFFH 340000H-347FFFH 338000H-33FFFFH 330000H-337FFFH 328000H-32FFFFH 320000H-327FFFH 318000H-31FFFFH 310000H-317FFFH 208000H-20FFFFH 300000H-307FFFH 2F8000H-2FFFFFH 2F0000H-2F7FFFH 2E8000H-2EFFFFH 2E0000H-2E7FFFH 2D8000H-2DFFFFH 2D0000H-2D7FFFH 2C8000H-2CFFFFH 2C0000H-2C7FFFH 2B8000H-2BFFFFH 2B0000H-2B7FFFH 2A8000H-2AFFFFH 2A0000H-2A7FFFH 298000H-29FFFFH Bank4 BA113 BA112 BA111 BA110 BA109 BA108 BA107 BA106 BA105 BA104 BA103 BA102 BA101 BA100 BA99 BA98 BA97 BA96 BA95 BA94 BA93 BA92 BA91 BA90 -8- Revision 1.0 November 2001 K5T6432YT(B)M Table 2. Flash Memory Bottom Boot Block Address (K5T6432YB) MCP MEMORY Address Range K5T6432YB Block BA89 BA88 BA87 BA86 Block Size Word Mode (x16) 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 290000H-297FFFH 288000H-28FFFFH 280000H-287FFFH 278000H-27FFFFH 270000H-277FFFH 268000H-26FFFFH 260000H-267FFFH 258000H-25FFFFH 250000H-257FFFH 248000H-24FFFFH 240000H-247FFFH 238000H-23FFFFH 230000H-237FFFH 228000H-22FFFFH 220000H-227FFFH 218000H-21FFFFH 210000H-217FFFH 208000H-20FFFFH 200000H-207FFFH 1F8000H-1FFFFFH 1F0000H-1F7FFFH 1E8000H-1EFFFFH 1E0000H-1E7FFFH 1D8000H-1DFFFFH 1D0000H-1D7FFFH 1C8000H-1CFFFFH 1C0000H-1C7FFFH 1B8000H-1BFFFFH 1B0000H-1B7FFFH 1A8000H-1AFFFFH 1A0000H-1A7FFFH 198000H-19FFFFH 190000H-197FFFH 188000H-18FFFFH 180000H-187FFFH 178000H-17FFFFH 170000H-177FFFH 168000H-16FFFFH 160000H-167FFFH 158000H-15FFFFH 150000H-157FFFH 148000H-14FFFFH 140000H-147FFFH 138000H-13FFFFH 130000H-137FFFH Bank4 BA85 BA84 BA83 BA82 BA81 BA80 BA79 BA78 BA77 BA76 BA75 BA74 BA73 BA72 BA71 BA70 BA69 BA68 BA67 BA66 BA65 BA64 BA63 BA62 Bank3 BA61 BA60 BA59 BA58 BA57 BA56 BA55 BA54 BA53 BA52 BA51 BA50 BA49 BA48 BA47 BA46 BA45 -9- Revision 1.0 November 2001 K5T6432YT(B)M Table 2. Flash Memory Bottom Boot Block Address (K5T6432YB) MCP MEMORY Address Range K5T6432YB Block BA44 BA43 BA42 BA41 BA40 BA39 BA38 BA37 BA36 Block Size Word Mode (x16) 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 128000H-12FFFFH 120000H-127FFFH 118000H-11FFFFH 110000H-117FFFH 108000H-10FFFFH 100000H-107FFFH F8000H-FFFFFH F0000H-F7FFFH E8000H-EFFFFH E0000H-E7FFFH D8000H-DFFFFH D0000H-D7FFFH C8000H-CFFFFH C0000H-C7FFFH B8000H-BFFFFH B0000H-B7FFFH A8000H-AFFFFH A0000H-A7FFFH 98000H-9FFFFH 90000H-97FFFH 88000H-8FFFFH 80000H-87FFFH 78000H-7FFFFH 70000H-77FFFH 68000H-6FFFFH 60000H-67FFFH 58000H-5FFFFH 50000H-57FFFH 48000H-4FFFFH 40000H-47FFFH 38000H-3FFFFH 30000H-37FFFH 28000H-2FFFFH 20000H-27FFFH 18000H-1FFFFH 10000H-17FFFH 08000H-0FFFFH 07000H-07FFFH 06000H-06FFFH 05000H-05FFFH 04000H-04FFFH 03000H-03FFFH 02000H-02FFFH 01000H-01FFFH 00000H-00FFFH Bank3 BA35 BA34 BA33 BA32 BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 Bank2 BA18 BA17 BA16 BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8 Bank1 BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0 - 10 - Revision 1.0 November 2001 K5T6432YT(B)M Flash MEMORY COMMAND DEFINITION Table 3. Command List (F-WP = VIH or VIL) 1st Cycle Command Mode Read Array Sequential Page Read Device Identifier Read Status Register Clear Status Register Suspend Resume Notes : Write Write Write Write Write Write Write Address Data (DQ0-15) FFH F3H 90H 70H 50H B0H D0H Read Read Read SA5) RD0 IA3) ID SRD4) 1) MCP MEMORY 2nd Cycle Address Mode A21-A18 A0 Data (DQ0-15) 1) 3rd Cycle Mode Address Data 1) (DQ0-15) X X Bank2) Bank2) X Read SA+i6) RDi Bank2) Bank2) Bank2) Bank2) 1. Upper byte data (DQ15-DQ8) is ignored. 2. Bank=Bank address (bank1-Bank4:A21-18) 3. IA=ID code address:A0=VIL (Manufacture' code):A0=VIH (Device code), ID=ID code s 4. SRD=Status Register Data 5. SA=Sequential page Address:A21-A3, A2-A0:0h 6. SA+i;A21-A3 must be flxed and A2-A0 must be incremented from 0h to 7h. Table 4. Command List (F-WP = VIH) 1st Cycle Command Mode Word Program Page Program Page Buffer to Flash Block Erase / Confirm Erase All Unlocked Blocks Clear Page Buffer Single Date Load to Page Buffer Flash to Page Buffer Notes : Write Write Write Write Write Write Write Write Address Bank Bank Bank Bank X X Bank Bank Data1) (DQ0-15) 40H 41H 0EH 20H A7H 55H 74H F1H Mode Write Write Write Write Write Write Write Write 2nd Cycle Address WA2) WA0 3) WA BA X X WA RA 6) 4) 3rd Cycle Data1) (DQ0-15) WD2) WD03) D0 1) Mode Address Data 1) (DQ0-15) Write WAn3) WDn3) 5) D01) D01) D01) WD D01) 1. Upper byte data (DQ15-DQ8) is ignored. 2. WA=Write Address, WD=Write Data 3. WA0, WAn=Write Address, WD0, WDn=Write Data, Write address and write data must be provided sequentially from 00H to 7FH for A6-A0. Page size is 128 words (128-word x 16-bit), and also A21-A7(block address, page address) must be valid. 4. WA=Write Address:A21-A7 (block address, page address) must be valid. 5. BA=Block Address:A21-A12(Bank1), A21-A15(Bank2, Bank3, Bank4) 6. RA=Read Address:A21-A7 (block address, page address) must be valid. - 11 - Revision 1.0 November 2001 K5T6432YT(B)M Flash MEMORY COMMAND DEFINITION MCP MEMORY Software lock release operation needs following consecutive 7bus cycles. Moreover, additional 127 bus cycles are needed for page program operation. Table 5. Command List (F-WP = VIH or VIL) 1st Cycle Setup Command for Software Lock Release Word Program Page Program 3) 2nd Cycle Data1) (DQ0-15) 60H 60H 60H 60H 60H 60H 60H 60H Mode Write Write Write Write Write Write Write Write Address Bank Bank Bank Bank Bank Bank Bank Bank 5th Cycle Data (DQ0-15) Block6) Block 6) 1) 3rd Cycle Data1) (DQ0-15) Block6) Block 6) 6) 6) 6) Mode Write Write Write Write Write Write Write Write Address Bank Bank Bank Bank Bank Bank Bank Bank 4th Cycle Mode Write Write Write Write Write Write Write Write Address Bank Bank Bank Bank Bank Bank Bank Bank Data 1) (DQ0-15) ACH ACH ACH ACH ACH ACH ACH ACH Page Buffer to Flash Block Erase / Confirm Erase All Unlocked Blocks Clear Page Buffer Single Data Load to Page Buffer Flash to Page Buffer Block Block Block Block6) Block 6) 6) Block Setup Command for Software Lock Release Word Program Page Program 3) Mode Write Write Write Write Write Write Write Write Address Bank Bank Bank Bank Bank Bank Bank Bank Mode Write Write Write Write Write Write Write Write Address Bank Bank Bank Bank Bank Bank Bank Bank Data1) (DQ0-15) 78H 78H 78H 78H 78H 78H 78H 78H Page Buffer to Flash Block Erase / Confirm Erase All Unlocked Blocks Clear Page Buffer Single Data Load to Page Buffer Flash to Page Buffer Block6) Block6) Block6) Block6) Block6) Block6) 6th Cycle Setup Command for Software Lock Release Word Program Page Program 3) 7th Cycle Data (DQ0-15) 40h 41h 0Eh 20H A7H 55H 74H F1H 1) 8th-134th Cycle Data (DQ0-15) WD2) WD03) D01) D01) D01) D01) WD D01) Write WAn3) WDn3) 1) Mode Write Write Write Write Write Write Write Write Address Bank Bank Bank Bank X X Bank Bank Mode Write Write Write Write Write Write Write Write Address WA2) WA0 3) Mode Address Data1) (DQ0-15) Page Buffer to Flash Block Erase / Confirm Erase All Unlocked Blocks Clear Page Buffer Single Data Load to Page Buffer Flash to Page Buffer Notes : WA4) BA 5) X X WA RA7) 1. Upper byte data (DQ15-DQ8) is ignored. 2. WA=Write Address, WD=Write Data 3. WA0, WAn=Write Address, WD0, WDn=Write Data, Write address and write data must be provided sequentially from 00H to 7FH for A6-A0. Page size is 128 words (128 word x 16 bit), and also A21-A7(block address, page address) must be valid. 4. WA=Write Address:A21-A7 (block address, page address) must be valid. 5. BA=Block Address:A21-A12(Bank1), A21-A15(Bank2, Bank3, Bank4) 6. Block=Block Address:A21-A15, Block=A21-A15 Address Block Block DQ7 Fixed0 Fixed0 DQ6 A21 A21 DQ5 A20 A20 DQ4 A19 A19 DQ3 A18 A18 DQ2 A17 A17 DQ1 A16 A16 DQ0 A15 A15 7. RA=Read Address: A21-A7 (block address, page address) must be valid. - 12 - Revision 1.0 November 2001 K5T6432YT(B)M Table 6. Device ID Code Code \ Pins Manufacturer Code Devide Code (Bottom Boot) Devide Code (Top Boot) A0 VIL VIH VIH DQ7 "0" "0" "0" DQ6 "0" "0" "0" DQ5 "0" "1" "1" DQ4 "1" "0" "0" DQ3 "1" "1" "1" DQ2 "1" "0" "0" MCP MEMORY DQ1 "0" "1" "1" DQ0 "0" "0" "1" Hex Date 1CH 2AH 2BH The output of upper byte data (DQ15-DQ7) is "0". Table 7. Block Locking Write Protection Provided F-RP F-WP Boot VIL x VIL VIH Locked Locked Unlocked Bank1 Parameter/Main Locked Locked Unlocked Bank2 Main Locked Locked Unlocked Bank3 Main Locked Locked Unlocked Bank4 Main Locked Locked Unlocked Deep Power Down Mode All Blocks Locked (Valid to operate Software Lock Release) All Blocks Unlocked Notes VIH F-WP pin must not be switched during performing Read / Write operations or WSM busy (WSMS=0). Table 8. Status Register Symbol (I/O Pin) S.R.7 (AQ7) S.R.6 (DQ6) S.R.5 (DQ5) S.R.4 (DQ4) S.R.3 (DQ3) S.R.2 (DQ2) S.R.1 (DQ1) S.R.0 (DQ0) Definition Status "1" Write State Machine Status Suspend Status Erase Status Program Status Block Status after Program Reserved Reserved Reserved Ready Suspended Error Error Error "0" Busy Operation in Progress/Completed Successful Successful Successful - Table 9. Flash Memory Operation Table Mode \ Pins Array Sequential Read Status Register Identifier Code Output Disable Program Write Erase Others Standby Deep Power Down Notes : VIL VIL VIL VIL VIL VIL VIH X VIL VIL VIH VIH VIH VIH X1) X VIH VIH VIH VIL VIL VIL X X VIH VIH VIH VIH VIH VIH VIH VIL Status Register Data Identifier Code High-Z Command / Data-In Command Command High-Z High-z F-CE VIL VIL OE VIL VIL WE VIH VIH F-RP VIH VIH DQ0-15 Data-Output Data-Output 1. X cab be VIH or VIL for control pins - 13 - Revision 1.0 November 2001 K5T6432YT(B)M Flash DEVICE OPERATION MCP MEMORY The 64Mbit DINOR IV Flash Memory includes on-chip program/erase control circuitry. The Write State Machine(WSM) control block erase and word/page program operations. Operational modes are selected by the commands written to the Command User Interface (CUI). The Status Register indicates the status of the WSM and when the WSM successfully completes the desired program or block erase operation. A Deep Power Down mode is enabled when the F-RP pin is at Vss, minimizing power consumption. Read Mode The 64Mbit DINOR IV Flash Memory has four read modes, which accesses to the memory array, the Sequential Page Read, the Device Identifier and the Status Register. The appropriate read commands are required to be written to the CUI. Upon initial device power up or after exit from deep power down, the 64Mbit DINOR IV Flash Memory automatically resets to read array mode. In the read array mode and in the conditions are low level input to OE, high level input to WE and F-RP, low level input to F-CE and address signals to the address inputs (A21 - A0) the data of the addressed location to the data input/output (DQ15-DQ0) is output. Standby Mode When F-CE is at VIH, the device is in the standby mode and its power consumption is reduced. Data input/output are in a highimpedance (High-Z) state. If the memory is deselected during block erase or program, the internal control circuits remain active and the device consumes normal active power until the operation completes. Output Disable When OE is at VIH, output from the devices is disabled. Data input/output are in a high-impedance (High-Z) state. Automatic Power Down (APD) The Automatic Power Down minimizes the power consumption during read mode. The device automatically turns to this mode when any addresses or F-CE isn't changed more than 200ns after the last alternation. The power consumption becomes the same as the stand-by mode. During this mode, the output data is latched and can be read out. New data is read out correctly when addresses are changed. Deep Power Down When F-RP is at VIL, the device is in the deep power down mode and its power consumption is substantially low. During read modes, the memory is deselected and the data input/output are in a high-impedance (High-Z) state. After return from power down, the CUI is reset to Read Array, and the Status Register is cleared to value 80H. During block erase or program modes, F-RP low will abort either operation. Memory array data of the block being altered become invalid. Write Mode Writes to the CUI enables reading of memory array data, device identifiers and reading and clearing of the Status Register. They also enable block erase and program. The CUI is written by bringing WE to low level and OE is at high level, while F-CE is at low level. Address and data are latched on the earlier rising edge of WE and F-CE. Standard micro processor write timings are used. Alternating Background Operation (BGO) The 64Mbit DINOR IV Flash Memory allows to read array from one bank while the other bank operates in software command write cycling or the erasing / programming operation in the background. Array Read operation with the other bank in BGO is performed by changing the bank address without any additional command. When the bank address points the bank in software command write cycling or the erasing / programming operation, the data is read out from the status register. The access time with BGO is the same as the normal read operation. BGO must be between Bank1, Bank2, Bank3, and Bank4. Back Bank array Read (BBR) In the 64Mbit DINOR IV Flash Memory , when one memory address is read according to a Read Mode in the case of the same as an access when a Read Mode command is input, an another Bank memory data can be read out (Random or Sequential Mode) by changing an another Bank address. - 14 - Revision 1.0 November 2001 K5T6432YT(B)M Software Command Definitions MCP MEMORY TThe device operations are selected by writing specific software command into the Commnad User Interface. Read Array Command (FFH) The device is in Read Array mode on initial device power up and after exit from deep power down, or by writing FFH to the Command User Interface. After starting the internal operation the device is set to the read status register mode automatically. Sequential Page Read Command (F3H) The Sequential Page Read command (F3H) timing can be used by writing the first command. This command is fast sequential 8 words read. During the read it is necessary to fix F-CE low and increase the addresses sequentially from 0h to 7h. The mode is kept until Read Array command is input. The first read of Seq. Page Read timing is the same as normal read (ta(CE)). F-CE should be fallen "L". The read timing after the first is fast read (ta(PAD)). When an another sequential page (A21-A3) is accessed before one sequential page (one 8-word) read is not finished, once F-CE is at VIH and A2-A0 data are 0h, after that F-CE is at VIL we can use the first read of Seq. Page Read or normal read (ta(CE)). Read Device Identifier Command (90H) We can normally read device identifier codes when Read Device Identifier Code Command (90H) is written to the command latch. Following the command write, the manufacturer code and the device code can be read from address 0000H and 0001H, respectively. Read Status Register Command (70H) The Status Register is read after writing the Read Status Register command of 70H to the Command User Interface. Also, after starting the internal operation the device is set to the Read Status Register mode automatically. The contents of Status Register are latched on the later falling edge of OE must be toggled every status read. Clear Status Register Command (50H) The Erase Status, Program Status and Block Status bits are set to "1"s by the Write State Machine and can only be reset by the Clear Status Register command of 50H. These bits indicate various failure conditions. status read. Block Erase / Confirm Command (20H/D0H) Automated block erase is initiated by writing the Block Erase command of 20H followed by the Confirm command of D0H. An address within the block to be erased is required. The WSM executes iterative erase pulse application and erase verify operation. Program Commands 1) Word Program (40H) Word program is executed by a two-command sequence. The Word program Setup command of 40H is written to the Command Interface, followed by a second write specifying the address and data to be written. The WSM controls the program pulse application and verify operation. 2) Page Program for Data Blocks (41H) Page Program allows fast programming of 128words of data. Writing of 41H initiates the page program operation for the Data area. From 2nd cycle to 129th cycle, write data must be serially inputted. Address A6-A0 have to be incremented from 00H to 7FH. After completion of data loading, the WSM controls the program pulse application and verify operation. 3) Single Data Load to Page Buffer (74H) / Page Buffer to Flash (0EH/D0H) Single data load to the page buffer is performed by writing 74H followed by a second write specifying the column address and data. Distinct data up to 128word can be loaded to the page buffer by this two-command sequence. On the other hand, all of the loaded data to the page buffer is programmed simultaneously by writing Page Buffer to Flash command of 0EH followed by the confirm command of D0H. After completion of programming the data on the page buffer is cleared automatically. - 15 - Revision 1.0 November 2001 K5T6432YT(B)M Flash to Page Buffer Command (F1H/D0H) MCP MEMORY Array data load to the page buffer is performed by writing the Flash to Page Buffer command of F1H followed by the Confirm command of D0H. An address within the page to be loaded is required. Then the array data can be copied into the other pages within the same bank by using the Page Buffer to Flash command. Clear Page Buffer Command (55H/D0H) Loaded data to the page buffer is cleared by writing the Clear Page Buffer command of 55H followed by the Confirm command of D0H. This command is valid for clearing data loaded by Single Data Load to Page Buffer command. Suspend/Resume Command (B0H/D0H) Writing the Suspend command of B0H during block erase operation interrupts the block erase operation and allows read out from another block of memory. Writing the Suspend command of B0H during program operation interrupts the program operation and allows read out from another block of memory. The Bank address is required when writing the Suspend/Resume Command. The device continues to output Status Register data when read, after the Suspend command is written to it. Polling the WSM Status and Suspend Status bits will determine when the erase operation or program operation has been suspended. At this point, writing of the Read Array command to the CUI enables reading data from blocks other than that which is suspended. When the Resume command of D0H is written to the CUI, the WSM will continue with the erase or program processes. Data Protection The 64M-bit DINOR(IV) Flash Memory has a master Write Protect pin (F-WP). When F-WP is at VIH, all blocks can be programmed or erased. When F-WP is low, all blocks are in locked mode which prevents any modifications to memory blocks. Software Lock Release function is only command which allows to program or erase. See the BLOCK LOCKING table on 13 page for details. Power Supply Voltage When the power supply voltage is less than VLKO, Low Vcc Lock-Out voltage, the device is set to the Read-only mode. Regarding DC electrical characteristics of VLKO, see 18 page. A delay time of 2us is required before any device operation is initiated. The delay time is measured from the time Vcc reaches Vccmin (2.7V). During power up, F-RP = Vss is recommended. Falling in Busy status is not recommended for possibility of damaging the device. Memory Organization The 64Mbit DINOR IV Flash Memory is constructed by 2 boot blocks of 4K words, 6 parameter blocks of 4K words and 7 main blocks of 32K words in Bank1, by 8 main blocks of 32K words in Bank2 and by 56 main blocks of 32K words in Bank3 and Bank4. CAPACITANCE Item Input Capacitance Output Capacitance A21-A0, OE, WE, CS2. F-CE, F-WP, F-RP DQ15-DQ0, F-RY/BY Symbol CIN COUT Test Condition TA=25C, Min Max 8 12 Unit pF pF f=1MHz, Vin=Vout=0V - 16 - Revision 1.0 November 2001 K5T6432YT(B)M ABSOLUTE MAXIMUM RATINGS Parameter F-Vcc Voltage All input or Output Voltage1) Symbol F-Vcc VI1 Ta Tbs Tstg Iout Conditions With Respect to Vss MCP MEMORY Rating -0.2 to +4.6 -0.6 to +4.6 -40 to +85 -50 to +95 -65 to +125 100 (Max.) Unit V Ambient Temperature Temperature under Bias Storage Temperature Outputs Short Circuit Current C mA Notes : 1. Minimum DC voltage is -0.5V on input / output pins. During transitions, the level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input / output pins is F-Vcc+0.5V which, during transitions, may overshoot to F-Vcc+1.5V for periods <20ns. DC CHARACTERISTICS Parameter Input Leakage Current Output Leackage Current Symbol ILI ILO ISB1 Vcc Standby Current ISB2 ISB3 Vcc Deep Power Down Current ISB4 ICC1 ICC1P ICC2 ICC3 ICC4 ICC5 VIL VIH VOL VOH1 Output High Voltage VOH2 Low F-Vcc Lock Out Voltage 2) Notes : Test Conditions 0V Typ1) Max Unit A A A A A A mA mA mA mA mA mA mA 1.0 1.0 50 0.1 5 0.1 20 4 5 200 5 15 5 30 8 10 15 35 35 200 -0.5 2.0 0.8 F-Vcc +0.5 0.45 0.85x F-Vcc F-Vcc -0.4 1.5 2.2 Vcc Read Current for Word Vcc Sequential Page Read Current Vcc Write Current for Word Vcc Program Current Vcc Erase Current Vcc Suspend Current Input Low Voltage Input High Voltage Output Low Voltage V V V V V V IOL=4.0mA IOH=-2.0mA IOL=4-100A VLKO All currents are in RMS unless otherwise noted 1. Typical values at F-Vcc=3.0V, Ta=25C. 2. To protect initiation of write cycle during F-Vcc power up / down, a write cycle is locked out for F-Vcc less than VLKO, Write State Machine is in Busy state, if F-Vcc is less than VLKO, the alteration of memory contents may occur. - 17 - Revision 1.0 November 2001 K5T6432YT(B)M AC CHARACTERISTICS Read Only Mode Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Sequential Page Access Time (After 2nd Cycle) Sequential Page Setup Time Sequential Page Read F-CE "H" Time Maximum Valid Time of Sequential Page Read Chip Enable to Output in Low-Z Chip Enable High to Output in High-Z Output Enablr to Output in Low-Z Output Enable to High to Output in High-Z F-RP Low to Output High-Z Output Hold from F-CE , OE and Address OE hold from WE High F-RP Recovery to CE Low tRC ta(AD) ta(CE) ta(OE) ta(PAD) tASPR tCEHRR tRPCRR tCLZ tDF(CE) tOLZ tDF(OE) tPHZ tOH tOEH tPS tELQX tEHQZ tGLQX tGHQZ tPLQZ tOH tWHGL tPHEL 0 10 150 0 0 -20 15 Symbol tAVAV tAVQV tELQV tGLQV MCP MEMORY Vcc=2.7V~3.3V Min 85 85 85 30 45 Typ Max Unit ns ns ns ns ns ns ns 20 ns ns 25 ns ns 25 150 ns ns ns ns ns Notes : 1. Timing measurements are made under AC waveforms for read operation. Read / Write Mode (WE Control) Parameter Wrie Cycle Time Address Setup Time Address Hold Time Data Setup time Data Hold time OE Holf from WE High Chip Enable Setup Time Chip Enable Hold Time Write Pulse Width Write Pulse Width High OE Hold to WE Low Block Lock Setup to Write Enable High Block Lock Hold from Valid SRD tWC tAS tAH tDS tDH tOEH tCS tCH tWP tWPH tGHWL tBLS tBLH Symbol tAVAV tAVWH tWHAX tDVWH tWHDX tWHGL tELWL tWHEH tWLWH tWHWL tGHWL tPHHWH tQVPH tWHRH1 tWHRH1 tWHRH2 tWHRL tPHWL 150 Vcc=2.7V~3.3V Min 85 35 0 35 0 10 0 0 35 30 0 85 0 30 4 150 Typ Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns s ms ms ns ns Duration of Auto Program Operation (Word Mode) tDAP Duration of Auto Program Operation (Page Mode) tDAP Duration of Auto Block Erase Operation Delay Time to Begin Internal Operation F-RP Recovery to F-CE Low tDAE tWHRL tPS 300 80 600 85 Notes : 1. Read timing parameters during command write operations mode are the same as during read only operation mode. 2. Typical values at F-Vcc=3.0V and Ta=25C. - 18 - Revision 1.0 November 2001 K5T6432YT(B)M AC CHARACTERISTICS Read / Write Mode (CE Control) Parameter Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time OE Hold from WE High Write Enable Setup Time Write Enable Hold Time F-CE Pulse Width F-CE "H" Pulse Width OE Hold to WE Low Block Lock Setup to Write Enable High Block Lock Hold from Valid SRD tWC tAS tAH tDS tDH tOEH tWS tWH tCEP tCEPH tGHEL tBLS tBLH Symbol tAVAV tAVWH tWHAX tDVWH tWHDX tWHGL tWLEL tEHWH tELEH tEHEL tGHEL tPHHWH tQVPH tWHRH1 tWHRH1 tWHRH2 tEHRL tPHWL 150 MCP MEMORY Vcc=2.7V~3.3V Min 85 35 0 35 0 10 0 0 35 30 85 85 0 30 4 150 300 Typ Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns s ms ms ns ns Duration of Auto Program Operation (Word Mode) tDAP Duration of Auto Program Operation (Page Mode) tDAP Duration of Auto Block Erase Operation Delay Time to Begin Internal Operation F-RP Recovery to F-CE Low tDAE tEHRL tPS 80 600 90 Notes : 1. Timing measurements are made under AC waveforms for read operations 2. Typical values at F-Vcc=3.0V and Ta=25C. Program / Erase Time Parameter Block Erase Time Main Block Write Time Page Write Time Flash to Page Buffer Time Min Typ 150 1 4 100 Max 600 4 80 150 Unit ms sec ms s Program Suspend / Erase Suspend Time Parameter Program Suspend Time Erase Suspend Time Min Typ Max 15 15 Unit s s F-Vcc Power up / Down timing Parameter tVCS F-RP=VIH Setup Time from F-Vcc min. Min 2 Typ Max 15 Unit s Please see 21 page. During power up / down, by the noise pulses on control pins, the device has possibility of accidental erase of programming. The device must be protected against initiation of write cycle for memory contents during power up / down. The delay time of min. 2 micro sec is always required before read operation or write operation is initiated from the time F-Vcc reaches F-Vcc min. during power up /down. By holding F-RP=VIL, the contents of memory is protected during F-Vcc power up / down. During power up, F-RP must be held VIL for min. 2us form the time F-Vcc reaches F-Vcc min.. During power down, F-RP must be held VIL until F-Vcc reaches Vss. F-RP doesn' have latch mode, therefore F-RP must be t held VIH during read operation or erase / program operation. - 19 - Revision 1.0 November 2001 K5T6432YT(B)M F-Vcc Power up / dowm Timing Read /Write Inhibit Read /Write Inhibit MCP MEMORY Read /Write Inhibit VCC 3.0V Vss tVCS VIH F-RP VIL VIH F-CE VIL tPS VIH tPS WE VIL AC Waveforms for Read Operation and Test Conditions tRC VIH Address Address VIL ta(AD) VIH F-CE VIL ta(CE) VIH tDF(CE) OE VIL tOEH VIH tDF(OE) ta(OE) VIL tOLZ VIH tOH High-Z tPHZ High-Z tPS VIH tCLZ or WE DATA VIL F-RP VIL 1.3V 1N914 TEST CONDITIONS FOR AC CHARACTERISTICS Input Voltage: VIL=0V, VIH=Flash VCC Input Rise and Fall Times: 5ns Reference Voltage at timing measurement: (Flash VCC)/2 Output Load: 1TTL gate + CL(30pF) 3.3kohm DUT - 20 - Revision 1.0 November 2001 K5T6432YT(B)M AC Waveforms for Sequential Page Read Operation Address A21 ~ A3 VIH Address VIL Address VIH MCP MEMORY A2 ~ A0 Address 0H 1H 2H 3H 4H 5H 6H 7H VIL VIH F-CE VIL VIH OE VIL VIH WE VIL VIH High-Z F3H VIL ta(AD) ta(CE) ta(PAD) DOUT ta(PAD) Valid ta(PAD) Valid ta(PAD) Valid ta(PAD) Valid ta(PAD) Valid ta(PAD) Valid Valid DATA - 21 - Revision 1.0 November 2001 K5T6432YT(B)M AC Waveforms for Word Program Operation(WE Control) Address A21 ~ A0 VIH VIL VIH Bank Address Valid tWC MCP MEMORY Address Vaild tAS Program tAH Bank Address Read Status Register Write Read Register F-CE VIL tCS VIH tCH ta(CE) OE VIL tWP VIH tWPH tOEH ta(OE) WE VIL tDS VIH High-Z tPS tWHRL DIN tDH SR Busy SR Ready DATA 40H FFH VIL VIH F-RP VIL tBLS VIH tDAP tBLH F-WP VIL AC Waveforms for Word Program Operation(CE Control) Address A21 ~ A0 VIH VIL VIH Bank Address Valid tWC Address Vaild tAS Program tAH Bank Address Valid Read Status Register Write Read Register F-CE VIL ta(CE) VIH OE VIL tWS VIH tCEP tWH tOEH ta(OE) WE VIL tDS VIH High-Z tPS tEHRL DIN tDH SR Busy SR Ready DATA 40H FFH VIL VIH F-RP VIL tBLS VIH tDAP tBLH F-WP VIL - 22 - Revision 1.0 November 2001 K5T6432YT(B)M AC Waveforms for Page Program Operation(WE Control) Address VIH A21 ~ A7 VIL VIH 00H VIL tWC tAS tAH Vaild 01H-7EH 7FH Bank Address Vaild The Other Bank Address Vaild MCP MEMORY Address Vaild Address Vaild Bank Address Vaild Read Status Register Write Read Register A6 ~ A0 ta(CE) F-CE VIH VIL tCS VIH tCH ta(CE) tGHWL tWP VIH tWPH tOEH ta(OE) tOEH ta(OE) OE VIL WE VIL tDH VIH tWHRL DOU tDS VIH DIN DIN SR Busy SR Ready DATA VIL High-Z 41H DIN FFH tDAP F-RP VIL tBLS VIH tBLH F-WP VIL AC Waveforms for Page Program Operation(CE Control) Address VIH A21 ~ A7 VIL VIH 00H VIL tWC VIH tAS tAH ta(CE) Vaild 01H-7EH 7FH Bank Address Vaild The Other Bank Address Vaild Address Vaild Address Vaild Bank Address Vaild Read Status Register Write Read Register A6 ~ A0 F-CE VIL tWS VIH tWH tCEPH tCEP VIH tOEH ta(OE) ta(CE) tGHWL tOEH ta(OE) OE VIL WE VIL tDH tEHRL DOU tDS DIN DIN SR Busy SR Ready DATA VIH VIL VIH High-Z tPS 41H DIN FFH tDAP F-RP VIL tBLS VIH tBLH F-WP VIL - 23 - Revision 1.0 November 2001 K5T6432YT(B)M AC Waveforms for Erase Operation(WE Control) Address VIH A21 ~ A0 VIL VIH Bank Address Vaild MCP MEMORY Address Vaild Bank Address tWC tAS tAH Erase Read Status Register Write Read Register F-CE VIL tCS VIH tCH tWP tWPH VIH tOEH ta(OE) ta(CE) OE VIL WE VIL tDS tWHRL DOH tDH SR Busy SR Ready DATA VIH VIL VIH High-Z tPS 20H FFH F-RP VIL tBLS VIH tDAE tBLH F-WP VIL AC Waveforms for Erase Operation(CE Control) Address VIH A21 ~ A0 VIL VIH VIL ta(CE) VIH Bank Address Vaild Address Vaild Bank Address tWC tAS tAH Erase Read Status Register Write Read Register F-CE OE VIL tWS VIH tCEP tWH tOEH ta(OE) WE VIL tDS tWHRL DOH tDH SR Busy SR Ready DATA VIH VIL VIH High-Z tPS 20H FFH F-RP VIL tBLS VIH tDAE tBLH F-WP VIL - 24 - Revision 1.0 November 2001 K5T6432YT(B)M AC Waveforms for Word Program Operation with BGO(WE Control) Address VIH A21 ~ A7 VIL VIH Address Vaild MCP MEMORY Change Bank Address Read Array in another bank Address Vaild Address Vaild Program in one bank Bank Address Vaild Read Status Register Address Vaild A6 ~ A0 Address Vaild Address Vaild VIL tWC tAS tAH VIH VIL tCS VIH tCH tWP VIL tWPH VIH tOEH Program F-CE ta(CE) OE ta(OE) WE VIL tDS VIH tWHRL DIN tDH SR Busy DATA VIL High-Z 40H DOUT DOUT AC Waveforms for Word Program Operation with BGO(CE Control) Address VIH A21 ~ A7 VIL VIH Address Vaild Address Vaild Address Vaild Program in one bank Bank Address Vaild Read Status Register Address Vaild Change Bank Address Read Array in another bank Address Vaild Address Vaild A6 ~ A0 VIL tWC tAS tAH VIH VIL Program F-CE ta(CE) VIH OE VIL tWS VIH tCEP tWH tOEH ta(OE) WE VIL tDS tEHRL DIN tDH SR Busy DATA VIH VIL High-Z 40H DOUT DOUT - 25 - Revision 1.0 November 2001 K5T6432YT(B)M AC Waveforms for Page Program Operatio with BGO(WE Control) Program in one bank MCP MEMORY Change Bank Address Read Array in another bank Address Vaild Address Vaild Address VIH A21 ~ A7 VIL A6 ~ A0 VIH Bank Address Vaild Address Vaild 00H Valid 01H-7EH 7FH Address Vaild Address Vaild VIL tWC tAS tAH ta(CE) VIH VIL tCS VIH tCH ta(CE) tGHWL ta(OE) tOEH ta(OE) F-CE OE VIL tWP VIH tWPH tOEH WE VIL tDH VIH tWHRL DOU tDS DIN DIN SR Busy DATA VIL High-Z 41H DIN DOUT DOUT AC Waveforms for Page Program Operatio with BGO(CE Control) Program in one bank Change Bank Address Read Array in another bank Address Vaild Address Vaild Address VIH A21 ~ A7 VIL A6 ~ A0 VIH Bank Address Vaild Address Vaild 00H Valid 01H-7EH 7FH VIL tWC tAS tAH ta(CE) VIH VIL tWS VIH tWH ta(CE) tGHEL ta(OE) ta(OE) F-CE OE VIL tCEP VIH tCEPH tOEH WE VIL tDH tEHRL DOUT tDS DIN DIN tEHRL SR Busy DATA VIH VIL High-Z 41H DIN DOUT DOUT - 26 - Revision 1.0 November 2001 K5T6432YT(B)M AC Waveforms for Erase Operation with BGO(WE Control) Program in one bank Read Status Register Address Vaild MCP MEMORY Change Bank Address Read Array in another bank Address Vaild Address Vaild Address VIH A21 ~ A0 VIL VIH Bank Address Vaild tWC tAS tAH F-CE VIL tCS VIH tCH tWP tWPH VIH tOEH ta(OE) ta(CE) OE VIL WE VIL tDS tWHRL DOH tDH SR Busy DATA VIH VIL High-Z 20H DOUT DOUT AC Waveforms for Erase Operation with BGO(CE Control) Address VIH A21 ~ A0 VIL VIH VIL ta(CE) VIH Program in one bank Bank Address Vaild Read Status Register Address Vaild Change Bank Address Read Array in another bank Address Vaild Address Vaild tWC tAS tAH F-CE OE VIL tWS VIH tCEP tWH tOEH ta(OE) WE VIL tDS tEHRL DOH tDH SR Busy DATA VIH VIL High-Z 20H DOUT DOUT - 27 - Revision 1.0 November 2001 K5T6432YT(B)M AC Waveforms for Suspend Operation(WE Control) Address VIH A21 ~ A0 VIL VIH VIL tCS VIH tCH MCP MEMORY Bank Address Vaild Bank Address Vaild tAS tAH Read Status Register F-CE ta(CE) OE VIL tWP VIH tOEH ta(OE) WE VIL Suspend Time S.R.6,7=1 SR Busy DATA VIH VIL VIH High-Z B0H F-RP VIL VIH tBLS tBLH F-WP VIL AC Waveforms for Suspend Operation(CE Control) Address VIH A21 ~ A0 VIL VIH VIL tOEH VIH ta(CE) Bank Address Vaild Bank Address Vaild tAS tAH Read Status Register F-CE OE VIL tWS VIH tCEP tWH ta(OE) WE VIL Suspend Time VIH High-Z S.R.6,7=1 SR Busy DATA VIL VIH B0H F-RP VIL VIH tBLS tBLH F-WP VIL - 28 - Revision 1.0 November 2001 K5T6432YT(B)M Word Program Flow Chart START Write 40H Write Address, Data Status Register Read No Write BOH? Yes Suspend Loop Write D0H Yes SR.7=1? Yes Full Status Check If Desired Page Program Completed No No MCP MEMORY Page Program Flow Chart START Write 41H n=0 Write Address n, DATA n No n=0 n=7FH? Yes Status Register Read SR.7=1? Yes Full Status Check If Desired Word Program Completed Write BOH? Yes Suspend Loop Write D0H Yes No Block Erase Flow Chart START Write 20H Write D0H Block Address Status Register Read No Write BOH? Yes Suspend Loop Write D0H Yes No Status Register Check Flow Chart START YES SR.4,5=1? No No SR.5=0? YES No SR.4=0? YES No SR.3=0? YES Pass (Block Erase, Program) Command Sequence Error SR.7=1? Yes Full Status Check If Desired Erase Completed Block Erase Error Program Error (Page Program) Block Erase Error (Block Fail) - 29 - Revision 1.0 November 2001 K5T6432YT(B)M Single Data Load to Page Buffer Flow Chart START Write B0H Write 74H Status Register Read No MCP MEMORY Suspend / Resume Flow Chart START Suspend Write Address, Data Load Finished? No S.R.7=1? Yes S.R.6=1? Yes Write FFH No Single Data Load To Page Buffer Completed Erase/Program Finished Read Array Data Read Finished? Yes No Page Buffer to Flash Flow Chart START Write 0H Write D0H Page Address Status Register Read No Write BOH? Yes Suspend Loop Write D0H Page Buffer To Flash Completed Yes No Write D0H Resume Operation Restart Clear Page Buffer Flow Chart START SR.7=1? Yes Full Status Check If Desired Write 55H Write D0H Clear Page Buffer Completed - 30 - Revision 1.0 November 2001 K5T6432YT(B)M Operation Status (WP=VIH) F3H MCP MEMORY Read/Standby State FFH (Sequential Page Read Mode) Read/Standby State (Read Array Mode) Clear Status Register Read Device Identifier Seq. Page Read Read Array (From the other Bank) Change Bank Address FFH (Read Array) F3H (Seq. Page) Read Array 50H Read Status Register 70H 90H 90H 70H FFH (Read Array) F3H (Seq. Page) D0H WD D0H Setup State Clear Page Bufer Setup 55H 74H F1H 0EH 41H 40H 20H A7H Single Data Load to Page Bufer Setup Flash Page Burrer Setup Page Buffer to Flash Setup Page Program Setup Word Program Setup Block Erase Setup Erase All Unlocked Blocks Setup Other D0H Wdi I=0-127 WD Internal State B0H B0H D0H D0H Other Ready Program & Verift D0H Read Status Register D0H Erase & Verift Read Status Register Change Bank Address Suspend State Read Status Register 70H Read State with BGO Read Array (From the other Bank) Seq. Page Read Change Bank Address FFH (Read Array) F3H (Seq. Page) Read Array - 31 - Revision 1.0 November 2001 K5T6432YT(B)M Operation Status (WP=VIL) MCP MEMORY F3H Seq. Page Read Read Array (From the other Bank) Change Bank Address Read/Standby State FFH (Sequential Page Read Mode) Read/Standby State (Read Array Mode) Read Status Register 70H Single Data Load to Page Bufer Setup 7BH Single Data Load to Page Bufer Setup BA * Single Data Load ACH Single Data Load to Page Bufer Setup to Page Bufer Setup BA * 70H FFH (Read Array) F3H (Seq. Page) Single Data Load to Page Bufer Setup 60H Read Device Identifier 90H 90H FFH (Read Array) F3H (Seq. Page) Other Read Array 50H D0H WD D0H Clear Status Register 55H 74H F1H 0EH 41H 40H 20H A7H Setup State Clear Page Bufer Setup Single Data Load to Page Bufer Setup Flash Page Burrer Setup Page Buffer to Flash Setup Page Program Setup Word Program Setup Block Erase Setup Erase All Unlocked Blocks Setup D0H Wdi i=0-127 WD Internal State B0H B0H D0H D0H Program & Verift Ready Read Status Register D0H D0H Erase & Verift Read Status Register Change Bank Address Suspend State Read Status Register 70H Read State with BGO Read Array (From the other Bank) Seq. Page Read Change Bank Address FFH (Read Array) F3H (Seq. Page) Read Array - 32 - Revision 1.0 November 2001 K5T6432YT(B)M UtRAM Part MCP MEMORY Clk gen. Precharge circuit. Vcc Vss Row Addresses Row select Memory array I/O1~I/O8 Data cont Data cont Data cont I/O Circuit Column select I/O9~I/O16 Column Addresses CS ZZ OE WE UB LB Control Logic FUNCTIONAL BLOCK DIAGRAM (32Mbit UtRAM) FUNCTIONAL DESCRIPTION CS H X1) L L L L L L L L L ZZ H L H H H H H H H H H OE X 1) WE X 1) LB X 1) UB X 1) I/O1~8 High-Z High-Z High-Z High-Z High-Z Dout High-Z Dout Din High-Z Din I/O9~16 High-Z High-Z High-Z High-Z High-Z High-Z Dout Dout High-Z Din Din Mode Deselected Deselected Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write Power Standby Deep Power Down Standby Active Active Active Active Active Active Active Active X1) X1) H H L L L X1) X 1) X1) X1) H H H H H L L L X1) H L X 1) X1) H X1) L H L L H L L L H L L H L X1) 1. X means don' care.(Must be low or high state) t - 33 - Revision 1.0 November 2001 K5T6432YT(B)M ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Symbol VIN, VOUT VCC PD TSTG TA MCP MEMORY Ratings -0.2 to VCC+0.3V -0.2 to 3.6V 1.0 -65 to 150 -25 to 85 Unit V V W C C 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions longer than 1seconds may affect reliability. STANDBY MODE STATE MACHINES CS=VIH Power On Initial State (Wait 200s) CS=VIL, UB or/and LB=VIL ZZ=VIH CS=VIH ZZ=VIH ZZ=VIL Deep Power Down Mode CS=VIH, ZZ=VIH Standby Mode Active ZZ=VIL Read Operation Twice STANDBY MODE CHARACTERISTIC Power Mode Standby Deep Power Down Memory Cell Data Valid Invaild Standby Current(A) 150 20 Wait Time(s) 0 200 RECOMMENDED DC OPERATING CONDITIONS1) Item Supply voltage Ground Input high voltage Input low voltage 1. TA=-25 to 85C, otherwise specified. 2. Overshoot: Vcc+1.0V in case of pulse width 20ns. 3. Undershoot: -1.0V in case of pulse width 20ns. 4. Overshoot and undershoot are sampled, not 100% tested. Symbol Vcc Vss VIH VIL Min 2.7 0 2.2 -0.23) Typ 3.0 0 - Max 3.3 0 Vcc+0.2 0.6 2) Unit V V V V CAPACITANCE1) (f=1MHz, TA=25C) Item Input capacitance Input/Output capacitance 1. Capacitance is sampled, not 100% tested. Symbol CIN CIO Test Condition VIN=0V VIO=0V Min - Max 8 10 Unit pF pF - 34 - Revision 1.0 November 2001 K5T6432YT(B)M DC AND OPERATING CHARACTERISTICS Item Input leakage current Output leakage current Average operating current Symbol MCP MEMORY Test Conditions VIN=Vss to Vcc CS=VIH, ZZ=VIH, OE=VIH or WE=VIL, VIO=Vss to Vcc Cycle time=1s, 100% duty, IIO=0mA, CS0.2V, ZZVcc-0.2V, VIN0.2V or VINVCC-0.2V Cycle time=Min, IIO=0mA, 100% duty, CS=VIL, ZZ=VIH, VIN=VIL or VIH Min -1 -1 2.4 - Typ 1) 2 18 120 5 Max 1 1 5 25 0.4 150 20 Unit A A mA mA V V A A ILI ILO ICC1 ICC2 Output low voltage Output high voltage Standby Current(CMOS) Deep Power Down VOL VOH ISB1 ISBD IOL=2.1mA IOH=-1.0mA CSVcc-0.2V, ZZVcc-0.2V, Other inputs=Vss to Vcc ZZ0.2V, Other inputs=Vss to Vcc 1. Typical values are tested at VCC=3.0V, TA=25C and not guaranteed. AC OPERATING CONDITIONS TEST CONDITIONS(Test Load and Test Input/Output Reference) Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage: 1.5V Output load(See right): CL=50pF Dout RL=50 VL=1.5V Z0=50 50pF* * Include scope and jig capacitance AC CHARACTERISTICS(Vcc=2.7~3.3V, TA=-25 to 85C) Speed Bins Parameter List Symbol Min Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output UB, LB Access Time Read Chip Select to Low-Z Output UB, LB Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output UB, LB Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write UB, LB Valid to End of Write Write Write Pulse Width Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z tRC tAA tCO tOE tBA tLZ tBLZ tOLZ tHZ tBHZ tOHZ tOH tWC tCW tAS tAW tBW tWP tWR tWHZ tDW tDH tOW 100 10 10 5 0 0 0 5 100 80 0 80 80 70 0 0 40 0 5 100ns 1) 100ns2) Max 100 100 50 100 25 25 25 30 Min 100 10 10 5 0 0 0 5 110 100 0 100 100 100 0 0 40 0 5 Max 100 100 50 100 25 25 25 30 - Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1. The characteristics which is restricted for continuous write operation over 20 times, please refer to technical note. 2. The characteristics for continuous write operation. - 35 - Revision 1.0 November 2001 K5T6432YT(B)M UtRAM TIMING DIAGRAMS MCP MEMORY TIMING WAVEFORM OF READ CYCLE(1)(Address Controlled, CS=OE=VIL, ZZ=WE=VIH, UB or/and LB=VIL) tRC Address tOH Data Out Previous Data Valid tAA Data Valid TIMING WAVEFORM OF READ CYCLE(2)(ZZ=WE=VIH) tRC1 Address tAA tRC2 CS tCO tHZ tBA UB, LB tBHZ tOE OE tOLZ tBLZ tLZ Data Valid tOHZ tOH Data out High-Z (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 3. The minimum read cycle(tRC) is determined later one of the tRC1 and tRC2. - 36 - Revision 1.0 November 2001 K5T6432YT(B)M TIMING WAVEFORM OF WRITE CYCLE(1)(WE Controlled, ZZ=VIH) tWC Address tCW(2) CS tAW tBW tWP(1) WE tAS(3) Data in High-Z tWHZ Data out Data Undefined tDW Data Valid tDH tWR(4) MCP MEMORY UB, LB High-Z tOW TIMING WAVEFORM OF WRITE CYCLE(2)(CS Controlled, ZZ=VIH) tWC Address CS tAS(3) UB, LB tCW(2) tAW tBW tWR(4) tWP(1) WE tDW Data in Data Valid tDH Data out High-Z High-Z - 37 - Revision 1.0 November 2001 K5T6432YT(B)M TIMING WAVEFORM OF WRITE CYCLE(3)(UB, LB Controlled, ZZ=VIH) tWC Address tCW(2) CS tAW tBW UB, LB tAS(3) tWP(1) WE tDW Data in Data Valid tDH tWR(4) MCP MEMORY Data out High-Z High-Z (WRITE CYCLE) 1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high. TIMING WAVEFORM OF DEEP POWER DOWN MODE Read Operation Twice or Stay High during 300s 200s ZZ Normal Operation MODE 0.5s Suspend Wake up Normal Operation Deep Power Down Mode CS - 38 - Revision 1.0 November 2001 K5T6432YT(B)M TIMING WAVEFORM OF POWER UP(1) MCP MEMORY Read Operation Twice 200s VCC ZZ CS TIMING WAVEFORM OF POWER UP(2)(No Dummy Cycle) 200s 300s VCC ZZ CS - 39 - Revision 1.0 November 2001 K5T6432YT(B)M PACKAGE DIMENSION 81-Ball Tape Ball Grid Array Package (measured in millimeters) MCP MEMORY Top View Bottom View 10.8.000.10 A 10.800.10 (Datum A) 12 11 10 0.80 A B 9 0.80x11=8.80 8 7 6 5 4 3 2 1 B #A1 (Datum B) 10.400.10 D E F G H 0.80 0.80x11=8.80 4.40 0.320.05 1.100.10 0.450.05 C 4.40 J K L M 81- 0.450.05 0.20 M A B Side View 0.08MAX 10.400.10 - 40 - Revision 1.0 November 2001 10.400.10 |
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