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EL7232
Data Sheet July 5, 2006 FN7283.2
Dual Channel, High Speed, High Current Line Driver with 3-State
The EL7232 3-state drivers are particularly well suited for ATE and microprocessor based applications. The low quiescent power dissipation makes this part attractive in battery applications. The 2A peak drive capability, makes the EL7232 an excellent choice when driving high speed capacitive lines, as well. The input circuitry provides level shifting from TTL levels to the supply rails. The EL7232 is available in 8-pin PDIP and 8-lead SO packages.
Features
* 3-State output * 3V and 5V input compatible * Clocking speeds up to 10MHz * 20ns Switching/delay time * 2A Peak drive * Low, matched output impedance 5 * Low quiescent current 2.5mA * Wide operating voltage 4.5V-16V
Ordering Information
PART NUMBER EL7232CN EL7232CNZ EL7232CS EL7232CS-T7 EL7232CSZ (See Note) EL7232CSZ-T7 (See Note) PART MARKING EL7232CN PACKAGE 8 Ld PDIP TAPE & REEL 7" 7" 13" PKG. DWG. # MDP0031 MDP0031 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027
* Pb-Free available (RoHS compliant)
Applications
* Parallel bus line drivers * EPROM and PROM programming * Motor controls * Charge pumps * Sampling circuits * Pin drivers * Bridge circuits
EL7232CN Z 8 Ld PDIP* 7232CS 7232CS 7232CSZ 7232CSZ 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free)
EL7232CSZ-T13 7232CSZ (See Note)
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
Pinout
EL7232 (8-PIN PDIP, SO) TOP VIEW
3-STATE A IN 3-STATE B IN V+ A OUT B OUT GND
Manufactured under U.S. Patent Nos. 5,334,883, #5,341,047
Truth Table
3-STATE 1 1 0 0 INPUT 0 1 0 1 OUTPUT 1 0 Open Open
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2003, 2005-2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
EL7232
Absolute Maximum Ratings (TA = 25C)
Supply (V+ to Gnd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5V Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V above V+ Combined Peak Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . .4A Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 125C Power Dissipation SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .570mW PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1050mW
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
DC Electrical Specifications
PARAMETER INPUT VIH IIH VIL IIL VHVS OUTPUT ROH ROL IOFF IPK IDC Pull-Up Resistance Pull-Down Resistance Logic "1" Input Voltage Logic "1" Input Current Logic "0" Input Voltage Logic "0" Input Current Input Hysteresis
TA = 25C, V = 15V unless otherwise specified TEST CONDITIONS MIN TYP MAX UNITS
DESCRIPTION
2.4 @V+ 0.1 10 0.8 @0V 0.1 0.3 10
V A V A V
IOUT = -100 mA IOUT = +100 mA VOUT = V+ VOUT = 0V Source Sink Source/Sink 100 0.2
3 4
6 6 10
A A mA
3-State Output Leakage Peak Output Current Continuous Output Current
2.0 2.0
POWER SUPPLY IS VS Power Supply Current Operating Voltage TA = 25C, V = 15V unless otherwise specified TEST CONDITIONS MIN TYP MAX UNITS Inputs High 4.5 1 2.5 16 mA V
AC Electrical Specifications
PARAMETER SWITCHING CHARACTERISTICS tR tF tD-ON tD-OFF Rise Time Fall Time Turn-On Delay Time Turn-Off Delay Time
DESCRIPTION
CL = 500pF CL = 1000pF CL = 500pF CL = 1000pF
7.5 10 10 13 18 20 20 25 25
ns ns ns ns
2
EL7232 Timing Table
Standard Test Configuration
Simplified Schematic
3
EL7232 Typical Performance Curves
MAX POWER/DERATING CURVES SWITCH THRESHOLD vs SUPPLY VOLTAGE
INPUT CURRENT vs VOLTAGE
PEAK DRIVE vs SUPPLY VOLTAGE
QUIESCENT SUPPLY CURRENT
"ON" RESISTANCE vs SUPPLY VOLTAGE
4
EL7232 Typical Performance Curves
(Continued)
AVERAGE SUPPLY CURRENT vs CAPACITIVE LOAD
AVERAGE SUPPLY CURRENT vs VOLTAGE AND FREQUENCY
RISE/FALL TIME vs LOAD
RISE/FALL TIME vs SUPPLY VOLTAGE
5
EL7232 Typical Performance Curves
(Continued)
RISE/FALL TIME vs TEMPERATURE
PROPAGATION DELAY vs SUPPLY VOLTAGE
PROPAGATION DELAY vs TEMPERATURE
6
EL7232 Small Outline Package Family (SO)
A D N (N/2)+1 h X 45
A E E1 PIN #1 I.D. MARK c SEE DETAIL "X"
1 B
(N/2) L1
0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X
SEATING PLANE L 4 4
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150") 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300") (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX 0.003 0.002 0.003 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. L 2/01
7
EL7232 Plastic Dual-In-Line Packages (PDIP)
D E N PIN #1 INDEX
SEATING PLANE L e b
A2
A c
E1
A1 NOTE 5
eA eB
1
2 b2
N/2
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE SYMBOL A A1 A2 b b2 c D E E1 e eA eB L N NOTES: 1. Plastic or metal protrusions of 0.010" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane. 4. Dimension eB is measured with the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. PDIP8 0.210 0.015 0.130 0.018 0.060 0.010 0.375 0.310 0.250 0.100 0.300 0.345 0.125 8 PDIP14 0.210 0.015 0.130 0.018 0.060 0.010 0.750 0.310 0.250 0.100 0.300 0.345 0.125 14 PDIP16 0.210 0.015 0.130 0.018 0.060 0.010 0.750 0.310 0.250 0.100 0.300 0.345 0.125 16 PDIP18 0.210 0.015 0.130 0.018 0.060 0.010 0.890 0.310 0.250 0.100 0.300 0.345 0.125 18 PDIP20 0.210 0.015 0.130 0.018 0.060 0.010 1.020 0.310 0.250 0.100 0.300 0.345 0.125 20 TOLERANCE MAX MIN 0.005 0.002 +0.010/-0.015 +0.004/-0.002 0.010 +0.015/-0.010 0.005 Basic Basic 0.025 0.010 Reference Rev. B 2/99 2 1 NOTES
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 8

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