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Features
* * * * * * * * * * * * * * * * *
Single-chip 3.5GHz WiMAX Transceiver Fully Differential Design Low-IF/Zero-IF Transceiver Architecture; Requires No External Filters Self Calibration Mode for RX / TX Filters Support Channel Bandwidths of 3.5, 5.0, 7.0, 8.75MHz, and 10MHz Modulation up to 64QAM Ultra-fast Fractional-N Synthesizer Sensitivity < -74 dBm at 64-QAM, CR=3/4, 7MHz BW Phase Noise Synthesizer: 0.8 (-37dBc) Low Supply Voltage: 3.0 V TX Output PRF: 0 dBm, -34 dB EVM RX/TX Operating Current: 270/315mA Typical Low Power Off Current: < 20A Typical 56-lead QFN Package Low External Component Count Integrated Self IQ Calibration (no external components or control) HFDD Support
3.5GHz WiMAX Transceiver AT86RF535B
Applications
* 3.5 GHz Band Wireless Communication Devices * IEEE(R) 802.16-2004 Radios * Supports OFDM up to 64QAM
Preliminary
Description
Atmel's AT86RF535B is a fully integrated, low cost RF 3.5GHz Low-IF/Zero-IF conversion transceiver for WiMAX applications. It combines excellent RF performance, small size, and low current consumption. The AT86RF535 chip is fabricated on the advanced SiGe BiCMOS process AT46000. The transceiver combines LNA, PA driver, RX/TX mixer, RX/TX filters, VCO, Synthesizer, RX Gain control, and TX Power control, all fully digitally controlled. Only a minimum number of external components are required.
5190A-WiMAX-4/07
Figure 1.
AT86RF535B Block Diagram
TX Power Control
RX Gain Control
LNA
I Q
Synthesizer
Driver
I Q
Config Register
CLK
2
AT86RF535B [Preliminary]
5190A-WiMAX-4/07
AT86RF535B [Preliminary]
Quick Reference Data
Table 1.
Symbol FRF DFRS VDD IDDRX IDDTX IDDSYN IDDSTB SENS PRF PN TAMB Note:
Quick Reference Data
Parameter Input Center Frequency Frequency Resolution Supply Voltage Supply Current Supply Current Supply Current Supply Current Sensitivity QPSK Sensitivity 64QAM TX Output Power Integrated Phase Noise of Synthesizer Operating Ambient Temperature Conditions Min 3.4 3.0 Typ Max 3.8 19.6 3.6 Unit GHz Hz V mA mA mA mA -88 -70 dBm dBm deg rms +70 C
Applied to VDD pins Receive mode Transmit mode, -5dBm, incl. Balun Synthesizer Mode Stand By Mode, CLK driver activated Clock Load 20pF BW=3.5MHz, CR=1/2, S/N=9.4dB BW=7MHz, CR=3/4, S/N=24.4dB FRF= 3.5 GHz, 15dB back off for 64QAM, EVM=-34dB, incl. Balun Integrated over Frequency Range 50kHz ... 1MHz
3.3 270 315 135 2.5 -92 -74 0 0.8
-30
27
All voltages are referred to GND. VDD=3.0V TAMB=27C, unless otherwise noted.
Electrical Characteristics
Table 2.
Symbol FRF ZIN SENS PIN,MAX NFSSB GRX,STEP GRX,RANGE tRX/TX Symbol ACR1 ACR2 ROUT COUT VOMAX
Receiver Characteristics (Note 1)
Parameter Input Center Frequency Differential Impedance at LNA Input Sensitivity QPSK 1/2 Sensitivity 64QAM 3/4 Maximum Input Power Noise Figure Single Side Band RX Chain: Gain Steps RX Chain: Gain Range RX to TX Switching Time Conditions System 3.4 Includes a matching inductor and two series capacitors BW=3.5MHz, S/N=9.4dB BW=7MHz, S/N=24.4dB BW=7MHz, EVM=24.4dB high gain mode, includes balun w/o Frontend loss 100 -90 -69 -20 5 0.76 95.5 5 50 Max -11 -4 -30 -23 6 3.8 GHz diff. dBm dBm dB dB dB s Unit dB dB M pF V Min Typ Max Unit
TDD Mode HFDD Mode Parameter Conditions Min System 16QAM 3/4 Adjacent Ch. Rejection 64QAM 3/4 Nonadjacent Ch. 16QAM 3/4 Rejection 64QAM 3/4 Baseband filters, DC cancellation, RSSI, IQ outputs Output load resistance Pin to GND 1 Output load capacitance Pin to GND Maximum Output Voltage Differential 1
Typ
20
50
3
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VOUT GB,OFFSTEP GB,RANGE
Nominal I or Q output Voltage I, Q output buffer: Gain Offset Steps I, Q output buffer: Gain Range
Differential at the load specified Output buffer gain offset = 0dB Backoff -15dB relative to I or Q
0.141 0.76 -9 +2.25
Vrms dB dB
BW3dB
3-dB Bandwidth of Filter
IMRR FIF CMD
Image Rejection Ratio Low-IF Frequency Common Mode IQ Voltage
Low-IF Center Frequency: 1.875 MHz 2.7 MHz 3.75 MHz 5.0 MHz Note2 Note 2 Note 2 1.2
3.5
5.0 7.0 8.75 -42 -36 MHz
dB MHz
2.0 4.0
1.25 1.35
V DC
Table 3.
Symbol FRF ZOUT POUT tTX/RX GPA,RANGE GLSB,STEP
Transmitter Characteristics (Note 1)
Parameter Output Center Frequency Differential Impedance at Driver Output TX Output Power TX to RX Switching Time TX Chain Gain Control Range TX Chain Gain Control LSB Step Size Low-IF Center Frequency: 1.875 MHz 2.7 MHz 3.75 MHz 5.0 MHz Note2 Referred to sub carrier level of 64QAM modulated signals Note 2, 3 Referred to sub carrier level of 64QAM modulated signals Note 2, 3 64QAM 3/4, 0dBm Output Power Differential Peak, Differential Conditions System 3.4 100 For 64QAM modulated signals TDD Mode HFDD Mode 50 0 5 50 71.9 0.76 3.8 GHz diff dBm s dB dB Min Typ Max Unit
3.5
5.0 7.0 8.75 MHz
BW3dB
3-dB Bandwidth of Filter
LCarr
Carrier Leakage
-20
-12
dBc
IMRR EVM ZIN VIN VIN,DC Notes:
Image Rejection Ratio Error Vector Magnitude IQ Input Impedance IQ Input Voltage DC Input Voltage
-49
-45 -34
dBr dB k diff Vp,diff V
10 1 1.25
1. VDD=3.0V, TAMB =27C, FRF=3.55 GHz, specific application circuit TBD, unless otherwise noted. 2. Internally adjusted by build-in self-calibration. 3. ETSI Mask Compliant
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AT86RF535B [Preliminary]
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AT86RF535B [Preliminary]
Functional Description
The AT86RF535B is based on the IEEE 802.16-2004 standard. This product will provide transmit, receive, and frequency synthesis functions using the OFDM modulation schemes, as defined in the above specifications. The AT86RF535B consists of a frequency-agile RF transceiver intended for use in 3.5-GHz licensed bands at data rates up to 26Mbps. Configuration and control registers and a bi-directional data communications interface are available to communicate with existing baseband devices from different vendors. The AT86RF535B addresses the requirements of base station (BS) as well as subscriber stations (SS) equipment. The device will operate down to 3.0V. The AT86RF535 is fabricated in Atmel's AT46000 advanced SiGe BiCMOS process technology and is assembled in a 8mm x 8mm 56-lead QFN package.
RX Path
The differential low noise amplifier (DLNA) makes use of a differential bipolar stage with resistive emitter linearization. For digital gain control operation the DLNA supports the four gain modes 0, 6, 12, and 18dB. The linearity improves as the gain is reduced. The differential inphase quadrature phase mixer (IQMIX) utilizes a differential bipolar stage with emitter degeneration for the best linearity performance. A complex driving LO source is chosen for optimal LO leakage cancellation. The IQMIX has 4, 10, 16, and 22dB of switchable gain. The receive poly phase filter (RXPPF) is designed as a frequency shifted leapfrog structure. The filter provides three different bandwidths at three different center frequencies. The bandwidth of this filter is tuned by a built-in self-test (BIST). The PPF filter cap values are automatically adjusted upon power-up. The cap tuning can be recalled via SPI. Image rejection is also calibrated upon request via SPI. There are also three digitally controlled gain amplifiers (DGA1-3) available to provide the necessary amplification for the receive signal. Each stage supports the four gain modes 0, 6, 12, and 18dB, respectively. An additional fine gain stage DGB enables gain tuning of approximately 6dB in 0.76 dB steps. An output buffer with gain offset matches the voltage swing of the radio to the respective Baseband input stage. The gain control is complete digital and affects LNA, MIX, and the three DGAs by using the same granularity for each stage. The BB/MAC provides the gain vector at a separated serial interface. Fast TX/RX switching is possible via TX/RX switch input pins controlled by BB/MAC. The low-IF conversion receiver does not have to amplify DC signals, but the gain setting process produces different offsets in gain stages. An offset correction takes place after each gain step in the receiver to prevent signal saturation. Every stage has an individual offset correction circuit to maintain the correct overall dynamic range. The DC feedback (DCFB) works as an output offset compensation network, which depends on actual gain setting. The internal gain control operation is optimized for fixed target amplitude. To adapt to different application requirements, the IQ Output Buffer DGB has a programmable gain offset from - 1.5dB to 6dB in increments of 0.76dB. This allows the nominal output voltage to be set between 180mVp and 650mVp. The gain is controllable via the register setting. The IQOB is able to drive 5
5190A-WiMAX-4/07
a capacitive load on all four-output ports (RXI1, RXI2, RXQ1, RXQ2). The CMD pin is available to provide the common mode voltage of the Digital Output Buffer (DGB).
TX Path
The transmit low pass (TXLP) filter is band limited to meet the emission regulation for OFDM signals. The data signals to the four input ports (TXI1, TXI2, TXQ1, TXQ2) driving the TXLP should be digital but with defined levels. The complex filtered BB signal is up converted with IQ low-IF up converter (IQUC). A complex driving LO source is used to minimize LO leakage. The output currents of the two mixer stages are added together. The resulting signal drives the power amplifier control block (PAC). PAC is a Gilbert cell based current domain amplifier with the gain controlled by DC voltage across the mixer core. In that way linear to logarithmic (dB) gain control is achieved. The BB/MAC provides the gain setting vector at a separated serial interface.
Synthesizer
The voltage controlled oscillator (VCO) operates at two times the local oscillator (LO) frequency. The VCO output feeds a specialized divide-by-two module. The divider provides the required times one LO frequency with both in-phase and quadrature components for use in the IQ Mixer (IQMIX) and the IQ upconverter (IQUC). The use of the divider at two times the LO also reduces load pull on the LO frequency each time the integrated power amplifier (PA) is enabled. The VCO core is a differential double-grounded bipolar stage with the load for the VCO tank circuit made up of inductive and capacitive components in parallel. No external tuning devices are required. A fully differential inductor is contained on-chip. The capacitive portion of the frequency determining circuitry is made up of a binary weighted capacitor array and an analog voltage controlled varactor. The radio makes use of a hybrid phase lock loop (PLL) architecture. The coarse tuning is accomplished with the combination of Digital PLL/Binary capacitance array and the fine tuning is accomplished using the more conventional analog portion of the PLL. This use of coarse and fine tuning together reduces the analog VCO gain requirement. The reduction of tuning tolerance issues and noise are a direct effect of this type of PLL. Additionally, the characteristic impedance of the loop filter can be increased to reduce the charge pump current which helps in the integration of the active loop filter on-chip. This PLL also contains both integral and proportional charge pumps whose currents may be changed via register settings. This allows the loop parameters to be optimized for tuning speed and noise reduction. The fractional-N synthesizer in this radio utilizes a unique phase interpolation divider (PID) rather than the more conventional modulus divider architecture. The PID allows for very good frequency resolution and fast tuning speed. It also has the speed and power advantages of an asynchronous divider and is fully programmable within a restricted frequency range. Because of the coarse digital tuning the analog tuning gain could be reduced so that the characteristic impedance of the loop filter increases and the charge pump current is reduced. This helps to integrated the whole active loop filter (APLL). Using of two (proportional and integral components) charge pumps and programming their currents permit changing of filter parameters.
6
AT86RF535B [Preliminary]
5190A-WiMAX-4/07
AT86RF535B [Preliminary]
The phase interpolation divider (PDIV) is an alternate divider architecture to a conventional modulus divider. It has the speed and power advantages of an asynchron divider and is programmable in a restricted range.
Integrated Calibration Support
Calibration of the transceiver imbalances to optimize transmit LO leakage, transmit and receive image rejection ratio (IMRR) will be performed in between RX/TX operation. It is totally independent from BB/MAC processor.
SPI Interface
Serial peripheral interface (SPI) controls the transceiver. This 4-wire bus contains the ports SDE, SCL, SDI and SDO. The SPI has an 8-bit organization. Each transmission starts with a command byte with the following structure: MSB CMD ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 LSB ADR0
The command bit CMD is set to "1" for WRITE operation and "0" for READ operation. The transmission is continued with the data bytes. The number of data bytes depends on the register. The MSB of each data byte is send first. For an 8 bit register: MSB DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 LSB DATA0
For a 16 bit register: MSB DATA15 DATA7 DATA14 DATA6 DATA13 DATA5 DATA12 DATA4 DATA11 DATA3 DATA10 DATA2 DATA9 DATA1 LSB DATA8 DATA0
7
5190A-WiMAX-4/07
Figure 2.
SDE
SPI transmission for multiple bytes
SCL
SDI
X
CMD
ADR 6 ADR 5
ADR 4
ADR 3
ADR 2
ADR 1
ADR0
IN MSB OUT MSB
IN LSB OUT LSB
SDO
X
CMD
ADR 6
ADR 5
ADR 4
ADR 3
ADR 2
ADR 1
ADR 0
Pin Description and Package Drawing
Table 4.
Pin FSW VSSDPLL VDDDPLL VDDBBIF PTX
Pin Description
Pin No. 1 2 3 4 5 Description PLL Frequency Switch for HFDD Mode Digital CMOS input levels Ground Supply of Digital PLL Modules Voltage Supply of Digital PLL Modules Supply Voltage of Digital Base Band Interface Pads Power Switch Transmit Path High active, digital CMOS input levels RF Receive Input 1 Low noise amplifier input. The 50? matching is in part by the bond/package inductance and an external component (tbd). RF Receive Input 2 Complementary signal to RFRX1 Ground Supply of Radio Frequency Receive Circuit Modules Voltage Supply of Radio Frequency Receive Circuit Modules Analog Test Bus Analog IO Analog output/input signal for testing purposes, connection configurable over SPI Voltage Supply of Radio Frequency Transmit Circuit Modules Voltage Supply of Radio Frequency Transmit Circuit Module Voltage Supply of Radio Frequency Transmit Circuit Modules Voltage Supply of Radio Frequency Transmit Circuit Modules Voltage Supply of Power Amplifier Driving Module Voltage Supply of Power Amplifier Driving Module
RFRX1
6
RFRX2 VSSRFRX VDDRFRX ATB VDDRFTX1 VDDRFTX1 VDDRFTX2 VDDRFTX2 VDDPA VDDPA
7 8 9 10 11 12 13 14 15 16
8
AT86RF535B [Preliminary]
5190A-WiMAX-4/07
AT86RF535B [Preliminary]
Table 4.
Pin RFTX1
Pin Description (Continued)
Pin No. 17 Description RF Transmit Output 1 P1dB up to +15dBm @ 50? differential 3.5GHz. The 50? matching is in part by the bond/package inductance and an external component (tbd). RF Transmit Output 2 Complementary signal to RFTX1 Voltage Supply of Power Amplifier Driving Module Voltage Supply of Power Amplifier Driving Module Power Switch of Receive Path High active, digital CMOS input levels Digital Test Bus Input/Output Digital DTB input/output signal for testing purposes, connection and direction is configurable over SPI. Ground Supply SPI Interface Pads and of Digital Circuit Modules Voltage Supply of Digital Circuit Modules Voltage Supply of Digital Base Band Interface Pads SPI Enable Digital Input The rising edge of SCL and a low SDE indicate the start of a data transmission to the SPI slave SPI Clock Digital Input At every rising edge the SDI data is latched into the internal SPI register. SDO data change also on the rising edge. SPI Data Digital Input Serial SPI data input stream is started with SDE and contain first an address byte. Read in is MSB first. The MSB of the address byte is the R/W control bit. After the address byte there follows a number of data bytes. The actual number of data bytes depends on the address. SPI Data Digital Output Power On Reset Low active, open drain output with internal 10k? pull up resistor Base Band Transmit Input I Negative Complementary signal to BBTXIP Base Band Transmit Input I Positive Base band transmit input signal In Phase Base Band Transmit Input Q Positive Complementary signal to BBTXQN Base Band Transmit Input Q Negative Base band transmit input signal Quad Phase Voltage Supply of BB TX circuit modules Common Mode Voltage Bias Output RX Elements DC output voltage 1.0V, only active if PRX=High
RFTX2 VDDPA VDDPA PRX
18 19 20 21
DTB VSSDIG VDDDIG VDDBBIF NSDE
22 23 24 25 26
SCL
27
SDI
28
SDO NRES BBTXIN BBTXIP BBTXQP BBTXQN VDDBBTX VCMD
29 30 31 32 33 34 35 36
9
5190A-WiMAX-4/07
Table 4.
Pin
Pin Description (Continued)
Pin No. Description Base Band Receive Output I Negative In Phase output negative. The base band-processed signal is level voltage programmable to adapt to different base band ADCs. The capacitive load should be less than 10pF asymmetric Base Band Receive Output I Positive Complementary signal to BBRXIN Base Band Receive Output Q Positive Quad Phase output positive. The base band-processed signal is level voltage programmable to adapt to different base band ADCs. The capacitive load should be less than 10pF asymmetric. Base Band Receive Output Q Negative Complementary signal to BBRXQP Voltage Supply of BB Receive circuit modules Voltage Supply of BB Receive circuit modules Ground Supply of CMOS Clock Output Driver 40MHz CMOS Clock Digital Output Driver Ground Supply of CMOS Clock Output Driver Ground Supply of Crystal Clock Input Buffer Crystal Clock Input Buffer Voltage Supply of Crystal Clock Input Buffer Voltage Supply of Phase Frequency Detector and Charge Pump Modules Ground Supply of Phase Frequency Detector and Charge Pump Modules
BBRXIN
37
BBRXIP
38
BBRXQP
39
BBRXQN VSSBBRX VDDBBRX VDDCLK CLK VSSCLK VSSXCL XCL VDDXCL VDDCHP VSSCHP
40 41 42 43 44 45 46 47 48 49 50 51
VDDAPLL VSSAPLL CVI VSSVCO VDDVCO Note:
52 53 54 55 56
Voltage Supply of PLL Analog Divider Modules Ground Supply of PLL Analog Divider Modules VCO Control Voltage IO (Testpin) Ground Supply of Synthesizer modules VCO and APLF Voltage Supply of Synthesizer modules VCO and APLF
Additional ground supplies are generated by down bonds to exposed paddle
10
AT86RF535B [Preliminary]
5190A-WiMAX-4/07
AT86RF535B [Preliminary]
Figure 3. Pin Information
VDDAPLL
VSSAPLL
VDDVCO
VDDCHP
VSSVCO
VSSCHP
VDDXCL
PIN56
PIN55
PIN54
PIN53
PIN52
PIN51
PIN50
PIN48
PIN47
PIN49
PIN46
PIN45
PIN44
FSW VSSDPLL VDDDPLL VDDBBIF PTX RFRX1 RFRX2 VSSRFRX VDDRFRX ATB VDDRFTX1 VDDRFTX1 VDDRFTX2 VDDRFTX2
PIN43
VDDCLK
VSSXCL
VSSCLK
CLK
XCL
CVI
PIN1 PIN2
AT86RF535B
PIN42 PIN41 PIN40 PIN39 PIN38 PIN37
VDDBBRX VSSBBRX BBRXQN BBRXQP BBRXIP BBRXIN VCMD VDDBBTX BBTXQN BBTXQP BBTXIP BBTXIN NRES SDO
PIN3 PIN4 PIN5 PIN6 PIN7 PIN8 PIN9 PIN10 PIN11 PIN12 PIN13 PIN14
PIN15 PIN16 PIN17 PIN18 PIN19 PIN20 PIN21 PIN22 PIN23 PIN24 PIN25 PIN26 PIN27
QFN56
PIN36 PIN35 PIN34 PIN33 PIN32 PIN31 PIN30 PIN29
PIN28
RFTX1
RFTX2
VDDPA
VDDPA
VDDPA
VDDPA
PRX
VSSDIG DTB
VDDDIG
VDDBBIF
NSDE
SCL
SDI
11
5190A-WiMAX-4/07
Revision History
Doc. Rev. 5190A
Date 4/2007
Comments Initial document release.
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AT86RF535B [Preliminary]
5190A-WiMAX-4/07
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5190A-WiMAX-4/07

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