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74LCXH16374 Low Voltage 16-Bit D-Type Flip-Flop with Bushold
February 2001 Revised June 2005
74LCXH16374 Low Voltage 16-Bit D-Type Flip-Flop with Bushold
General Description
The LCXH16374 contains sixteen non-inverting D-type flipflops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock (CP) and Output Enable (OE) are common to each byte and can be shorted together for full 16-bit operation. The LCXH16374 is designed for low voltage (2.5V or 3.3V) VCC applications. The LCXH16374 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. The LCXH16374 data inputs include active bushold circuitry, eliminating the need for external pull-up resistors to hold unused or floating data inputs at a valid logic level.
Features
s 5V tolerant control inputs and outputs s 2.3V-3.6V VCC specifications provided s 6.2 ns tPD max (VCC
3.3V), 20 PA ICC max
s Bushold on inputs eliminating the need for external pull-up/pull-down resistors s Power down high impedance outputs s r24 mA output drive (VCC
3.0V)
s Implements patented noise/EMI reduction circuitry s Latch-up performance exceeds 500 mA s ESD performance:
Human body model ! 2000V Machine model ! 200V
s Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
Ordering Code:
Order Number 74LCXH16374G (Note 1)(Note 3) 74LCXH16374MEA (Note 2) 74LCXH16374MTD (Note 2) Package Number BGA54A MS48A MTD48 Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 1: Ordering code "G" indicates Trays. Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
GTO is a trademark of Fairchild Semiconductor Corporation.
(c) 2005 Fairchild Semiconductor Corporation
DS500441
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74LCXH16374
Connection Diagrams
Pin Assignment for SSOP and TSSOP
Pin Descriptions
Pin Names OEn CPn I0-I15 O0-O15 NC Description Output Enable Input (Active LOW) Clock Pulse Input Bushold Inputs Outputs No Connect
FBGA Pin Assignments
1 A B C D E F G H J O0 O2 O4 O6 O8 O10 O12 O14 O15 2 NC O1 O3 O5 O7 O9 O11 O13 NC 3 OE1 NC VCC GND GND GND VCC NC OE2 4 CP1 NC VCC GND GND GND VCC NC CP2 5 NC I1 I3 I5 I7 I9 I11 I13 NC 6 I0 I2 I4 I6 I8 I10 I12 I14 I15
Truth Tables
Inputs Pin Assignment for FBGA CP1 Outputs I0-I7 H L X X O0-O7 H L O0 Z Outputs I8-I15 H L X X O8-O15 H L O0 Z OE1 L L L H Inputs CP2

L X

L X
OE2 L L L H
(Top Thru View)
H L X Z O0
HIGH Voltage Level LOW Voltage Level Immaterial High Impedance Previous O0 before HIGH-to-LOW of CP
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74LCXH16374
Functional Description
The LCXH16374 consists of sixteen edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Each byte has a buffered clock and buffered Output Enable common to all flip-flops within that byte. The description which follows applies to each byte. Each flip-flop will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CPn) transition. With the Output Enable (OEn) LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the high impedance state. Operation of the OEn input does not affect the state of the flip-flops.
Logic Diagrams
Byte 1 (0:7)
Byte 2 (8:15)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74LCXH16374
Absolute Maximum Ratings(Note 3)
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Source/Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature I0 - I15 OE1, CPn Parameter Value Conditions Units V V 3-STATE Output in HIGH or LOW State (Note 4) VI GND VO GND VO ! VCC V mA mA mA mA mA
0.5 to 7.0 0.5 to VCC 0.5 0.5V to 7.0V 0.5 to 7.0 0.5 to VCC 0.5 50 50 50 r50 r100 r100 65 to 150
qC
Recommended Operating Conditions (Note 5)
Symbol VCC VI VO IOH/IOL Supply Voltage Input Voltage Output Voltage Output Current HIGH or LOW State 3-STATE VCC VCC VCC TA Free-Air Operating Temperature Input Edge Rate, VIN 0.8V-2.0V, VCC 3.0V 3.0V 3.6V 2.7V 3.0V 2.3V 2.7V Parameter Operating Data Retention Min 2.0 1.5 0 0 0 Max 3.6 3.6 VCC VCC 5.5 Units V V V
r24 r12 r8 40
0 85 10
mA
qC
ns/V
't/'V
Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 4: IO Absolute Maximum Rating must be observed. Note 5: Floating or unused control inputs must be HIGH or LOW.
DC Electrical Characteristics
Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage IOH IOH IOH IOH IOH VOL LOW Level Output Voltage IOL IOL IOL IOL IOL II Input Leakage Current Data Control VI Conditions VCC (V) 2.3 2.7 2.7 3.6 2.3 2.7 2.7 3.6 TA
40qC to 85qC
Max
Units
Min 1.7 2.0
V 0.7 0.8 V
100 PA 8 mA 12 mA 18 mA 24 mA
100 PA 8 mA 12 mA 16 mA 24 mA VCC or GND
2.3 3.6 2.3 2.7 3.0 3.0 2.3 3.6 2.3 2.7 3.0 3.0 2.3 3.6 2.3 3.6
VCC 0.2 1.8 2.2 2.4 2.2 0.2 0.6 0.4 0.4 0.55 V V
r5.0 r5.0
0V d VI d 5.5
PA
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74LCXH16374
DC Electrical Characteristics
Symbol II(HOLD) Parameter Bushold Input Minimum Drive Hold Current
(Continued)
VCC (V) VIN VIN VIN VIN 0.7V 1.7V 0.8V 2.0V 2.3 3.0 2.7 3.6 2.3 3.6 0 2.3 3.6 2.3 3.6 2.3 3.6 TA
Conditions
40qC to 85qC
Max 45
Units
Min
45
75
PA
75
300
II(OD)
Bushold Input Over-Drive Current to Change State
(Note 7) (Note 8) (Note 7) (Note 8)
300
450
PA
450 r5.0
10 20
IOZ IOFF ICC
3-STATE Output Leakage Power-Off Leakage Current Quiescent Supply Current Increase in ICC per Input
0 d VO d 5.5V VO VI VIH VCC VCC or GND VCC 0.6V
PA PA PA PA
3.6V d VO d 5.5V (Note 6)
r20
500
'ICC
Note 6: Outputs disabled or 3-STATE only. Note 7: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 8: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
AC Electrical Characteristics
TA Symbol Parameter VCC CL Min fMAX tPHL tPLH tPZL tPZH tPLZ tPHZ tS tH tW tOSHL tOSLH Setup Time Hold Time Pulse Width Output to Output Skew (Note 9) Output Disable Time Maximum Clock Frequency Propagation Delay CP to On Output Enable time 170 1.5 1.5 1.5 1.5 1.5 1.5 2.5 1.5 3.0 1.0 1.0 6.2 6.2 6.1 6.1 6.0 6.0 1.5 1.5 1.5 1.5 1.5 1.5 2.5 1.5 3.0 6.5 6.5 6.3 6.3 6.2 6.2 1.5 1.5 1.5 1.5 1.5 1.5 3.0 2.0 3.5 7.4 7.4 7.9 7.9 7.2 7.2 3.3V r 0.3V 50 pF Max
40q to 85qC, RL
VCC CL Min 2.7V 50 pF Max
500: VCC CL Min 2.5V r 0.2V 30 pF Max MHz ns ns ns ns ns ns ns Units
Note 9: Skew is defined as the absolute value of the differences between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
Dynamic Switching Characteristics
Symbol VOLP VOLV Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL CL CL CL CL 50 pF, VIH 30 pF, VIH 50 pF, VIH 30 pF, VIH Conditions 3.3V, VIL 2.5V, VIL 3.3V, VIL 2.5V, VIL 0V 0V 0V 0V VCC (V) 3.3 2.5 3.3 2.5 TA 25qC Units V V Typical 0.8 0.6
0.8
0.6
Capacitance
Symbol CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance Parameter VCC VCC VCC Open, VI 3.3V, VI 3.3V, VI Conditions 0V or VCC 0V or VCC 0V or VCC, f 10 MHz Typical 7 8 20 Units pF pF pF
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74LCXH16374
AC LOADING and WAVEFORMS Generic for LCX Family
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) Test tPLH, tPHL tPZL, tPLZ tPZH, tPHZ Switch Open 6V at VCC 3.3 r 0.3V, and 2.7V VCC x 2 at VCC 2.5 r 0.2V GND
Waveform for Inverting and Non-Inverting Functions
3-STATE Output High Enable and Disable Times for Logic
Propagation Delay. Pulse Width and trec Waveforms
Setup Time, Hold Time and Recovery Time for Logic
3-STATE Output Low Enable and Disable Times for Logic FIGURE 2. Waveforms (Input Characteristics; f =1MHz, tr = tf = 3ns) Symbol Vmi Vmo Vx Vy VCC 3.3V r 0.3V 1.5V 1.5V VOL 0.3V VOH 0.3V 2.7V 1.5V 1.5V VOL 0.3V VOH 0.3V
trise and tfall
2.5V r 0.2V VCC/2 VCC/2 VOL 0.15V VOH 0.15V
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74LCXH16374
Schematic Diagram Generic for LCXH Family (with Bushold)
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74LCXH16374
Physical Dimensions inches (millimeters) unless otherwise noted
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A
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74LCXH16374
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A
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74LCXH16374 Low Voltage 16-Bit D-Type Flip-Flop with Bushold
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 10 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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