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HT82A851R USB Audio MCU
Features
* Operating voltage: fSYS = 6M/12MHz: 3.3V~5.5V * 16 bidirectional I/O lines (max.) * Two 16-bit programmable timer/event counters and * Two hardware implemented Isochronous transfers * Total FIFO size: 464 bytes
(8, 8, 384, 32, 32 for EP0~EP4)
* Programmable frequency divider (PFD) * Integrated SPI hardware circuit * Play/Record Interrupt * HALT and wake-up features reduce power
overflow interrupts
* 409615 program memory ROM * 3848 data memory RAM (Bank0,1) * USB 2.0 full speed compatible * USB spec V1.1 full speed operation and USB audio
consumption
* Watchdog Timer * 16-level subroutine nesting * Bit manipulation instruction * 15-bit table read instruction * 63 powerful instructions * All instructions executed within one or two machine
device class spec V1.0
* Built-in digital PGA (Programmable Gain Amplifier) * 48kHz/8kHz sampling rate for audio playback
controlled by software option
* 8kHz audio recording sampling rate * Supports audio playback digital volume control * 5 endpoints supported (endpoint 0 included) * Supports 1 Control, 2 Interrupt, 2 Isochronous
cycles
* Low voltage reset function (3.0V0.3V) * 24-pin SSOP package
transfer
General Description
The HT82A851R is an 8-bit high performance RISC-like microcontroller designed for wireless USB Phone product applications. The HT82A851R combines a SPI, USB transceiver, SIE (Serial Interface Engine), audio class processing unit, FIFO and an 8-bit MCU into a single chip. The play frequency in the HT82A851R operates at a sampling rate of 48/8kHz. HT82A851R has a digital programmable gain amplifier. The gain range is from -32dB to +6dB. For the Isochronous input, the digital gain range is from 0dB to 19.5dB.
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Block Diagram
STACK0 STACK1 STACK2 STAC K14 P ro g ra m ROM P ro g ra m C o u n te r STAC K15 IN T C TM R1 M U X In s tr u c tio n R e g is te r TM R1C MP M U X DATA M e m o ry W DTS W D T P r e s c a le r In s tr u c tio n D ecoder ALU T im in g G e n e ra to r S h ifte r PCC PC OSCO USBDP USBDN V33O OSCI ACC F IF O D ig ita l PGA S e r ia l In te rfa c e PFD PORT C PC3 M U X MUX PAC STATUS PA PORT A PA0~PA7 W DT M U X fS /4 BP In te rru p t C ir c u it TM R0C M U X TM R0 fS
YS
/4 P C 1 /T M R 0
YS
P C 2 /T M R 1
E N /D IS fS
YS
/4
W DT OSC
PC 4~PC 7 (S D O , S D I, S C S , S C K ) P C 0 /B Z
U S B 1 .1 X C V R
U S B 1 .1 F u ll S p e e d E n g in e
D ig ita l V o lu m e C o n tro l
3 .3 V R e g u la to r
Pin Assignment
PA3 PA2 PA1 PA0 P C 7 /S C K P C 6 /S C S P C 5 /S D I P C 4 /S D O PC3 P C 2 /T M R 1 P C 1 /T M R 0 P C 0 /B Z 9 10 11 12 8 7 6 5 4 3 2 1 24 23 22 21 20 19 18 17 16 15 14 13 PA4 PA5 PA6 PA7 DVSS1 V33O USBDP USBDN DVDD1 RESET OSCO OSCI
H T82A 851R 2 4 S S O P -A
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Pin Description
Pin Name I/O Description Bidirectional 8-bit input/output port. Each bit can be configured as a wake-up input by a configuration option. Software instructions determine if the pin is a CMOS output or a Schmitt trigger input. Pull-high resistor can be connected to the pins via configuration options - nibble option. Can be software optioned as a bidirectional input/output or serial interface clock signal. Can be software optioned as a bidirectional input/output or serial interface slave select signal.
PA0~PA7
I/O
PC7/SCK PC6/SCS PC5/SDI PC4/SDO PC3 PC2/TMR1, PC1/TMR0 PC0/BZ OSCI OSCO RESET DVDD1 USBDN USBDP V33O DVSS1
I/O I/O
I/O or Can be software optioned as a bidirectional input/output or serial data input. O I/O or Can be software optioned as a bidirectional input/output or serial data output. O I/O Bidirectional I/O lines. Software instructions determine if the pin is a CMOS output or a Schmitt trigger input. Pull-high resistor can be connected to the pins via configuration options. Software instructions determine if the pin is a CMOS output or a Schmitt trigger input. Pull-high resistor can be connected to the pins via configuration options.TMR0, TMR1 are pin shared with PC1, PC2 respectively.
I/O
I/O or Can be software optioned as a bidirectional input/output or as a PFD output. O I O I 3/4 I/O I/O O 3/4 OSCI, OSCO are connected to an 6MHz or 12MHz crystal/resonator (determined by software instructions) for the internal system clock Schmitt trigger reset input, active low Positive digital power supply USBD- line. The USB function is controlled by a software control register USBD+ line. The USB function is controlled by a software control register 3.3V regulator output Negative digital power supply, ground
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V Input Voltage..............................VSS-0.3V to VDD+0.3V IOL Total ..............................................................150mA Total Power Dissipation .....................................500mW Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C IOH Total............................................................-100mA
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D.C. Characteristics
Symbol VDD IDD ISUS VIL1 VIH1 VIL2 VIH2 IOL IOH RPH VLVR VV33O Parameter Operating Voltage Operating Current Suspend Current Input Low Voltage for I/O Ports Input High Voltage for I/O Ports Input Low Voltage (RESET) Input High Voltage (RESET) I/O Port Sink Current I/O Port Source Current Pull-high Resistance Low Voltage Reset 3.3V Regulator Output Test Conditions VDD 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V IV33O=-5mA VOL=0.1VDD VOH=0.7VDD 3/4 3/4 Conditions 3/4 No load, fSYS=12MHz No load, system HALT, USB transceiver and 3.3V regulator on 3/4 3/4 3/4 3/4 Min. 3.3 3/4 3/4 0 0.7VDD 0 0.9VDD 3/4 3/4 30 2.7 3.0 Typ. 5.0 5 350 3/4 3/4 3/4 3/4 5 -5 40 3.0 3.3 Max. 5.5 3/4 3/4 0.3VDD VDD 0.4VDD VDD 3/4 3/4 80 3.3 3.6 Ta=25C Unit V mA mA V V V V mA mA kW V V
A.C. Characteristics
Symbol fSYS Parameter System Clock (Crystal OSC) Test Conditions VDD 5V 5V 3/4 3/4 3/4 Conditions 3/4 3/4 3/4 3/4 3/4 Min. 0.4 3/4 1 3/4 1 Typ. 3/4 100 3/4 1024 3/4 Max. 12 3/4 3/4 3/4 3/4
Ta=25C Unit MHz ms ms tSYS ms
tWDTOSC Watchdog Oscillator Period tRES tSST tINT RESET Input Pulse Width System Start-up Timer Period Interrupt Pulse Width
Note: tSYS=1/fSYS
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Functional Description
Execution Flow The microcontroller system clock is sourced from a crystal oscillator. The system clock is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to be effectively executed in a cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. Program Counter - PC The program counter, PC, controls the sequence in which the instructions stored in the program memory are executed. Its contents specify the full program memory range. After accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by one. The program counter then
S y s te m C lo c k T1 T2 T3 T4 T1 T2
points to the memory word containing the next instruction code. When executing a jump instruction, a conditional skip execution, loading to the PCL register, performing a subroutine call or returning from a subroutine, an initial reset, an internal interrupt, external interrupt or return from interrupts, the PC manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise the next instruction is executed. The lower byte of the program counter, PCL, is a readable and writeable register. Moving data into the PCL performs a short jump. The destination will be within the current program memory page. When a control transfer takes place, an additional dummy cycle is required.
T3 T4 T1 T2 T3 T4
O S C 2 ( R C o n ly ) PC PC PC+1 PC+2
F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )
Execution Flow
Mode Initial Reset Reserved Timer/Event Counter 0 Overflow Timer/Event Counter 1 Overflow Play Interrupt Serial Interface Interrupt Record Interrupt Skip Loading PCL Jump, Call Branch Return from Subroutine
Program Counter *11 0 0 0 0 0 0 0 *11 #11 S11 *10 0 0 0 0 0 0 0 *10 #10 S10 *9 0 0 0 0 0 0 0 *9 #9 S9 *8 0 0 0 0 0 0 0 *8 #8 S8 *7 0 0 0 0 0 0 0 @7 #7 S7 *6 0 0 0 0 0 0 0 @6 #6 S6 *5 0 0 0 0 0 0 0 @5 #5 S5 *4 0 0 0 0 1 1 1 @4 #4 S4 *3 0 0 1 1 0 0 1 @3 #3 S3 *2 0 1 0 1 0 1 0 @2 #2 S2 *1 0 0 0 0 0 0 0 @1 #1 S1 *0 0 0 0 0 0 0 0 @0 #0 S0
Program Counter+2
Program Counter Note: *11~*0: Program counter bits #11~#0: Instruction code bits Rev. 1.20 5 S11~S0: Stack register bits @7~@0: PCL bits June 15, 2007
HT82A851R
Program Memory - PROM The program memory is used to store the executable program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 409615 bits, addressed by the program counter and table pointer. Certain locations in the program memory are reserved for special usage: * Location 000H This area is reserved for program initialization. After a chip reset, the program always begins execution at location 000H.
* Location 004H
rupt is enabled and the stack is not full, the program begins execution at location 00CH.
* Location 010H
This area is reserved for the play interrupt service program. If play data is valid, and the interrupt is enabled and the stack is not full, the program begins execution at location 010H.
* Location 014H
This area is reserved for when 8 bits of data have been received or transmitted successfully from the serial interface. If the related interrupts are enabled, and the stack is not full, the program begins execution at location 014H.
* Location 018H
This area is reserved for the USB interrupt service program. If the USB interrupt is activated, the interrupt is enabled and the stack is not full, the program begins execution at location 004H.
* Location 008H
This area is reserved for the record interrupt service program. If the record frequency time out (8kHz), the interrupt is enabled and the stack is not full, the program begins execution at location 018H.
* Table location
This area is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results from a Timer/Event Counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008H.
* Location 00CH
This area is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt results from a Timer/Event Counter 1 overflow, and the inter000H 004H 008H 00CH 010H 014H 018H 01BH 020H D e v ic e In itia liz a tio n P r o g r a m U S B In te r r u p t S u b r o u tin e T im e r /E v e n t C o u n te r 0 In te r r u p t S u b r o u tin e T im e r /E v e n t C o u n te r 1 In te r r u p t S u b r o u tin e P la y In te r r u p t S u b r o u tin e S e r ia l In te r fa c e In te r r u p t S u b r o u tin e R e c o r d In te r r u p t S u b r o u tin e P ro g ra m M e m o ry
FFFH
L o o k - u p T a b le ( 2 5 6 w o r d s ) 1 5 b its N o te : n ra n g e s fro m 1 to F
Program Memory
Any location in the program memory can be used as a look-up table. There are three method to read the program memory data. The first method uses the TABRDC instruction to transfer the contents of the current page lower-order byte to the specified data memory, and the current page higher-order byte to the TBLH register. The second method uses the TABRDL instruction to transfer the contents of the last page lower-order byte to the specified data memory, and the last page higher-order byte to the TBLH register. The third method uses the TABRDC instruction together with the TBLP and TBHP pointers to transfer the contents of the lower order byte at the specified address to the specified data memory, and the higher order byte at the specified address to the TBLH register. Before accessing the table data, the address to be read must be placed in the table pointer registers, TBLP and TBHP. Note that if the configuration option TBHP is disabled, then the value in TBHP has no effect. Only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are transferred to the lower portion of TBLH, and the remaining 1-bit word is read as 0.The Table Higher-order byte register, TBLH, is read only. The TBLH register is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of TBLH in the main routine are likely to be changed by the table read instruction used in the ISR. Table Location
Instruction TABRDC [m] TABRDL [m]
*11 P11 1
*10 P10 1
*9 P9 1
*8 P8 1
*7 @7 @7
*6 @6 @6
*5 @5 @5
*4 @4 @4
*3 @3 @3
*2 @2 @2
*1 @1 @1
*0 @0 @0
Table Location Note: *11~*0: Table location bits P11~P8: Current program counter bits TBHP register bit3~bit0 when TBHP is enabled P11~P8: Current program counter bits when TBHP is disabled @7~@0: Table pointer bits
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In such cases errors can occur. Therefore, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read instruction has to be used in both the main routine and the ISR, the interrupt should be disabled prior to the table read instruction. It should not be re-enabled until TBLH has been backed up. All table related instructions require two cycles to complete the operation. These areas may function as normal program memory depending upon requirements. Stack Register - STACK This is a special part of the memory which is used to save the contents of the program counter only. The stack is organised into 16 levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the stack pointer, SP, which is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the program counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the stack pointer is decremented, using RET or RETI, the interrupt will be serviced. This feature prevents a stack overflow allowing the programmer to use the structure more easily. In a similar case, if the stack is full and a CALL is subsequently executed, a stack overflow will occur and the first entry will be lost. Only the most recent 16 return addresses are stored. Data Memory - RAM The data memory is divided into two functional groups. These are the special function registers and the general purpose data memory in Bank0 and Bank1: 3848 bits. Most are read/write, but some are read only. The special function registers are overlapped in all banks. Any unused space before 40H is reserved for future expanded usage and if read will return a value of 00H. The general purpose data memory, addressed from 40H to FFH, is used for data and control information under instruction commands. All data memory areas can handle arithmetic, logical, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by SET [m].i and CLR [m].i. They are also indirectly accessible through the memory pointer registers, MP0 or MP1.
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H PLAY_D ATAL_L PLAY_D ATAL_H PLAY_DATAR_L PLAY_DATAR_H RECO RD_DATA_L RECO RD_DATA_H G e n e ra l P u rp o s e D a ta R A M (1 9 2 B y te s ) (B a n k 0 /B a n k 1 ) MODE SB SB RECOR RECOR _CTRL CR DR D _ IN _ L D _ IN _ H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H IN T C 1 TBHP USC USR UCC AW R STALL S IE S M IS C S E T IO F IF O 0 F IF O 1 F IF O 2 F IF O 3 F IF O 4 D A C _ L IM IT _ L D A C _ L IM IT _ H DAC_W R PG A_CTRL PFDC PFDD S p e c ia l P u r p o s e D a ta M e m o ry USVC B a n k 0 S p e c ia l R e g is te r In d ir e c t A d d r e s s in g R e g is te r 0 MP0 In d ir e c t A d d r e s s in g R e g is te r 1 MP1 BP ACC PCL TBLP TBLH W DTS STATUS IN T C 0 TM R0H TM R0L TM R0C TM R1H TM R1L TM R1C PA PAC PB PBC PC PCC
:U nused R e a d a s "0 0 "
FFH
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Indirect Addressing Register Locations 00H and 02H are the indirect addressing registers, however they are not physically implemented. Any read/write operation to [00H] or [02H] will access the data memory pointed to by MP0 and MP1. Reading location 00H or 02H indirectly will return a result of 00H. Writing indirectly results in no operation. Data transfer between two indirect addressing registers is not supported. The memory pointer registers, MP0 and MP1, are 8-bit registers which are used to access the Data Memory in combination with indirect addressing registers. Bank Pointer The bank pointer is used to select the required Data Memory bank. If Data Memory bank 0 is to be selected, then a 0 should be loaded into the BP register. Data Memory locations before 40H in any bank are overlapped. Accumulator The accumulator is closely related to ALU operations. It is also mapped to location 05H of the data memory and can carry out immediate data operations. The data movement between two data memory locations must pass through the accumulator. Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions:
* Arithmetic operations - ADD, ADC, SUB, SBC, DAA * Logic operations - AND, OR, XOR, CPL * Rotation - RL, RR, RLC, RRC * Increment and Decrement - INC, DEC * Branch decision - SZ, SNZ, SIZ, SDZ ....
Status Register - STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). It also records the status information and controls the operation sequence. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results from those intended. The TO flag can be affected only by a system power-up, a WDT time-out or executing the CLR WDT or HALT instruction. The PDF flag can be affected only by executing the HALT or CLR WDT instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, upon entering the interrupt sequence or executing a subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status are important and if the subroutine can corrupt the status register, precautions must be taken to save it properly. Interrupt The device provides a USB interrupt, internal timer/event counter interrupts, play/record data valid interrupt and a serial interface interrupt. The Interrupt Control Register0 (INTC0;0BH) and the interrupt control register1 (INTC1;1EH) both contain the interrupt control bits that are used to set the enable/disable status and interrupt request flags. Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other Function
The ALU not only saves the results of a data operation but also changes the status register. Bit No. 0 Label C
C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared. OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PDF is cleared by a system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction. TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 Status (0AH) Register
1 2 3 4 5 6~7
AC Z OV PDF TO 3/4
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interrupt requests may occur during this interval but only the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit of the INTC0 or INTC1 may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. All these kinds of interrupts have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the program memory. Only the program counter is pushed onto the stack. If the contents of the register or status register (STATUS) are altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. The USB interrupts are triggered by the following USB events and the related interrupt request flag (USBF; bit 4 of the INTC0) will be set. * Accessing the corresponding USB FIFO from the PC
* The USB suspend signal from the PC * The USB resume signal from the PC * USB Reset signal
When the interrupt is enabled, the stack is not full and the USB interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (USBF) and EMI bits will be cleared to disable other interrupts. When the PC Host accesses the FIFO of the HT82A851R, the corresponding request bit of the USR is set, and a USB interrupt is triggered. So the user can easily determine which FIFO has been accessed. When the interrupt has been served, the corresponding bit should be cleared by firmware. When the HT82A851R receives a USB Suspend signal from the Host PC, the suspend line (bit0 of USC) of the HT82A851R is set and a USB interrupt is also triggered. Also when the HT82A851R receives a Resume signal from the Host PC, the resume line (bit3 of USC) of the HT82A851R is set and a USB interrupt is triggered. The internal Timer/Event Counter 0 interrupt is initialized by setting the Timer/Event Counter 0 interrupt request flag (bit 5 of INTC0), caused by a timer 0 overflow. When the interrupt is enabled, the stack is not full and the T0F bit is set, a subroutine call to location 08H will occur. The related interrupt request flag (T0F) will be reset and the EMI bit cleared to disable further interrupts.
Bit No. 0 1 2 3 4 5 6 7
Label EMI EUI ET0I ET1I USBF T0F T1F 3/4
Function Controls the master (global) interrupt (1=enable; 0=disable) Controls the USB interrupt (1=enable; 0=disable) Controls the Timer/Event Counter 0 interrupt (1=enable; 0=disable) Controls the Timer/Event Counter 1 interrupt (1=enable; 0=disable) USB interrupt request flag (1=active; 0=inactive) Internal Timer/Event Counter 0 request flag (1=active; 0=inactive) Internal Timer/Event Counter 1 request flag (1=active; 0=inactive) Unused bit, read as 0 INTC0 (0BH) Register
Bit No. 0 1 2 3, 7 4 5 6
Label EPLAYI ESII RECI 3/4 PLAYF SIF RECF Play interrupt (1=enable; 0=disable)
Function
Control Serial interface interrupt (1=enable; 0=disable) Record interrupt (1=enable; 0=disable) Unused bit, read as 0 Play interrupt request flag (1=active; 0=inactive) Serial interface interrupt request flag (1=active; 0=inactive) Record interrupt request flag (1=active; 0=inactive) INTC1 (1EH) Register
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The internal Timer/Event counter 1 interrupt is initialized by setting the Timer/Event Counter 1 interrupt request flag (bit 6 of INTC0), caused by a timer 1 overflow. When the interrupt is enabled, the stack is not full and T1F is set, a subroutine call to location 0CH will occur. The related interrupt request flag (T1F) will be reset and the EMI bit cleared to disable further interrupts. The play interrupt is initialized by setting the play interrupt request flag (bit 4 of INTC1), caused by a play data valid. When the interrupt is enabled, the stack is not full and the PLAYF is set, a subroutine call to location 10H will occur. The related interrupt request flag (PLAYF) will be reset and the EMI bit cleared to disable further interrupts. If PLAY_MODE (bit 3 of MODE_CTRL register) is set to 1, the play interrupt frequency will change to 8kHz, otherwise the interrupt frequency is 48kHz. The serial interface interrupt is indicated by the interrupt flag (SIF; bit 5 of INTC1), that is generated by the reception or transfer of a complete 8-bits of data between the HT82A851R and the external device. The serial interface interrupt is controlled by setting the Serial interface interrupt control bit (ESII; bit 1 of INTC1). After the interrupt is enabled (by setting SBEN; bit 4 of SBCR), and the stack is not full and the SIF is set, a subroutine call to location 14H occurs. The record interrupt is initialized by setting the record interrupt request flag (bit 6 of INTC1), caused by a record frequency time out (8kHz). When the interrupt is enabled, the stack is not full and RECF is set, a subroutine call to location 18H will occur. The related interrupt request flag (RECF) will be reset and the EMI bit cleared to disable further interrupts. During the execution of an interrupt subroutine, other interrupt acknowledge signals are held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (if the stack is not full). To return from the interrupt subroutine, RET or RETI may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not. Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests the following table shows the priority that is applied. These can be masked by resetting the EMI bit. Interrupt Source USB interrupt Timer/Event Counter 0 overflow Timer/Event Counter 1 overflow Play Interrupt Serial Interface Interrupt Record Interrupt Priority 1 2 3 4 5 6 Vector 04H 08H 0CH 10H 14H 18H It is recommended that a program does not use the CALL subroutine within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged once the CALL operates in the interrupt subroutine. Oscillator Configuration The microcontroller contains an integrated oscillator circuit.
OSCI
OSCO C r y s ta l O s c illa to r
System Oscillator This oscillator is designed for the system clock. The HALT mode stops the system oscillator and ignores any external signals to conserve power. A crystal across OSCI and OSCO is needed to provide the feedback and phase shift required for the oscillator. No other external components are required. If preferred, a resonator can also be connected between OSCI and OSCO for oscillation to occur, but two external capacitors connected between OSCI, OSCO and ground are required. The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if the system enters the power down mode, the system clock stops running, but the WDT oscillator still continues to run. The WDT oscillator can be disabled by a configuration option to conserve power. Watchdog Timer - WDT The WDT clock source is implemented by a dedicated RC oscillator (WDT oscillator) or the instruction clock (system clock/4). The timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The WDT can be disabled by a configuration option. However, if the WDT is disabled, all executions related to the WDT lead to no operation. When the WDT clock source is selected, it will be first divided by 256 (8-stage) to get the nominal time-out period. By invoking the WDT prescaler, longer time-out periods can be realized. Writing data to WS2, WS1, WS0 can give different time-out periods. The WDT OSC period is typically 65ms. This time-out period may vary with temperature, VDD and process variations. The WDT OSC always keeps running in any operation mode.
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Bit No. Label Function Watchdog Timer division ratio selection bits Bit 2,1,0 = 000, Division Ratio = 1:1 Bit 2,1,0 = 001, Division Ratio = 1:2 Bit 2,1,0 = 010, Division Ratio = 1:4 Bit 2,1,0 = 011, Division Ratio = 1:8 Bit 2,1,0 = 100, Division Ratio = 1:16 Bit 2,1,0 = 101, Division Ratio = 1:32 Bit 2,1,0 = 110, Division Ratio = 1:64 Bit 2,1,0 = 111, Division Ratio = 1:128 Unused bit, read as 0 WDTS (09H) Register
W DT OSC S y s te m C lo c k /4
M ask O p tio n S e le c t W D T P r e s c a le r 8 - b it C o u n te r 7 - b it C o u n te r
0 1 2
WS0 WS1 WS2
3~7
3/4
W S0~W S2
8 -to -1 M U X W D T T im e - o u t
Watchdog Timer If the instruction clock is selected as the WDT clock source, the WDT operates in the same manner except in the halt mode. In the HALT mode, the WDT stops counting and lose its protecting purpose. In this situation the logic can only be re-started by external logic. The high nibble of the WDTS is reserved for the DAC write mode. The WDT overflow under normal operation initializes a chip reset and sets the status bit TO. In the HALT mode, the overflow initializes a warm reset, and only the program counter and stack pointer are reset to zero. To clear the contents of the WDT, there are three methods to be adopted, i.e., an external reset (a low level to RESET), a software instruction, and a HALT instruction. There are two types of software instructions; CLR WDT and the other set CLR WDT1 and CLR WDT2. Of these two types of instruction, only one type of instruction can be active at a time depending on the configuration option CLR WDT times selection option. If the CLR WDT is selected (i.e., CLR WDT times equal one), any execution of the CLR WDT instruction clears the WDT. In the case that CLR WDT1 and CLR WDT2 are chosen (i.e., CLR WDT times equal two), these two instructions have to be executed to clear the WDT; otherwise, the WDT may reset the chip due to a time-out. Power Down Operation - HALT The Power-down mode is entered by the execution of a HALT instruction and results in the following:
* The system oscillator will be turned off but the WDT * The WDT and WDT prescaler will be cleared and will
start counting again if the WDT clock is sourced from the internal WDT oscillator.
* All of the I/O ports remain in their original condition. * The PDF flag is set and the TO flag is cleared.
The system can leave the Power-down mode by means of an external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset causes a device initialisation and the WDT overflow performs a warm reset. After the TO and PDF flags are examined, the cause for the device reset can be determined. The PDF flag is cleared by a system power-up or by executing the CLR WDT instruction and is set when executing the HALT instruction. The TO flag is set if the WDT time-out occurs, and causes a wake-up that only resets the program counter and SP; the others remain in their original status. A port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each pin in port A can be independently selected to wake-up the device using configuration options. After awakening from an I/O port stimulus, the program will resume execution at the next instruction. If the device is awakened from an interrupt, two sequence may occur. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt response takes place. If an interrupt request flag is set to 1 before entering the Power-down mode, the wake-up function of the related interrupt will be disabled. Once a wake-up event occurs, it takes 1024 tSYS (system clock periods) to resume normal operation, i.e., a dummy period is inserted. If the wake-up results from an
oscillator keeps running if the internal WDT oscillator is selected.
* The contents of the on-chip data memory and regis-
ters remain unchanged. Rev. 1.20 11
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interrupt acknowledge signal, the actual interrupt subroutine execution will be delayed by one or more cycles. If the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. To minimise power consumption, all the I/O pins should be carefully managed before entering the Power-down mode. Reset There are four ways in which a reset can occur:
V
* RES reset during normal operation * RES reset during HALT * WDT time-out reset during normal operation * USB reset
The functional unit chip reset status are shown below. Program Counter Interrupt WDT 000H Disable Clear. After master reset, WDT begins counting
Timer/event Counter Off Input/output Ports Stack Pointer
DD
Input mode Points to the top of the stack
100kW 10kW 0 .1 m F
0 .0 1 m F RESET
The WDT time-out during HALT is different from other chip reset conditions, since it can perform a warm re set that resets only the program counter and stack pointer, leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions. Most registers are reset to the initial condition when the reset conditions are met. By examining the PDF and TO flags, the program can distinguish between different chip resets. TO 0 u 0 1 1 PDF 0 u 1 u 1 RESET Conditions RESET reset during power-up RESET reset during normal operation RESET wake-up HALT WDT time-out during normal operation WDT wake-up HALT
Reset Circuit
VDD RES S S T T im e - o u t C h ip R eset tS
ST
Reset Timing Chart
HALT W DT
RESET W a rm R eset
Note: u stands for unchanged To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra delay of 1024 system clock pulses when the system resets (power-up, WDT time-out or RES reset) or the system awakes from the HALT state. When a system reset occurs, the SST delay is added during the reset period. Any wake-up from HALT will enable the SST delay.
OSCI SST 1 0 - b it R ip p le C o u n te r S y s te m R eset
C o ld R eset
Reset Configuration
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The registers status are summarized in the following table. Reset (Power On) xxxx xxxx xxxx xxxx 0000 0000 xxxx xxxx 000H xxxx xxxx -xxx xxxx 0000 0111 --00 xxxx -000 0000 xxxx xxxx xxxx xxxx 00-0 1000 xxxx xxxx xxxx xxxx 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 -000 0000 xxxx xxxx 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 xxxx x010 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 WDT RES Reset Time-out RES Reset (Normal (Normal (HALT) Operation) Operation) uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu 000H uuuu uuuu -uuu uuuu 0000 0111 --1u uuuu -000 0000 uuuu uuuu uuuu uuuu 00-0 1000 uuuu uuuu uuuu uuuu 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 -000 0000 uuuu uuuu uuxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu xxxx x010 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu 000H uuuu uuuu -uuu uuuu 0000 0111 --uu uuuu -000 0000 uuuu uuuu uuuu uuuu 00-0 1000 uuuu uuuu uuuu uuuu 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 -000 0000 uuuu uuuu 10xx 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 xxxx x010 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu 000H uuuu uuuu -uuu uuuu 0000 0111 --01 uuuu -000 0000 uuuu uuuu uuuu uuuu 00-0 1000 uuuu uuuu uuuu uuuu 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 -000 0000 uuuu uuuu 10xx 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 xxxx x010 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 WDT Time-Out (HALT)* uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 000H uuuu uuuu -uuu uuuu uuuu uuuu --11 uuuu -uuu uuuu uuuu uuuu uuuu uuuu uu-u uuuu uuuu uuuu uuuu uuuu uu-u u--uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu 10xx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu xxxx x010 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 USB Reset USB Reset (Normal) (HALT) uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 000H uuuu uuuu -uuu uuuu 0000 0111 --uu uuuu -000 0000 uuuu uuuu uuuu uuuu 00-0 1000 uuuu uuuu uuuu uuuu 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 -000 0000 uuuu uuuu 1000 0u00 00uu 0000 0u00 u000 0000 0000 0000 0000 0u00 u000 0000 0000 xxxx x010 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00uu uuuu uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu 000H uuuu uuuu -uuu uuuu 0000 0111 --01 uuuu -000 0000 uuuu uuuu uuuu uuuu 00-0 1000 uuuu uuuu uuuu uuuu 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 -000 0000 uuuu uuuu 1000 0u00 00uu 0000 0u00 u000 0000 0000 0000 0000 0u00 u000 0000 0000 xxxx x010 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00uu uuuu
Register
MP0 MP1 BP ACC Program Counter TBLP TBLH WDTS STATUS INTC0 TMR0H TMR0L TMR0C TMR1H TMR1L TMR1C PA PAC PC PCC USVC INTC1 TBHP USC USR UCC AWR STALL SIES MISC SETIO FIFO0 FIFO1 FIFO2 FIFO3 FIFO4 PGA_CTRL
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Reset (Power On) 0000 0000 0000 0000 0000 0000 0110 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 WDT RES Reset Time-out RES Reset (Normal (Normal (HALT) Operation) Operation) 0000 0000 0000 0000 0000 0000 0110 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0110 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0110 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 WDT Time-Out (HALT)* 0000 0000 0000 0000 0000 0uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu USB Reset USB Reset (Normal) (HALT) 0uuu 0000 0uuu 0000 0000 0uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0uuu 0000 0uuu 0000 0000 0uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
Register
PFDC PFDD MODE_CTRL SBCR SBDR RECORD_IN_L RECORD_IN_H PLAY_DATAL_L PLAY_DATAL_H PLAY_DATAR_L PLAY_DATAR_H
Note: * stands for warm reset u stands for unchanged x stands for unknown - stands for undefined Timer/Event Counter Two timer/event counters are implemented in the microcontroller. Each timer contains a 16-bit programmable count-up counter whose clock may be sourced from an external or internal clock source. The internal clock source comes from fSYS/4. The external clock input allows external events to be counted, time intervals or pulse widths to be measured, or to generate an accurate time base. There are three registers related to Timer/Event Counter 0, TMR0H, TMR0L and TMR0C, and another three related to Timer/Event Counter 1, TMR1H, TMR1L and TMR1C. When writing data to the TMR0L and TMR1L registers, note that the data will only be written into a lower-order byte buffer. The data will not be actually written into the TMR0L and TMR1L registers until a write operation to the TMR0H and TMR1H registers is implemented. Reading the TMR0L and TMR1L registers will read the contents of the lower-order byte buffer. The TMR0C and TMR1C registers are the Timer/Event Counter control registers, which define the operating mode, the count enable or disable and the active edge. The TM0 and TM1 bits define the operation mode. The event count mode is used to count external events, which means that the clock source is sourced from the external TMR0 or TMR1 pin. The timer mode functions as a normal timer with the clock source coming from the internal clock. Finally, the pulse width measurement mode can be used to count the high level or low level duration of an external signal on pins TMR0 or TMR1, whose counting is based on the internal clock source. In the event count or timer mode, the timer/event counter starts counting from the current contents in the timer/event counter and ends at FFFFH . Once an overflow occurs, the counter is reloaded from the timer/event counter preload register, and generates an interrupt request flag (T0F; bit 5 of INTC0, or T1F; bit 6 of INTC0). In the pulse width measurement mode with the values of the TON and TE bits equal to 1, after the TMR0 or TMR1 pin has received a transient from low to high, or high to low if the TE bit is 0, it will start counting until the TMR0 or TMR1 pin returns to its original level and resets the TON bit. The measured result remains in the timer/event counter even if the activated transient occurs again. Therefore, only 1-cycle measurement is made. Not until the TON bit is again set can the cycle measurement re-function. In this operational mode, the timer/event counter begins counting not according to the logic level but to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter register and issues an interrupt request, as in the other two modes, i.e., event and timer modes. To enable a count operation, the Timer ON bit (TON; bit 4 of TMR0C or TMR1C) should be set to 1. In the pulse width measurement mode, TON is automatically cleared after the measurement cycle is completed. But in the other two modes, the TON bit can only be reset by instructions. A Timer/Event Counter overflow is one of the wake-up sources. No matter what the operational mode is, writing a 0 to ET0I or ET1I disables the related interrupt service.
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Bit No. 0~2, 5 Label 3/4 Unused bit, read as 0 Defines the TMR active edge of the timer/event counter In Event counter mode (TM1, TM0)=(0, 1): 1=count on falling edge; 0=count on rising edge In Pulse width measurement mode (TM1, TM0)=(1, 1): 1=start counting on the rising edge, stop on the falling edge; 0=start counting on the falling edge, stop on the rising edge Enable/disable the timer counting (0=disable; 1=enable) Defines the operating mode 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMR0C (0EH), TMR1C (11H) Register Function
3
TE
4
TON
6 7
TM0 TM1
fS
Y S /4
f IN
T
D a ta B u s TM 1 TM 0 TE 1 6 B its T im e r /E v e n t C o u n te r P r e lo a d R e g is te r R e lo a d
T M R 0 /1
TM 1 TM 0 TON
P u ls e W id th M e a s u re m e n t M o d e C o n tro l
1 6 B its T im e r /E v e n t C o u n te r (T M R 0 /1 )
O v e r flo w to In te rru p t
Timer/Event Counter 0/1 If the timer/event counter is turned OFF, writing data to the timer/event counter preload register will also reload the data into the timer/event counter. But if the timer/event counter is turned on, data written to the timer/event counter is kept only in the timer/event counter preload register. The timer/event counter keeps operating until an overflow occurs. When the timer/event counter is read, the clock is blocked to avoid errors, which may result in a counting error. Blocking of the clock should be taken into account by the programmer. Input/Output Ports There are 16 bidirectional input/output lines in the microcontroller, labeled from PA, PC which are mapped to the data memory of [12H], [16H] respectively. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A,[m] (m=12H, 16H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC, PCC) to control the input/output configuration. With this control register, CMOS output or Schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically (i.e. on-the-fly) under software control. To function as an input, the corresponding latch of the control register must write 1. The input source also depends on the control register. If the control register bit is 1 the input will read the pad state. If the control register bit is 0 the contents of the latches will move to the internal bus. The latter is possible in the Read-modify-write instruction. For output function, CMOS configurations can be selected. These control registers are mapped to locations 13H, 17H. After a chip reset, these input/output lines remain at high levels or floating state (depending on the pull-high options). Each bit of these input/output latches can be set or cleared by SET [m].i and CLR [m].i (m=12H, 16H) instructions. Some instructions first input data and then follow the output operations. For example, SET [m].i, CLR [m].i, CPL [m], CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each line of port A has the capability of waking-up the device.
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P u ll- H ig h O p tio n V
DD
C o n tr o l B it
D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r
D CK S
Q Q
D a ta B it Q D CK S Q
W r ite D a ta R e g is te r
PA PC PC PC PC PC PC PC PC
0~P 0 /B 1 /T 2 /T 3 4 /S 5 /S 6 /S 7 /S
MR0 MR1 DO DI CS CK
Z
A7
M R e a d D a ta R e g is te r S y s te m W a k e - u p ( P A o n ly ) B Z fo r P T M R 0 fo r P T M R 1 fo r P P S D O fo r P S D I fo r P S C S fo r P S C K fo r P C0 C1 C2 U
X C o n fig u r a tio n O p tio n
C3 C4 C5 C6 C7
Input/Output Ports Low Voltage Reset - LVR (by Configuration Option) The LVR option is 3.0V. The microcontroller provides a low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device is within the range 0.9V~VLVR, the LVR will automatically reset the device internally. The LVR includes the following specifications:
* The low voltage (0.9V~VLVR) condition has to remain
the Resume line (bit 3 of USC) will be set. In order to make the HT82A851R work properly, the firmware must set USBCKEN (bit 3 of UCC) to 1 and clear SUSP2 (bit4 of the UCC). Since the Resume signal will be cleared before the Idle signal is sent out by the host and the Suspend line (bit 0 of USC) will go to 0. So when the MCU is detecting the Suspend line (bit0 of USC), the condition of the Resume line should be noted and taken into consideration. The following is the timing diagram:
SUSPEND U S B R e s u m e S ig n a l
in its condition for a time exceeding 1ms. If the low voltage state does not exceed 1ms, the LVR will ignore it and will not perform a reset function.
* The LVR uses the OR function with the external
RESET signal to perform a chip reset. Suspend Wake-Up and Remote Wake-Up If there is no signal on the USB bus for over 3ms, the HT82A851R will go into a suspend mode. The Suspend line (bit 0 of the USC) will be set to 1 and a USB interrupt is triggered to indicate that the HT82A851R should jump to the suspend state to meet the requirements of the USB suspend current spec. In order to meet the requirements of the suspend current, the firmware should disable the USB clock by clearing USBCKEN (bit3 of UCC) to 0. Also the user can further decrease the suspend current by setting SUSP2 (bit4 of the UCC). When the resume signal is sent out by the host, the HT82A851R will be woken up by the USB interrupt and
U S B _ IN T
The device with remote wake up function can wake-up the USB Host by sending a wake-up pulse through RMWK (bit 1 of USC). Once the USB Host receives the wake-up signal from the HT82A851R, it will send a Resume signal to the device. The timing is as follows:
SUSPEND M in . 1 USB CLK
M in . 2 .5 m s U S B R e s u m e S ig n a l
RMW K
U S B _ IN T
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USB Interface The HT82A851R device has 5 Endpoints (EP0~EP4). EP0 supports Control transfer. EP1 and EP4 support Interrupt transfer. EP2 supports Isochronous out transfer. EP3 supports Isochronous in transfer. These registers, including USC (20H), USR (21H), UCC (22H), AWR (23H), STALL (24H), SIES (25H), MISC (26H), FIFO0 (28H), FIFO1 (29H), FIFO2 (2AH), FIFO3 (2BH), FIFO4 (2CH) are used for the USB function. The FIFO size of each FIFO is 8 bytes (FIFO0), 8 bytes (FIFO1), 384 bytes (FIFO2), 32 bytes (FIFO3), 32 bytes (FIFO4). The total is 464 bytes. URD (bit7 of USC) is the USB reset signal control function definition bit. Bit No. 0 Label SUSP R/W R Reset 0 Functions Read only, USB suspend indication. When this bit is set to 1 (set by SIE), it indicates that the USB bus has entered the suspend mode. The USB interrupt is also triggered when this bit changes from low to high. USB remote wake-up command. It is set by MCU to force the USB host to leave the suspend mode. USB reset indication. This bit is set/cleared by the USB SIE. This bit is used to detect a USB reset event on the USB bus. When this bit is set to 1, this indicates that a USB reset has occurred and that a USB interrupt will be initialized. USB resume indication. When the USB leaves the suspend mode, this bit is set to 1 (set by SIE). When the RESUME is set by SIE, an interrupt will be generated to wake-up the MCU. In order to detect the suspend state, the MCU should set USBCKEN and clear SUSP2 (in the UCC register) to enable the SIE detect function. RESUME will be cleared when the SUSP goes to 0. When the MCU is detecting the SUSP, the condition of RESUME (causes the MCU to wake-up) should be noted and taken into consideration. 0/1: Turn-off/on V33O output Undefined bit, read as 0. USB reset signal control function definition 1: USB reset signal will reset MCU 0: USB reset signal cannot reset MCU USC (20H) Register
1
RMWK
R/W
0
2
URST
R/W
0
3
RESUME
R
0
4 5~6 7
V33C 3/4 URD
R/W 3/4 R/W
0 3/4 1
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The USR (USB endpoint interrupt status register) register is used to indicate which endpoint is accessed and to select the serial bus (USB). The endpoint request flags (EP0F, EP1F, EP2F, EP3F, EP4F) are used to indicate which endpoints are accessed. If an endpoint is accessed, the related endpoint request flag will be set to 1 and the USB interrupt will occur (if the USB interrupt is enabled and the stack is not full). When the active endpoint request flag is serviced, the endpoint request flag has to be cleared to 0 by software. Bit No. 0 Label EP0F R/W R/W Reset 0 Functions When this bit is set to 1 (set by SIE), it indicates that endpoint 0 has been accessed and a USB interrupt will occur. When the interrupt has been serviced, this bit should be cleared by software. When this bit is set to 1 (set by SIE), it indicates that endpoint 1 has been accessed and a USB interrupt will occur. When the interrupt has been serviced, this bit should be cleared by software. When this bit is set to 1 (set by SIE), it indicates that endpoint 2 has been accessed and a USB interrupt will occur. When the interrupt has been serviced, this bit should be cleared by software. When this bit is set to 1 (set by SIE), it indicates that endpoint 3 has been accessed and a USB interrupt will occur. When the interrupt has been serviced, this bit should be cleared by software. When this bit is set to 1 (set by SIE), it indicates that endpoint 4 has been accessed and a USB interrupt will occur. When the interrupt has been serviced, this bit should be cleared by software. Undefined bit, read as 0. USR (21H) Register There is a system clock control register implemented to select the clock used in the MCU. This register consists of a USB clock control bit (USBCKEN), a second suspend mode control bit (SUSP2) and a system clock selection bit (SYSCLK). The endpoint selection is determined by EPS2, EPS1 and EPS0. Bit No. Label R/W Reset Functions Accessing endpoint FIFO selection, EPS2, EPS1, EPS0: 000: Select endpoint 0 FIFO 001: Select endpoint 1 FIFO 010: Select endpoint 2 FIFO 011: Select endpoint 3 FIFO 100: Select endpoint 4 FIFO 101: reserved for future expansion, cannot be used 110: reserved for future expansion, cannot be used 111: reserved for future expansion, cannot be used If the selected endpoints do not exist, the related function will be absent. USB clock control bit. When this bit is set to 1, it indicates that the USB clock is enabled. Otherwise, the USB clock is turned-off. This bit is used for reducing power consumption in the suspend mode. In normal mode, clear this bit to 0 In the HALT mode, set this bit to 1 to reducing power consumption. Defines the MCU system clock - sourced from the external OSC or from the PLL output - 16MHz clock. 0: system clock sourced from OSC 1: system clock sourced from the PLL output - 16MHz Used to specify the system clock oscillator frequency used by MCU. If a 6MHz crystal oscillator or resonator is used, this bit should be set to 1. If a 12MHz crystal oscillator or resonator is used. this bit should be cleared to 0. UCC (22H) Register
1
EP1F
R/W
0
2
EP2F
R/W
0
3
EP3F
R/W
0
4 5~7
EP4F 3/4
R/W 3/4
0 3/4
0~2
EPS0~ EPS2
R/W
0
3
USBCKEN
R/W
0
4
SUSP2
R/W
0
5
fSYS16MHz
R/W
0
6
SYSCLK
R/W
0
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The AWR register contains the current address and a remote wake up function control bit. The initial value of AWR is 00H. The address value extracted from the the USB command has not to be loaded into this register until the SETUP stage has finished. Bit No. 0 1~7 Label WKEN AD0~AD6 R/W R/W R/W Power-on 0 0000000 Functions USB remote-wake-up enable/disable (1/0) USB device address
AWR (23H) Register The STALL register shows if the corresponding endpoint works properly or not. As soon as the endpoint works improperly, the related bit in the STALL has to be set to 1. The STALL register will be cleared by a USB reset signal. Bit No. 0~4 5~7 Label STL0~STL4 STL5~STL7 R/W R/W 3/4 Power-on 00000 000 Functions Set by the user when related USB endpoints were stalled. Cleared by a USB reset and a Setup Token event. Undefined bit, read as 0.
STALL (24H) Register Bit No. Label R/W Power-on Functions This bit is used to configure the SIE to automatically change the device address by the value stored in the AWR register. When this bit is set to 1 by firmware, the SIE will update the device address by the value stored in the AWR register after the PC host has successfully read the data from the device by an IN operation. Otherwise, when this bit is cleared to 0, the SIE will update the device address immediately after an address is written to the AWR register. So, in order to work properly, the firmware has to clear this bit after a next valid SETUP token is received. This bit is used to indicate that some errors have occurred when the FIFO0 is accessed. This bit is set by SIE and should be cleared by firmware. This bit is used to indicate the OUT token (except the OUT zero length token) has been received. The firmware clears this bit after the OUT data has been read. Also, this bit will be cleared by SIE after the next valid SETUP token is received. This bit is used to indicate the current USB receiving signal from PC host is an IN token. This bit is used to indicate the SIE is a transmitted NAK signal to the host in response to the PC host IN or OUT token. Error condition failure flag include CRC, PID, no integrate token error, CRCF will be set by hardware and the CRCF need to be cleared by firmware. Token pakcage active flag, low active. NAK token interrupt mask flag. If this bit set, when the device sent a NAK token to the host, an interrupt will be disabled. Otherwise if this bit is cleared, when the device sends a NAK token to the host, it will enter the interrupt sub-routine. SIES (25H) Register
0
ASET
R/W
0
1
ERR
R/W
0
2
OUT
R/W
0
3 4
IN NAK
R R
0 0
5 6
CRCF EOT
R/W R
0 1
7
NMI
R/W
0
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The MISC register combines command and status to control the desired endpoint FIFO action and to show the status of the desired endpoint FIFO. MISC will be cleared by a USB reset signal. Bit No. 0 Label REQUEST R/W R/W Power-on 0 Functions After setting the status of the desired one, FIFO can be requested by setting this bit high . After finishing, this bit must be set low. To represent the direction and transition end MCU access. When set to logic 1, the MCU desires to write data to the FIFO. After finishing, this bit must be set to logic 0 before terminating request to represent transition end. For an MCU read operation, this bit must be set to logic 0 and set to logic 1 after finishing. MCU requests to clear the FIFO, even if the FIFO is not ready. After clearing the FIFO, the USB interface will send force_tx_err to tell the Host that data under-run if the Host wants to read data. Enables the isochronous in pipe interrupt. Enables the isochronous out pipe interrupt. To show that the data in the FIFO is a setup command. This bit will remain in this state until the next one enters the FIFO. To show that the desired FIFO is ready To show that the host sent a 0-sized packet to the MCU. This bit must be cleared by a read action to the corresponding FIFO. MISC (26H) Register Bit No. 0 1 2 3 4 5~7 Label DATATG* SETIO1** SETIO2** SETIO3** SETIO4** 3/4 R/W R/W R/W R/W R/W R/W 3/4 Power-on 0 1 0 1 1 3/4 DATA token toggle bit Set endpoint1 input or output pipe (1/0), default input pipe(1) Set endpoint2 input or output pipe (1/0), default output pipe(0) Set endpoint3 input or output pipe (1/0), default input pipe(1) Set endpoint4 input or output pipe (1/0), default input pipe(1) Undefined bit, read as 0 Functions
1
TX
R/W
0
2 3 4 5 6 7
CLEAR ISO_IN_EN ISO_OUT_EN SETCMD READY LEN0
R/W R/W R/W R/W R R
0 0 0 0 0 0
Note: *USB definition: when the host sends a set Configuration, the Data pipe should send the DATA0 (about the Data toggle) first. So, when the Device receives a set configuration setup command, the user needs to toggle this bit as the following data will send a Data0 first. **It is only required to set the data pipe as an input pile or output pile. The purpose of this function is to avoid the host sending a abnormal IN or OUT token and disabling the endpoint. SETIO (27H) Register, USB Endpoint 1 ~ Endpoint 4 Set IN/OUT Pipe Register The speaker output volume and speaker mute/un-mute are controlled by the USB Speaker Volume Control register. The range of the volume is set from 6 dB to -32 dB by software. Speaker mute control: MUTE=0: Mute Speaker output MUTE=1: Normal Bit No. 0~6 7 Label USVC0~ USVC6 MUTE R/W R/W R/W Power-on 0 0 Volume control Bit0~Bit6 Mute control, low active. Functions
USB Speaker Volume Control (1CH) Register
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Result (dB) 6 5.5 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 -0.5 -1 -1.5 USVC 000_1100 000_1011 000_1010 000_1001 000_1000 000_0111 000_0110 000_0101 000_0100 000_0011 000_0010 000_0001 000_0000 111_1111 111_1110 111_1101 Result (dB) -2 -2.5 -3 -3.5 -4 -4.5 -5 -5.5 -6 -6.5 -7 -7.5 -8 -8.5 -9 -9.5 USVC 111_1100 111_1011 111_1010 111_1001 111_1000 111_0111 111_0110 111_0101 111_0100 111_0011 111_0010 111_0001 111_0000 110_1111 110_1110 110_1101 Result (dB) -10 -10.5 -11 -11.5 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 -22 -23 USVC 110_1100 110_1011 110_1010 110_1001 110_1000 110_0111 110_0110 110_0101 110_0100 110_0011 110_0010 110_0001 110_0000 101_1111 101_1110 101_1101 Result (dB) -24 -25 -26 -27 -28 -29 -30 -31 -32 3/4 3/4 3/4 3/4 3/4 3/4 3/4 USVC 101_1100 101_1011 101_1010 101_1001 101_1000 101_0111 101_0110 101_0101 101_0100 3/4 3/4 3/4 3/4 3/4 3/4 3/4
Speaker Volume Control Table Label FIFO0~ FIFO4 R/W R/W Power-on xxH Functions EPi accessing register (i = 0~4). When an endpoint is disabled, the corresponding accessing register should be disabled.
FIFO0~4 (28H~2CH) USB Endpoint Accessing Register Definitions Digital PGA Bit No. 0~5 6 7 Label Functions
There are six bits to control the digital PGA (0~19.5 dB). The PGA is a digital amplifier PGA0~PGA5 used to amplify the 16-bit data that comes from the PCM ADC. The PGA value versus gain relationship is shown in the follow table. 3/4 MUTE_MKB Undefined bit, read as 0. Microphone mute Control: MUTE_MKB =0: Mute microphone input. MUTE_MKB =1: Normal. PGA_CTRL (30H) Register PGA_CRTL Value (PGA5~PGA0) Gain (dB) 0 0.5 : : 19.5 19.5 : : 19.5
000000 000001 : : 100111 101000 : : 111111
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Writing to RECORD_IN_L register will only put the written data to an internal lower-order byte buffer (8-bit) and writing RECORD_IN _H will transfer the RECORD_IN _L and RECORD_IN_H registers content to isochronous in buffer. When record interrupt happened, firmware should write 16-bit 2s complement value to RECORD_IN_L and RECORD_IN_H registers. PFD Control Label PFDC PFDD Bit 7 0 PFDD7 Bit 6 PRES1 PFDD6 Bit 5 PRES0 PFDD5 Bit 4 PFDEN PFDD4 Bit 3 0 PFDD3 Bit 2 0 PFDD2 Bit 1 PFD_IO PFDD1 Bit 0 Reserved PFDD0
The PFD (programmable frequency divider) is implemented in the HT82A851R. It is composed of two portions: a prescaler and a general counter. The prescaler is controlled by the register bits, PRES0 and PRES1. The 4-stage prescaler is divided by 16. The general counter is programmed by an 8-bit register PFDD. The PFDD is inhibited to write while the PFD is disabled. To modify the PFDD contents, the PFD must be enabled. When the generator is disabled, the PFDD is cleared by hardware. PFD prescaler selection: PRES1 0 0 1 1 PRES0 0 1 0 1 PFD frequency source 1 PFD frequency source 2 PFD frequency source 4 PFD frequency source 8 Prescaler Output
The bit PFD_IO is used to determine whether PC0 is a general purpose I/O port or a PFD output. Label PFD_IO=1 PFD_IO=0 PC0 is PFD output PC0 is a general purpose IO Port (Default =0)
PFD F re q u e n c y P r e s c a le r O u tp u t PFD O u tp u t
Functions
fS
YS
/4
4 - S ta g e P r e s c a le r (1 /1 6 )
P r e s c a le r
PFDD
PR ES1,PR ES0 N o te : P F D O u tp u t F re q u e n c y = P r e s c a le r O u tp u t 2 (N + 1 ) , w h e re N
PFDEN
= th e v a lu e o f th e P F D
d a ta
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SPI The serial interface function is similar to the Motorola SPI, where four basic signals are included. These are the SDI (Serial Data Input), SDO (Serial Data Output), SCK (serial clock) and SCS (slave select pin).
SCS
SCK
SDI
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
SDO
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
SPI Timing Label SBCR Default SBDR Default Functions Serial Bus Control Register Serial Bus Data Register D7 CKS 0 D7 U D6 M1 1 D6 U D5 M0 1 D5 U D4 SBEN 0 D4 U D3 MLS 0 D3 U D2 CSEN 0 D2 U D1 WCOL 0 D1 U D0 TRF 0 D0 U
Note: U unchanged Two registers, SBCR and SBDR, are provided for serial interface control, status and data storage.
* SBCR: Serial bus control register

Bit7 (CKS): clock source selection: fSIO = fSYS/2, select as 0; fSIO = fSYS, select as 1 Bit6 (M1), Bit5 (M0): master/slave mode and baud rate selection
-
M1, M0= 00: Master mode, baud rate = fSIO 01: Master mode, baud rate = fSIO/4 10: Master mode, baud rate = fSIO/16 11: Slave mode Enable: (SCS dependent on CSEN bit) Disable (R) enable: SCK, SDI, SDO, SCS =0 (SCK=0) and wait to write data to SBDR (TXRX buffer) Master mode: write data to SBDR (TXRX buffer) (R) start transmission/reception automatically Master mode: when data has been transferred (R) set TRF Slave mode: when a SCK (and SCS dependent on CSEN) is received, data in the TXRX buffer is shifted-out and data on SDI is shifted-in. Disable: SCK (SCK), SDI, SDO, SCS floating and related pins are IO ports. Label SBEN=1 SBEN=0 Functions PC4~PC7 are SPI function pins (pin SCS will go low if CSEN=1). PC4~PC7 are general purpose I/O Port pins - default
Bit4 (SBEN): Serial bus enable/disable (1/0)
-
-
Note: 1. If SBEN=1, the pull-high resistors on PC4~PC7 will be disabled. When this happens external pull-high resistors should be added to the SPI related pins if necessary (EX: pin SCS). 2. If CSEN=0, the SCS pin will enter a floating state.

Bit3 (MLS): MSB or LSB (1/0) shift first control bit Bit2 (CSEN): serial bus selection signal enable/disable (SCS), when CSEN=0, SCS is floating Bit1 (WCOL): this bit is set to 1 if data is written to SBDR (TXRX buffer) when the data is transferring (R) writing will be ignored if data is written to SBDR (TXRX buffer) when the data is transferring WCOL will be set by hardware and cleared by software. Bit 0 (TRF): data transferred or data received (R) used to generate an interrupt Note: data reception is still operational when the MCU enters the Power-down mode 23 June 15, 2007
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* SBDR: Serial bus data register
Data written to SBDR (R) write data to the TXRX buffer only Data read from SBDR (R) read from SBDR only
Operating Mode description: Master transmitter: clock sending and data I/O started by writing to SBDR Master clock sending started by writing to SBDR Slave transmitter: data I/O started by clock reception Slave receiver: data I/O started by clock reception
* Clock polarity = rising (CLK) or falling (CLK): 1 or 0 (software option)
Serial Interface Operation: Label Functions
* Select CKS and select M1,M0 = 00, 01, 10 * Select CSEN, MLS (same as slave) * Set SBEN * Writing data to SBDR (R) data is stored in the TXRX buffer (R) output CLK (and SCS) signals (R) go
Master
* * * * *
to step 5 (R) (SIO internal operation (R) data stored in the TXRX buffer, and the SDI data is shifted into the TXRX buffer (R) data transferred, data in the TXRX buffer is latched into SBDR) Check WCOL; WCOL = 1 (R) clear WCOL and go to step 4; WCOL = 0 (R) go to step 6 Check TRF or waiting for SBI (serial bus interrupt) Read data from SBDR Clear TRF Go to step 4
* CKS dont care and select M1, M0 = 11 * Select CSEN, MLS (same as master) * Set SBEN * Writing data to SBDR (R) data is store in the TXRX buffer (R) waiting for master clock signal (and
Slavehans
* * * * *
SCS): CLK (R) go to step 5 (R) (SIO internal operations (R) CLK (SCS) received (R) output data in TXRX buffer and SDI data is shifted into the TXRX buffer (R) data transferred, data in the TXRX buffer is latched into SBDR) Check WCOL; WCOL = 1 (R) clear WCOL, go to step 4; WCOL = 0 (R) go to step 6 Check TRF or waiting for SBI (serial bus interrupt) Read data from SBDR Clear TRF Go to step 4
* WCOL: master/slave mode, set if writing to SBDR when data is transferring (transmitting or receiving) and this writing
will be ignored. The WCOL function can be enabled/disabled by a software option (SIO_WCOL bit of MODE_CTRL register). WCOL is set by SIO and cleared by the user.
* Data transmission and reception will continue to operated when the MCU enters the power-down mode. * CPOL is used to select the clock polarity of CLK and is a software option (SIO_CPOL bit of MODE_CTRL register). * MLS: MSB or LSB first selection * CSEN: chip select function enable/disable, CSEN = 1 (R) SCS signal function is active. The master should output a
SCS signal before the CLK signal and slave data transferring should be disabled(enabled) before(after) SCS signal received. CSEN = 0, SCS signal is not needed, SCS pin (master and slave) should be floating.
* CSEN: CSEN software option (SIO_CSEN bit of MODE_CTRL register) is used to enable/disable software CSEN
function. If CSEN software option is disable, software CSEN always disabled. If CSEN software option is enabled, software CSEN function can be used.
* SBEN = 1 (R) serial bus standby; SCS (CSEN = 1) = 1; SCS = floating (CSEN = 0); SDI = floating; SDO = 1; master
CLK = output 1/0 (dependent on CPOL software option), slave CLK = floating
* SBEN = 0 (R) serial bus disable; SCS = SDI = SDO = CLK = floating * TRF is set by SIO and cleared by the user. When the data is transferring (transmission and reception) is complete,
TRF is set to generate SBI (serial bus interrupt).
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S B E N = 1 , C S E N = 0 a n d w r ite d a ta to S B D R SCS S B E N = 1 , C S E N = 1 a n d w r ite d a ta to S B D R ( if p u ll- h ig h e d )
( if p u ll- h ig h e d )
CLK
SDI
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
SDO
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
CLK
SIO Timing
Label SBCR Default SBDR Default
Functions Serial Bus Control Register Serial Bus Data Register
D7 CKS 0 D7 U
D6 M1 1 D6 U
D5 M0 1 D5 U
D4 SBEN 0 D4 U
D a ta B u s
D3 MLS 0 D3 U
D2 CSEN 0 D2 U
D1 WCOL 0 D1 U
D0 TRF 0 D0 U
SBDR
( R e c e iv e d D a ta R e g is te r )
D7
D6
D5
D4
D3
D2
D1
D0 M
U X
SDO
B u ffe r
SDO
M LS M In te rn a l B a u d R a te C lo c k EN SCK A n d , S ta rt C lo c k P o la r ity SBEN A n d , S ta rt EN M a s te r o r S la v e SBEN CSEN U X SDI
SBEN
A n d , S ta rt M
U X
C0
C1
C2 AND
TRF W C O L F la g
M a s te r o r S la v e
In te r n a l B u s y F la g SBEN SCS
W r ite S B D R W r ite S B D R E n a b le /D is a b le W r ite S B D R
Block Diagram of SIO
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Label WCOL CESN Set by SIO cleared by users Enable or disable device selection function pin Master mode: 1/0=with/without SCS output control Slave mode: 1/0= with/without SCS input control Enable or disable serial bus (0= initialize all status flags) When SBEN=0, all status flags should be initialized When SBEN=0, all SIO related function pins should stay in a floating state 1= data transmitted or received 0= data is transmitting or still not received Functions
SBEN
TRF
If the clock polarity set to rising edge (SIO_CPOL=1), the serial clock timing will follow CLK, otherwise (SIO_CPOL=0) CLK is the serial clock timing. Mode Control The MODE_CTRL register is used to control SPI function. Bit No. 0~2 3 Label 3/4 PLAY_MODE Reserved Play mode control 1= 8kHz/16-bit 0= 48kHz/16-bit (default) There are three bits used to control the mode of SPI operation. 1= clock polarity rising edge 0= clock polarity falling edge (default) 1= WCOL bit of SBCR register enable 0= WCOL bit of SBCR register disable (default) 1= CSEN bit of SBCR register enable 0= CSEN bit of SBCR register disable (Default) Undefined bit, read as 0 MODE_CTRL (34H) Register SPI Usage Example SPI_Test: clr UCC.@UCC_SYSCLK ;12MHz SYSCLK set SIO_CSEN ;SPI Chip Select Function Enable clr SIO_CPOL ;falling edge change data ;Master Mode, SCLK=fSIO clr M1 clr M0 ;-------------clr CKS ;fSIO=fSYS/2 clr TRF ;clear TRF flag clr TRF_INT ;clear Interrupt SPI flag set MLS ;MSB shift first set CSEN ;Chip Select Enable set SBEN ;SPI Enable, SCS will go low if POLLING_MODE clr ESII ;SPI Interrupt Disable ;WRITE INTO WRITE ENABLE INSTRUCTION MOV A,OP_WREN MOV SBDR,A $0: snz TRF jmp $0 clr TRF else Rev. 1.20 26 June 15, 2007 Functions
4
SIO_CPOL
5 6 7
SIO_WCOL SIO_CSEN 3/4
HT82A851R
set ESII ;SPI Interrupt Enable ;WRITE INTO "WRITE ENABLE" INSTRUCTION MOV A,OP_WREN MOV SBDR,A $0: snz TRF_INT ;set at SPI Interrupt jmp $0 clr TRF_INT endif Play/Record Data The play/record interrupt will be activated when play/record data is valid on PLAY_DATA/ RECORD_DATA registers. The PLAY_DATA/RECORD_DATA registers will latch data until next interrupt happen. The PLAY_DATA is unsigned value (0~FFFFH). RECORD_DATA is 2s complement value (8000H~7FFFH). The update rate of RECORD_DATA is 8kHz . The update rate of PLAY_DATA is 48kHz (PLAY_MODE=0) or 8KHz (PLAY_MODE=1). All these registers (3AH~3FH) are read only. Address 3AH 3BH 3CH 3DH 3EH 3FH Label PLAY_DATAL_L PLAY_DATAL_H PLAY_DATAR_L PLAY_DATAR_H RECORD_DATA_L RECORD_DATA_H Bit 7 PL_D7 Bit 6 PL_D6 Bit 5 PL_D5 Bit 4 PL_D4 Bit 3 PL_D3 Bit 2 PL_D2 Bit 1 PL_D1 PL_D9 PR_D1 Bit 0 PL_D0 PL_D8 PR_D0 PR_D8 R_D0 R_D8
PL_D15 PL_D14 PL_D13 PL_D12 PL_D11 PL_D10 PR_D7 PR_D6 PR_D5 PR_D4 PR_D3 PR_D2
PR_D15 PR_D14 PR_D13 PR_D12 PR_D11 PR_D10 PR_D9 R_D7 R_D15 R_D6 R_D14 R_D5 R_D13 R_D4 R_D12 R_D3 R_D11 R_D2 R_D10 R_D1 R_D9
Configuration Options The following table shows all of the configuration options in the microcontroller. All of the OTP options must be defined to ensure proper system functioning. No. 1 2 3 4 5 6 7 8 Option PA0~PA7 pull-high resistor enabled or disabled (by bit) LVR enable or disable WDT enable or disable WDT clock source: fSYS/4 or WDTOSC CLRWDT instruction(s): 1 or 2 PA0~PA7 wake-up enabled or disabled (by bit) PC0~PC7 pull-high resistor enabled or disabled (by nibble) TBHP enable or disable (default disable)
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Application Circuits
J1 VDD USBUSB+ VSS USB CON 4 1 2 L1 1 2
0 .1 m F
1 2 3 D+ DVSS
0 .1 m F
33W 33W 1 .5 k W USBDN V33O USBDP PA0
U S B A C T IV E D1 330kW G LED
L6 Bead
47pF
47pF
0 .1 m F
10mF
VDD
AVDD1
PA3 AVDD2 PA2 PA1 PA0 50kW PC7 PC6 PC5 PC4 AVDD2 PC3 PC2 PC1 PC0 10 11 12 9 8 7 6 5 4 3 2
1
U1 PA3 PA2 PA1 PA0 P C 7 /S C K P C 6 /S C S P C 5 /S D I P C 4 /S D O PC3 P C 2 /T M R 1 P C 1 /T M R 0 P C 0 /B Z PA4 PA5 PA6 PA7 DVSS1 V33O USBDP USBDN DVDD1 RESET OSCO OSCI
24 23 22 21 20 19 18 17 16 15 14 13
PA4 PA5 PA6 PA7 DVSS1 V33O USBDP USBDN DVDD1 RESET OSCO OSCI 12M H z Y1
0 .1 m F
B e a d F e r r ite
10mF
AVDD1
10W
0 .1 m F 10mF
DVDD
U2 VDD
0 .1 m F
3V3 2
0 .1 m F
5 /3 .3 V 3 V IN VOUT
100kW SW 1 R eset
10mF
GND 1
10mF
H T82A 851R
1 L3 2 AVSS2 AVSS2 PC3 PC7 PC5 7 5 3 1 GND CE SCK VDD CSN MOSI 8 6 4 2 AVDD2 PC6 PC4 PC2
B e a d F e r r ite
M IS O IR Q H eader 4x2
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Instruction Set
Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be CLR PCL or MOV PCL, A. For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Logical and Rotate Operations The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application where rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction RET in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
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Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the SET [m].i or CLR [m].i instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the HALT instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table conventions: x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] INCA [m] INC [m] DECA [m] DEC [m]
Description
Cycles
Flag Affected
Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory
1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 1 1Note 1 1Note
Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z
Logic Operation
Increment & Decrement
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Mnemonic Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 1Note 1Note 1 1 1 1Note 1 1 None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Read table (current page) to TBLH and Data Memory Read table (last page) to TBLH and Data Memory 2Note 2Note None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Description Cycles Flag Affected
Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged.
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Instruction Definition
ADC A,[m] Description Operation Affected flag(s) ADCM A,[m] Description Operation Affected flag(s) ADD A,[m] Description Operation Affected flag(s) ADD A,x Description Operation Affected flag(s) ADDM A,[m] Description Operation Affected flag(s) AND A,[m] Description Operation Affected flag(s) AND A,x Description Operation Affected flag(s) ANDM A,[m] Description Operation Affected flag(s) Rev. 1.20 Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ACC + [m] + C OV, Z, AC, C Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ACC + [m] + C OV, Z, AC, C Add Data Memory to ACC The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. ACC ACC + [m] OV, Z, AC, C Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ACC + x OV, Z, AC, C Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ACC + [m] OV, Z, AC, C Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND [m] Z Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND x Z Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ACC AND [m] Z 32 June 15, 2007
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CALL addr Description Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack Program Counter + 1 Program Counter addr None Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] 00H None Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i 0 None Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF
Operation
Affected flag(s) CLR [m] Description Operation Affected flag(s) CLR [m].i Description Operation Affected flag(s) CLR WDT Description Operation
Affected flag(s) CLR WDT1 Description
Operation
Affected flag(s) CLR WDT2 Description
Operation
Affected flag(s)
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CPL [m] Description Operation Affected flag(s) CPLA [m] Description Complement Data Memory Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] [m] Z Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC [m] Z Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ACC + 00H or [m] ACC + 06H or [m] ACC + 60H or [m] ACC + 66H C Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] [m] - 1 Z Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] - 1 Z Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO 0 PDF 1 TO, PDF
Operation Affected flag(s) DAA [m] Description
Operation
Affected flag(s) DEC [m] Description Operation Affected flag(s) DECA [m] Description Operation Affected flag(s) HALT Description
Operation
Affected flag(s)
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INC [m] Description Operation Affected flag(s) INCA [m] Description Operation Affected flag(s) JMP addr Description Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] [m] + 1 Z Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] + 1 Z Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter addr None Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC [m] None Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC x None Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ACC None No operation No operation is performed. Execution continues with the next instruction. No operation None Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR [m] Z
Operation Affected flag(s) MOV A,[m] Description Operation Affected flag(s) MOV A,x Description Operation Affected flag(s) MOV [m],A Description Operation Affected flag(s) NOP Description Operation Affected flag(s) OR A,[m] Description Operation Affected flag(s)
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OR A,x Description Operation Affected flag(s) ORM A,[m] Description Operation Affected flag(s) RET Description Operation Affected flag(s) RET A,x Description Operation Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR x Z Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ACC OR [m] Z Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter Stack None Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter Stack ACC x None Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit (bit 0; register INTC). If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter Stack EMI 1 None Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 None Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 [m].7 None
Affected flag(s) RETI Description
Operation
Affected flag(s) RL [m] Description Operation
Affected flag(s) RLA [m] Description
Operation
Affected flag(s)
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RLC [m] Description Operation Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 C C [m].7 C Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 C C [m].7 C Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 None Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 [m].0 None Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 C C [m].0 C Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 C C [m].0 C
Affected flag(s) RLCA [m] Description
Operation
Affected flag(s) RR [m] Description Operation
Affected flag(s) RRA [m] Description
Operation
Affected flag(s) RRC [m] Description Operation
Affected flag(s) RRCA [m] Description
Operation
Affected flag(s)
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SBC A,[m] Description Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] - C OV, Z, AC, C Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] - C OV, Z, AC, C Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] - 1 Skip if [m] = 0 None Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC [m] - 1 Skip if ACC = 0 None Set Data Memory Each bit of the specified Data Memory is set to 1. [m] FFH None Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i 1 None
Operation Affected flag(s) SBCM A,[m] Description
Operation Affected flag(s) SDZ [m] Description
Operation Affected flag(s) SDZA [m] Description
Operation
Affected flag(s) SET [m] Description Operation Affected flag(s) SET [m].i Description Operation Affected flag(s)
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SIZ [m] Description Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] + 1 Skip if [m] = 0 None Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] + 1 Skip if ACC = 0 None Skip if bit i of Data Memory is not 0 If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i 0 None Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] OV, Z, AC, C Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] OV, Z, AC, C Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - x OV, Z, AC, C
Operation Affected flag(s) SIZA [m] Description
Operation Affected flag(s) SNZ [m].i Description
Operation Affected flag(s) SUB A,[m] Description
Operation Affected flag(s) SUBM A,[m] Description
Operation Affected flag(s) SUB A,x Description
Operation Affected flag(s)
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SWAP [m] Description Operation Affected flag(s) SWAPA [m] Description Operation Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 [m].7 ~ [m].4 None Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3 ~ ACC.0 [m].7 ~ [m].4 ACC.7 ~ ACC.4 [m].3 ~ [m].0 None Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m] = 0 None Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] Skip if [m] = 0 None Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i = 0 None Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None
Affected flag(s) SZ [m] Description
Operation Affected flag(s) SZA [m] Description
Operation Affected flag(s) SZ [m].i Description
Operation Affected flag(s) TABRDC [m] Description Operation
Affected flag(s) TABRDL [m] Description Operation
Affected flag(s)
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XOR A,[m] Description Operation Affected flag(s) XORM A,[m] Description Operation Affected flag(s) XOR A,x Description Operation Affected flag(s) Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR [m] Z Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ACC XOR [m] Z Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR x Z
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Package Information
24-pin SSOP (209mil) Outline Dimensions
24 A
13 B
1
12
C C' G H D E F
a
Symbol A B C C D E F G H a
Dimensions in mil Min. 291 196 9 311 65 3/4 4 22 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 26 3/4 3/4 3/4 3/4 Max. 323 220 15 345 73 3/4 10 37 8 8
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Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 86-21-6485-5560 Fax: 86-21-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 Fax: 86-10-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 86-28-6653-6590 Fax: 86-28-6653-6591 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com
Copyright O 2007 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
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