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SIP41101
New Product
Vishay Siliconix
Half-Bridge N-Channel MOSFET Driver With Break-Before-Make
FEATURES
D D D D D D D 5-V Gate Drive Undervoltage Lockout Sub 1-W Gate Drivers Internal Bootstrap Diode Drive MOSFETs In 4.5- to 30-V Systems Switching Frequency: 250 kHz to 1 MHz Synchronous Enable/Disable Option
APPLICATIONS
D D D D D D Multi-Phase DC/DC High Current Synchronous Buck Converters High Frequency Synchronous Buck Converters Asynchronous-to-Synchronous Adaptations Mobile Computer DC/DC Converters Desktop Computer DC/DC Converters
DESCRIPTION
The SIP41101 is a high speed half-bridge driver, with make-before-break, for use in high frequency, high current multiphase dc-to-dc power supplies for supply voltages as high as 30 V. It is designed to operate at frequencies up to 1 MHz. The high-side driver is bootstrapped to allow driving an n-channel high-side MOSFET. The bootstrap diode is internal. The output drivers provide currents up to 4 A, allowing use of low rDS(on) power MOSFETs. The SIP41101 comes with internal break-before-make circuitry to prevent shoot-through current in the external MOSFETs. The SD control pin is provided to enable the drivers. A Synchronous Enable control pin is provided to disable the the low-side or synchronous MOSFET to maximize efficiency under low output current conditions.
The SIP41101 is available in a 16-pin TSSOP package for operation over the industrial temperature range of -40 to 85_C.
TYPICAL APPLICATION DIAGRAM
+5 to 30 V +5 V
VDD
BOOT
OUTH
IN Controller SYNC_EN SD
SIP41101
SH VOUT
OUTL
GND
SL
GND
GND
Document Number: 72377 S-31578--Rev. A, 11-Aug-03
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SIP41101
Vishay Siliconix
New Product
ABSOLUTE MAXIMUM RATINGS (ALL VOLTAGES REFERENCED TO GND = 0 V)
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V VSH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V VBOOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSH + 7 V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to 150_C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125_C Power Dissipationa TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925 mW Thermal Impedance (QJA)a TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135_C/W Notes a. Device mounted with all leads soldered or welded to PC board.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING RANGE (ALL VOLTAGES REFERENCED TO GND = 0 V)
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 V to 5.5 V VBOOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 V to 30 V CBOOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 nF to 1 mF Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to 85_C
SPECIFICATIONSa
Test Conditions Unless Specified p Parameter Power Supplies
Supply Voltage Supply Current Quiescent Current VDD IDD IDDQ fIN = 300 kHz, SD = H, Sync_en = H see Figure 1 IN = L, SD = H, Sync_en = H, No Load 4.5 25 1.4 5.5 40 2.5 V mA mA
Limits Mina Typb Maxa Unit
Symbol
VDD = 4.5 to 5.5 V, VBOOT = 4.5 to 30 V, TA = -40 to 85_C
Reference Voltage
Break-Before-Make VBBM VDD = 5.5 V 2.5 V
Logic Inputs -- IN, Sync En, SD
Input High Input Low VIH VIL 2.5 1.0 V
Undervoltage Lockout
VDD Undervoltage Undervoltage Hysteresis VUVL VHYST VDD Rising 2.5 3.6 400 4.4 V mV
Bootstrap Diode
Forward Voltage VF IF = 10 mA 0.65 V
MOSFET Drivers
High-Side High Side Drive Currentc Low-Side Low Side Drive Currentc High-Side High Side Driver Impedance Low-Side Low Side Driver Impedance IPKH(source) IPKH(sink) IPKL(source) IPKL(sink) RDH(source) RDH(sink) RDL(source) RDL(sink) VBOOT - VSH = 4.5 V, VOUTH-VSA=2 25V 45V V =2.25V VDD = 4.5 V, VOUTL=2 25V 45V =2.25V VDD = 4.5 V, SH = GND 45V VDD = 4 5 V 4.5 3.0 3.0 4.1 4.1 0.75 0.75 0.55 0.55 1.3 1.3 1.1 1.1 W A
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Document Number: 72377 S-31578--Rev. A, 11-Aug-03
SIP41101
New Product
SPECIFICATIONSa
Test Conditions Unless Specified Parameter MOSFET Drivers
High-Side Rise Timec High-Side Fall Timec High-Side High Side Propagation Delayc Low-Side Rise Timec Low-Side Fall Timec Low-Side Low Side Propagation Delayc trH tfH td(off)H
DtH-L
Vishay Siliconix
Limits Mina Typb
15 15 25 5 25 15 10 25 ns
Symbol
VDD = 4.5 to 5.5 V, VBOOT = 4.5 to 30 V, TA = -40 to 85_C
Maxa
Unit
10% - 90% 90% - 10% 50% - 50% 10% - 90% 90% - 10% 50% - 50%
trL tfL td(off)L
DtL-H
Notes a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum (-40_ to 85_C). b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. c. Guaranteed by design.
TIMING WAVEFORMS
IN
OUTH
OUTL
td(off)H
DtH-L
td(off)L
DtL-H
TEST SETUP
VDD VDD
BOOT OUTH
1W 2 nF
IN VDD SYNC_EN SD OUTL SH 1.5 W
5 nF GND GND SL
Figure 1.
Document Number: 72377 S-31578--Rev. A, 11-Aug-03 www.vishay.com
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SIP41101
Vishay Siliconix
New Product
PIN CONFIGURATION, ORDERING INFORMATION, AND TRUTH TABLE
SIP41101 (TSSOP-16)
IN GND SYNC_EN SD SL OUTL NC NC 1 2 3 4 5 6 7 8 Top View 16 15 14 13 12 11 10 9 VDD NC VDD NC BOOT NC OUTH SH
ORDERING INFORMATION
Part Number
SIP41101DQ-T1
Temperature Range
-40 to 85_C
Marking
41101
Eval Kit
SIP41101DB
Temperature Range
-40 to 85_C
TRUTH TABLE
SD
H H H H L
SYNC_EN
H H L L X
IN
L H L H X
OUTH
L H L H L
OUTL
H L L L L
PIN DESCRIPTION
Pin
1 2 3 4 5 6 7, 8, 11, 13, 15 9 10 12 14, 16
Name
IN GND SYNC_EN SD SL OUTL NC SH OUTH BOOT VDD Ground
Function
Input signal to the MOSFET drivers Synchronous MOSFET enable Shutdown Connection to source of low-side MOSFET Synchronous or low-side MOSFET gate drive No Connect Connection to source of high-side MOSFET Control or high-side MOSFET gate drive Connection for the bootstrap capacitor +5-V supply
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Document Number: 72377 S-31578--Rev. A, 11-Aug-03
SIP41101
New Product
FUNCTIONAL BLOCK DIAGRAM
VDD BOOT
Vishay Siliconix
Levelshift
OUTH SH
SD
Undervoltage + VDD
VBBM
IN Sync EN GND OUTL SL
Figure 2.
DETAILED OPERATION
Break-Before-Make Function The SIP41101 has an internal break-before-make function to ensure that both high-side and low-side MOSFETs are not turned on at the same time. The high-side drive (OUTH) will not turn on until the low-side gate drive voltage (measured at the OUTL pin) is less than VBBM, thus ensuring that the low-side MOSFET is turned off. The low-side drive (OUTL) will not turn on until the voltage at the MOSFET half-bridge output (measured at the SL pin) is less than VBBM, thus ensuring that the high-side MOSFET is turned Under Voltage Lockout Function The SIP41101 has an internal under-voltage lockout feature to prevent driving the MOSFET gates when the supply voltage (at VDD) is less than the under-voltage lockout specification (VUVL). This prevents the output MOSFETs from being turned on without sufficient gate voltage to ensure they are fully on. There is hysteresis included in this feature to prevent lockout from cycling on and off.
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
100
IDD Supply Current vs. Frequency
50
Rise and Fall Time vs. CLOAD
40 Rise and Fall times (ns) 50 Current (mA) tr(OUTL) 30 tr(OUTH)
20
20
10
tf(OUTL) tf(OUTH)
10 100 200 Frequency (kHz) Document Number: 72377 S-31578--Rev. A, 11-Aug-03 500 1000
0 0.3 1 3 10 Load Capacitance (nF) www.vishay.com
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SIP41101
Vishay Siliconix
TYPICAL WAVEFORMS
New Product
VIN Rising vs. SH
VIN, 2V/div
VIN Falling vs. SH
VIN, 2V/div
SH, 5V/div
SH, 5V/div
25 ns/div 25 ns/div
VIN Rising vs. OUTH and OUTL
VIN, 2V/div
VIN Falling vs. OUTH and OUTL
VIN, 2V/div
OUTH,
10V/div
OUTH, OUTL, OUTL,
5V/div
10V/div
5V/div
25 ns/div
25ns/div
SD vs. OUTL
Sync EN vs. OUTL
SD, 2V/div
Sync EN, 2V/div
OUTL, 5V/div
OUTL,
2V/div
400 ns/div
50ns/div
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Document Number: 72377 S-31578--Rev. A, 11-Aug-03

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