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MP7613
Octal 12-Bit DAC ArrayTM D/A Converter with Output Amplifier and Parallel Data/Address P Control Logic
FEATURES
* Eight Independent Channel 12-Bit DACs with Output Amplifiers * Low Power 320 mW (typ.) * Parallel Digital Data and Address Port * Double Buffered Data Interface * Readback of DAC Latches * Zero Volt Output Preset (Data = 10 .. 00) * 12-Bit Resolution, 11-Bit Accuracy * Extremely Well Matched DACs * Extremely Low Analog Ground Current (<60A/Channel) * +10 V Output Swing with +11.4 V Supplies * Rugged Construction - Latch-Up Proof * Serial Version: MP7612
APPLICATIONS
* * * * * * * Data Acquisition Systems ATE Process Control Self-Diagnostic Systems Logic Analyzers Digital Storage Scopes PC Based Controller/DAS
GENERAL DESCRIPTION
The MP7613 provides eight independent 12-bit resolution Digital-to-Analog Converters with voltage output amplifiers and a parallel digital address and data port. Built on using an advanced linear BiCMOS, these devices offer rugged solutions that are latch-up free, and take advantage of EXAR's patented thin-film resistor process which exhibits excellent long term stability and reliability. A standard -processor and TTL/CMOS compatible 12-bit input data port loads the data into the pre-selected DACS. This device can easily be interfaced to a data bus, and digital readback of each channel is available. Typical DAC matching is 0.7 LSB across all codes. Accuracy of +0.75 LSB for DNL and +1 LSB for INL is achieved for B grade versions. The output amplifier is capable of sinking and sourcing 5mA, and the output voltage settles to 12-bits in less than 30s (typ.).
SIMPLIFIED BLOCK DIAGRAM
RB0 12
VRP
D Q LAT0B XR XE DAC0
DB0 - DB11
12
Bus I/O
12
D Q LAT0A XR XE XE0
+ -
VO0
VRN
A0 - A2 LD1 RD CS R1 R2 LD2
3 8
RB7 XE0 - XE7 RB0 - RB7 D Q LAT7A XR XE XE7 D Q LAT7B XR XE 12
Control Logic
8
VRP
DAC7
VRN
+ -
VO7
VRP VRP VEE VEE VCC VCC AGND AGND VREF DGND DVDD
- +
VRN
VREFN
Rev. 2.00 1
MP7613
ORDERING INFORMATION
Package Type
PQFP PQFP PGA PGA PLCC PLCC
Temperature Range
-40 to +85C -40 to +85C -40 to +85C -40 to +85C -40 to +85C -40 to +85C
Part No.
MP7613BE MP7613AE MP7613BG MP7613AG MP7613BP MP7613AP
Res. (Bits)
12 12 12 12 12 12
INL (LSB)
1 2 1 2 1 2
DNL (LSB)
0.75 1 0.75 1 0.75 1
FSE (LSB)
6 8 6 8 6 8
PIN CONFIGURATIONS
33
See Packaging Section for Package Dimensions
23
34
22
See the following page for pin numbers and descriptions
Index 44 12
See the following page for pin numbers and descriptions
1
11
44-Pin PQFP (14 mm x 14 mm) Q44
1
44-Pin PGA G44
See the following page for pin numbers and descriptions
44-Pin PLCC P44
Rev. 2.00 2
MP7613
PIN OUT DEFINITIONS
PLCC PIN NO. 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PQFP & PGA PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 NAME N/C VO3 VEE VCC DGND VREF VREFN VCC VEE VO4 N/C VO5 VO6 VO7 AGND CS RD R2 R1 LD2 LD1 A2 A1 A0 N/C N/C DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DVDD DGND AGND VO0 VO1 VO2 DESCRIPTION No Connection DAC 3 Output Analog Negative Power Supply (-12 V) Analog Positive Power Supply (+12 V) Digital Ground (0 V) Analog Positive Voltage Reference Input (+5 V) Analog Negative Voltage Reference Output (-2.5 V) Analog Positive Power Supply (+12 V) Analog Negative Power Supply (-12 V) DAC 4 Output No Connection DAC 5 Output DAC 6 Output DAC 7 Output Analog Ground ( 0 V) Chip Select Enable Read Back Enable Second-Latch-Bank Reset Enable First-Latch-Bank Reset Enable Second-Latch-Bank Load Enable First-Latch-Bank Load Enable Digital Address Bit 2 Digital Address Bit 1 Digital Address Bit 0 No Connection No Connection Digital Input Data Bit 0 (LSB) Digital Input Data Bit 1 Digital Input Data Bit 2 Digital Input Data Bit 3 Digital Input Data Bit 4 Digital Input Data Bit 5 Digital Input Data Bit 6 Digital Input Data Bit 7 Digital Input Data Bit 8 Digital Input Data Bit 9 Digital Input Data Bit 10 Digital Input Data Bit 11 (MSB) Digital Positive Power Supply (+5 V) Digital Ground (0 V) Analog Ground (0 V) DAC 0 Output DAC 1 Output DAC 2 Output
Rev. 2.00 3
MP7613
ELECTRICAL CHARACTERISTICS
VCC = +12 V, VEE = -12 V, VREF = 5 V, DVDD = 5.0 V, T = 25C, Output Load = 5k (unless otherwise noted)
Parameter STATIC PERFORMANCE Resolution (All Grades) Integral Non-Linearity (Relative Accuracy) A B Differential Non-Linearity A B Positive Full Scale Error A B Negative Full Scale Error A B Bipolar Zero Offset A B INL Matching A B All Channels Maximum Error with DAC 0 adjusted to minimum error A B Bipolar Zero Matching A B Full Scale Error Matching A B DYNAMIC PERFORMANCE Voltage Settling from LD to VDAC Out1 Channel-to-Channel Crosstalk1, 6 Digital Feedthrough1, 6 Power Supply Rejection Ratio REFERENCE INPUTS Impedance of VREF VREF Voltage1, 2 REF VREF 350 3.5 700 1.05k 6 350 1.05k V See Application Hints for driving the reference input tsd CT Q PSRR 30 0.04 -70 5 50 50 s LSB dB ppm/% ZS to FS (20 V Step) DC CLK and Data to VOUTi VEE & VCC = +5%, ppm of FS N INL 2 1 DNL 1 0.75 +FSE 6 4 -FSE 6 4 ZOFS 4 3 DINL 2 1.5 ME 2 1.5 LSB 4 3 LSB 8 6 8 6 LSB 8 6 8 6 LSB 1 0.75 LSB 2 1 LSB 12 Bits LSB End Point Linearity Spec Symbol Min 25C Typ Max Tmin to Tmax Min Max Units Test Conditions/Comments
4 2 DZUFS 4 3
4 2 LSB 4 3 LSB 4 3
FSE
4 3
Rev. 2.00 4
MP7613
ELECTRICAL CHARACTERISTICS (CONT'D)
Parameter DIGITAL INPUTS3 Logic High Logic Low Input Current Input Capacitance1 ANALOG OUTPUTS Output Swing Output Drive Current VREFN Output Drive Current Output Impedance Output Short Circuit Current -VEE +1.4 -5 -10 RO ISC VCC -1.4 5 +10 1 25 30 40 55 V mA A mA mA mA mA VIH VIL IL CL 2.4 0.8 +10 8 V V A pF Symbol Min 25C Typ Max Tmin to Tmax Min Max Units Test Conditions/Comments
For test purposes only +FS to AGND +FS to VEE -FS to AGND -FS to VCC
DIGITAL OUTPUTS Output High Voltage Output Low Voltage POWER SUPPLIES VCC Voltage5 VEE Voltage5 DVDD Voltage Positive Supply Current Negative Supply Current Digital Supply Current Power Dissipation ANALOG GROUND CURRENT Per Channel1 DIGITAL TIMING SPECIFICATIONS1,4 Data Setup Time Data Hold Time Address Set-up Time Address Hold Time Chip Select to LD1 Set-up Time Chip Select to LD1 Hold Time LD1 Pulse Width LD1 Negative Edge to LD2 Positive Edge LD2 Pulse Width Chip Select to RD Set-Up Time Chip Select to RD Hold Time RD Pulse Width High Z to Data Valid for Readback Data Valid for Readback to High Z R1 Pulse Width R2 Pulse Width tDS tDH tAS tAH tCS1 tCH1 tLD1W tLD1LD2 tLD2W tCS2 tCH2 tRD tDA tDR R1W R2W 20 20 100 0 6 0 50 60 60 6 0 600 600 200 100 100 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns IAGND 60 A See Application Notes VCC VEE DVDD ICC IEE IDD PDISS VREF+1.5 12 -12.75 -12 4.5 5 8 15 320 12.75 -5 5.5 10 20 2 420 VREF+1.5 12.75 -12.75 -5 4.5 5.5 10 20 2 450 V V V mA mA mA mW VOH VOL 4.5 0.5 V V
Bipolar zero Bipolar zero Bipolar zero Bipolar zero
VIL = 0 V, VIH = 5 V, CL = 20 pF
Specifications are subject to change without notice
Rev. 2.00 5
MP7613
ELECTRICAL CHARACTERISTICS (CONT'D)
NOTES: 1 Guaranteed; not tested. 2 Specified values guarantee functionality. 3 Digital inputs should not go below digital GND or exceed DVDD supply voltage. 4 See Figures 1, 2, and 3. All digital input signals are specified with tR = tF = 10 ns 10% to 90% and timed from a 50% voltage level. 5 For power supply values < 2VREF, the output swing is limited as specified in Analog Outputs. 6 Digital feedthrough and channel-to-channel crosstalk are heavily dependent on the board layout and environment. Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS (TA = +25C unless otherwise noted)1, 2
VCC to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +16.5 V VEE to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -16.5 V DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.5 V VREF to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0 V Analog Outputs & Inputs Infinite Shorts to VCC, VEE, DVDD, AGND and DGND (provided that power dissipation of the package spec is not exceeded) AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1 V (Functionality guaranteed for 0.5 V only) Digital Input & Digital Output Voltage to: DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +.5 V DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -.5 V Operating Temperature Range . . . . . . . . . . -40C to +85C Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150C Storage Temperature Range . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +300C Package Power Dissipation Rating to 75C PQFP, PGA, PLCC . . . . . . . . . . . . . . . . . . . . . . 800mW Derates above 75C . . . . . . . . . . . . . . . . . . . 11mW/C
NOTES: 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100s.
APPLICATION NOTES Refer to Section 8 for Applications Information
NOTE: When using these DACs to drive remote devices, the accuracy of the output can be improved by utilizing a remote analog ground connection. The difference between the DGND and AGND should be limited to 300 mV to assure normal operation. If there is any chance that the AGND to DGND can be greater than 1 V, we recommend two back-to-back diodes be used between DGND and AGND to clamp the voltage and prevent damage to the DAC. Using a buffer between the remote ground location and AGND may help reduce noise induced from long lead or trace lengths.
Rev. 2.00 6
MP7613
Data Input/Output Bus Address A0-A2 Chip Select CS Load Latch A LD1 Load Latch B LD2 1 0 1 0 1 0 1 0 1 0 tLD2W Analog Output +FS -FS tSD tLD1LD2 don't care tCS1 tLD1W tAS tAH tCH1 don't care tDS tDH
Figure 1. Loading Latch A and Updating Latch B
Notes (1) Chip Select (CS) and Load LATCHA (LD1) Signals follow the same timing constraints and are interchangeable in the above diagram. (2) R1 = R2 = 1. (3) For the case where LD2 is in the low state, analog output would respond to the falling edge of LD1 (transparent mode).
Address A0-A2 Chip Select CS Data Readback RD Digital Output Data D0 to D13
1 0 1 0 1 0 1 0 don't care
tAS
tAH
don't care tCS2 tDA tRD tCH2 tDR
HIGH-Z
HIGH-Z
Figure 2. Read Back First Latch Bank of One DAC
Notes (1) Chip Select (CS) and Data Readback (RD) Signals follow the same timing constraints and are interchangeable in the above diagram. (2) R1 = R2 = 1.
R1 R2
1 0 1 0
tR1W Reset first latch bank to 1000 . . . . .0000 Reset second latch bank to 1000 . . . . .0000 and analog output to zero volt. tR2W
Figure 3. Reset Operations
Rev. 2.00 7
MP7613
A standard -processor and TTL/CMOS compatible input data port loads the data into the pre-selected DACS. If CS = 0, the chip accesses digital data on the bus. Then address bits A0 to A2 select the appropriate DAC and LD1 loads the data into the first-latch-bank. When all 8-channels first-latch-banks are loaded, then LD2 enables the second-latch-bank and updates all 8-channels simultaneously. The selected DAC becomes transparent (activity on the digital inputs appear at the analog output) when both LD1 = LD2 = 0. R1 = 0 resets the first-latch-bank. R2 = 0 resets the secondlatch-bank which sets the analog output to zero volts (data = 100...00), regardless of digital inputs.
Function
Load Latch 1 of DAC1 Load Latch 1 of DAC2 Load Latch 1 of DAC3 Load Latch 1 of DAC4 Load Latch 1 of DAC5 Load Latch 1 of DAC6 Load Latch 1 of DAC7 Load Latch 1 of DAC8 Load Latch 2 of DAC18 Read Latch 1 of DAC1 Read Latch 1 of DAC2 Read Latch 1 of DAC3 Read Latch 1 of DAC4 Read Latch 1 of DAC5 Read Latch 1 of DAC6 Read Latch 1 of DAC7 Read Latch 1 of DAC8 Reset Latch 1 of DAC18 Reset Latch 2 of DAC18
A2
0 0 0 0 1 1 1 1 X 0 0 0 0 1 1 1 1
A1
0 0 1 1 0 0 1 1 X 0 0 1 1 0 0 1 1
A0
0 1 0 1 0 1 0 1 X 0 1 0 1 0 1 0 1
RD
1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
LD1
01 01 01 01 01 01 01 01 1 1 1 1 1 1 1 1 1
LD2
1 1 1 1 1 1 1 1 01 1 1 1 1 1 1 1 1
CS
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R2
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
X X
X X
X X
X X
X X
X X
X X
0 1
1 0
Note: 1: High, 0: Low, X: Don't Care
Table 1. Octal Parallel Data Input 14-Bit DAC Truth Table
Note: For timing information see Electrical Characteristics
A0 to A2
3
3-8 Decoder
8
8
To first latch bank enable
LD1 8 CS RD LD2 R1 R2 To second latch bank enable To reset all first latch bank To reset all second latch bank 8 To switches across the first latch bank for readback enable
Figure 4. Simplified Parallel Logic Port
Rev. 2.00 8
MP7613
Hex Code 000 Binary Code 000000000000 Output Voltage = 2 * Vr (-1 + 2*D ) (Vr = +5 V) 4096 10 * (-1 + 0) = -10
7FF 800 801
011111111111 100000000000 100000000001
10 * (-1 +
4094 ) = -4.88 mV 4096 4096
10 * (-1 + 4096 ) = 0 10 * (-1 + 4098 ) = 4.88 mV
4096
FFF
111111111111
10 * (-1 + 8190 ) = 9.99512
4096
Table 2. MP7613 Ideal DAC Output vs. Input Code
Note: See Electrical Characteristics on pages 28-30 for real system accuracy
A0 to A15
16 3
AS
Address Decoder
A0 to A2
P
R From System Reset DB0 to DB16 From System Reset
LD1
R1 R2
12 or 14
DB0 to DB11 or DB13
Figure 5. Parallel P Interface
Rev. 2.00 9
MP7613
PERFORMANCE CHARACTERISTICS
11 V
0V
-11 V VOUT 2.5mV
0V
-2.5mV VOUT Settling 50s/Division
Graph 1. Typical Output Settling Characteristic VREF = 5 V, RL = 5K, CL = 500pF
Graph 1 shows the typical output settling characteristic of the MP7610 Family for a RESET !ZS!FS!ZS series of code transitions. The top graph shows the output voltage transients, while the bottom graph shows the difference between the output and the ideal output.
Graph 2. Linearity with VREF = 5 V, All DACs, All Codes
Rev. 2.00 10
MP7613
Graph 3. DAC 0 INL vs. VREF
Graph 4. DAC 0 DNL vs. VREF
Graph 5. DAC 0 Linearity with VREF = 5 V, VOUT = 10
Graph 6. DAC 0 Linearity with VREF = 4.5 V, VOUT = 9
Graph 7. DAC 0 Linearity with VREF = 4 V, VOUT = 8
Rev. 2.00 11
Graph 8. DAC 0 Linearity with VREF = 3.5 V, VOUT = 7
MP7613
VOUT 50W VO
MP7610 Family
5k
500pF
CL
I
2mA
CL = 500pF, 5nF, 50nF, 500nF
Figure 6. Circuit for Determining Typical Analog Output Pulse Response
2.0mA
I
0.0 400mV
VO
-400mV 200mV CL = 500pF CL = 5nF
CL = 50nF
CL = 500nF
VOUT
-200mV 0s 1.0s 2.0s 3.0s 4.0s 5.0s 6.0s
Graph 9. Typical Response of the MP7610 Family Analog Output to a Current Pulse with CL=500pF, 5nF, 50nF, 500nF (See NO TAG above)
Rev. 2.00 12
MP7613
44 LEAD PLASTIC QUAD FLAT PACK (14mm x 14mm PQFP, METRIC) Q44
D D1 33 23
34
22
D1 D
44
12
1 B A2 C e
11
A A1
L
MILLIMETERS SYMBOL A A1 A2 B C D D1 e L MIN -- 0.25 2.6 0.3 0.13 16.95 13.9 MAX 3.15 -- 2.8 0.4 0.23 17.45 14.1
INCHES MIN -- 0.01 0.102 0.012 0.005 0.667 0.547 MAX 0.124 -- 0.110 0.016 0.009 0.687 0.555
1.00 BSC 0.65 0 1.03 7
0.039 BSC 0.026 0 0.040 7
Coplanarity = 4 mil max.
Rev. 2.00 13
MP7613
44 LEAD PIN GRID ARRAY (PGA) G44
D A e b 8 7 6 e D1 5 4 3 2 1 H L1 Seating Plane G F E D C B A Pin 1 D1
D
INCHES SYMBOL A b D D1 e L1 Q 0.170 MIN 0.082 0.016 0.841 0.688 MAX 0.10 0.020 0.859 0.712 0.100 typ. 0.190 0.050 typ.
MILLIMETERS MIN 2.08 0.406 21.4 17.5 MAX 2.54 0.508 21.8 18.1 2.54 typ. 4.32 4.83 1.27 typ. PAD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Rev. 2.00 14
E E E E E E E
Q
CONNECTION TABLE PIN B2 B1 C2 C1 D2 D1 E1 E2 F1 F2 G1 G2 H2 G3 H3 PAD 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 PIN G4 H4 H5 G5 H6 G6 H7 G7 G8 F7 F8 E7 E8 D8 D7 PAD 31 32 33 34 35 36 37 38 39 40 41 42 43 44 PIN C8 C7 B8 B7 A7 B6 A6 B5 A5 A4 B4 A3 B3 A2
Note: The letters A-H and numbers 1-8 are the coordinates of a grid. For example, pin 1 is at the intersections of the "B" vertical line and the "2" horizontal line.
MP7613
44 LEAD PLASTIC LEADED CHIP CARRIER (PLCC) P44
D D1 1 A2 Seating Plane
B D D1 e1 D2
D3
C A1 A
INCHES SYMBOL A A1 A2 B C D D1 (1) D2 D3 e1 Note: (1) MIN 0.165 0.100 0.148 0.013 0.097 0.685 0.650 0590 MAX 0.180 0.110 0.156 0.021 0.0103 0.695 0.654 0.630
MILLIMETERS MIN 4.19 2.54 3.76 0.330 0.246 17.40 16.51 14.99 MAX 4.57 2.79 3.96 0.553 0.261 17.65 16.61 16.00
0.500 Ref 0.050 BSC
12.70 Ref. 1.27 BSC
Dimension D1 does not include mold protrusion. Allowed mold protrusion is 0.254 mm/0.010 in.
Rev. 2.00 15
MP7613
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1993 EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 2.00 16

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