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| R EM MICROELECTRONIC - MARIN SA H6060 Self Recovering Watchdog Description The H6060 is a monolithic low-power CMOS device combining a programmable timer and a series of voltage comparators on the same chip. The device is specially suited for watchdog functions such as microprocessor and supply voltage monitoring. If the P system malfunctions, the watchdog will recover it by issuing repeated active reset signals. The voltage monitoring part provides double security by combining both the unregulated voltage (VIN) and the regulated voltage (VDD) monitoring simultaneously. The H6060 initializes the power-on reset after VIN reaches VSH (see table 4) and VDD rises above 3.V. If VIN drops below VSL (see table 4), the H6060 gives an advanced warning signal for register saving and if the voltage drops further below VRL (see table 4), RES and RES go active. The H6060 functions at any supply voltage down to 1.6 V and is therefore particularly suited for start-up and shut-down control of microprocessor systems. Features Self recovering watchdog function: reset goes active after the 1st timeout period, reset goes inactive again after the 2nd timeout period, repeated active reset signal until the system recovers Standard timeout period and power-on reset time (100 ms), externally programmable if required Unregulated DC monitoring (VIN) with 3 standard or programmable trigger voltages for: power-on reset initialization, advanced power-fail warning ( SAVE ), reset at power-down ( RES ) Regulated DC monitoring (VDD): power-on reset initialization enabled only if VDD 3.5 V Internal voltage reference Works down to 1.6 V supply voltage Push-pull or Open drain outputs Low current consumption SO8 package Applications Microprocessor and microcontroller systems Point of sales equipment Telecom products Automotive subsystems Typical Operating Configuration Pin Assignment H6060 Fig. 1 Fig. 2 Copyright (c) 2004, EM Microelectronic-Marin SA 1 www.emmicroelectronic.com R H6060 Absolute Maximum Ratings Parameter Voltage VDD to VSS Voltage at any pin to VSS Voltage at any pin to VDD (except VIN) Voltage at VIN to VSS Current at any output Storage temperature Symbol VDD VMIN VINMAX VMIN IMAX TSTO Conditions - 0.3 to + 8 V - 0.3 + 0.3 + 15 V 10 mA -65C to +150C Table 1 all terminal voltages are kept within the voltage range. Unused inputs must always be tied to a defined logic voltage level. Operating Conditions Parameter Operating temperature Industrial Supply voltage Comparator input voltage Version 13, 14, 15, 16 Version 11,12 RC-oscillator programming (see Fig. 15) External capacitance External resistance * Leakage < 1A Symbol Min. TAI VDD VIN VIN -40 1.6 0 0 Max. Units +85 5.5 VDD 12 C V V V Stresses above these listed maximum ratings may cause permanent damages to the device. Exposure beyond specified operating conditions may affect device reliability or cause malfunction. Handling Procedures This device has built-in protection against high static voltages or electric fields; however, anti-static precautions must be taken as for any other CMOS component. Unless otherwise specified, proper operation can only occur when C1 R1 1 10 F k Table 2 Electrical Characteristics VDD = 5.0 V, TA = -40 to +85 C, unless otherwise specified Parameter VDD activation threshold VDD deactivation threshold Supply current Input VIN, TCL Leakage current Input current on pin VIN TCL input low level TCL input high level SAVE , RES , RES outputs Leakage currents Drive currents (all versions) Symbol VON VOFF IDD IIP IIN VIL VIH IOLK IOL IOL IOL IOH IOH IOH Test Conditions TA = 25 C TA = 25 C RC open, TCL at VDD or VSS VSS VIP VDD; TA = 85 C Version 12; VIN = 10 V 2.4 Version 15; VOUT = VDD VOL = 0.4 V VDD = 3.5 V; VOL = 0.4 V VDD = 1.6 V; VOL = 0.4 V VOH = 4.0 V VDD = 3.5 V; VOH = 2.8 V VDD = 1.6 V; VOH = 1.2 V Min. 3 VON - 0.3 80 Typ. Max. 3.5 140 Units V V A A A V V 0.005 100 1 180 0.8 Drive currents 1) (versions 14,16) 3.2 2 80 3.2 2 80 0.05 8 1 8 A mA mA A mA mA A Table 3 1) Versions: 15 = open drain outputs; 14, 16 = push-pull outputs VIN Surveillance Voltage thresholds at TA = 25 C Version 14 15, 16 1) 2) 1) Comparator Reference VDD Band-gap reference Input Resistance on VIN (RVIN) 100M 100M VSH 2.25 2.00 Threshold VSL VRL 2.00 1.95 1.75 1.90 2) Thresholds Tolerance Ratio Tolerance 3) 5% 10% 2% 2% Version: 15 = open drain outputs; 14, 16 = push-pull outputs at VDD = 5 V 3) Threshold ratio tolerance is defined as the tolerance of VSH / VSL and VSL / VRL. Table 4 Copyright (c) 2004, EM Microelectronic-Marin SA 2 www.emmicroelectronic.com R H6060 Timing Characteristics VDD = 5.0 V, TA = -40 C to +85 C, unless otherwise specified Parameter Propagation delays TCL to output pins VIN to output pins Logic transition times on all output pins Timeout period TTCL input pulse width Power-on reset debounce VIN low pulse Symbol TDIDO TAIDO TTR TTO TTO TTCL TDB TVINL Test Conditions Min. Typ. 250 4 30 60 45 150 100 Max. 500 10 100 160 200 Units ns s ns ms ms ns ms s Table 5 Excluding debounce time TDB Load 10 k, 100 pF RC open, unshielded, TA = 25 C RC open, unshielded (not tested) TTO/64 Where debounce time TDB Is guaranteed 10 Timing Waveforms Voltage Reaction: VDD Monitoring VDD VON VOFF VIN monitoring enabled Fig. 3 Voltage Reaction: VIN Monitoring VIN VSH VSL VRL TVINL Conditions: VDD > VON. No timeout. TTO 0 SAVE RES RES Timer Start Power-on Reset TTO TDB TDB Timer Stop Timer Start Power-on Reset No Power-on Reset (as VIN > VRL) Fig. 4 Copyright (c) 2004, EM Microelectronic-Marin SA 3 www.emmicroelectronic.com R H6060 Timer Reaction TTCL TCL Conditions: VIN > VRL after power-up sequence TTO TTO TTO RES TTO RES S Timer Reset Timeout Timer Reset Timer Reset Fig. 5 Combined Voltage and Timer Reaction VIN VSH VSL VRL TDB SAVE RES RES TCL Initialisation TTO TTO TTO RES RES Timeout Recover Timer Reset Timer Stop Fig. 6 Block Diagram VDD 1 2 VIN Band-Gap Reference VSH + + Save Control SAVE VSL + VRL Reset Control RES RES + 3 VSS RC Version Connections 11, 12 1 and 3 13, 14 1 15, 16 2 OSC Timer TCL Copyright (c) 2004, EM Microelectronic-Marin SA 4 Fig. 7 www.emmicroelectronic.com R H6060 Pin Description Pin Name 1 2 3 4 5 6 7 8 VIN TCL RC VSS RES SAVE RES VDD Function Voltage sense input Timer clear input signal RC oscillator tuning input GND terminal Active low reset output Save output Active high reset output Positive supply voltage terminal Table 6 Version 14: monitor the unregulated voltage and are ideal for programming of the VIN voltage thresholds. Fixed resistor values can be used for programming. Functional Description Supply Lines The circuit is powered through the VDD and VSS pins. It monitors both its own VDD supply and a voltage applied to the VIN input. VDD Monitoring During power-up the VIN monitoring is disabled and RES , RES and SAVE stay active low as long as VDD is below VON (3.5 V). As soon as VDD reaches the VON level, the state of the outputs depend on the watchdog timer and the voltage at VIN relative to the thresholds (see Fig. 4). If the supply voltage VDD falls back below VOFF (VON - 0.3 V) the watchdog timer and the VIN monitoring are disabled and the outputs RES , RES and SAVE become active. The VDD line should be free of voltage spikes. VIN Monitoring The analog voltage comparators compare the voltage applied to VIN (typically connected to the input of the voltage regulator) with the stabilized supply voltage VDD (version 14) or with the bandgap voltage (versions 15, 16) (see Fig. 7). At power-up, when VDD reached VON and VIN reaches the VSH level, the SAVE output goes inactive, and the timer starts running, setting RES and RES in active after the time TTO (see. Fig. 4). If VIN falls below VSL , the SAVE output goes active and stays active until VIN rises again above VSH . If VIN falls below the voltage VRL , RES and RES will become active and the on-chip timer will stop. When VIN rises again above VSH, the timer will initiate a power-up sequence. The RES and RES outputs may however be influenced independently of the voltage VIN by the timer action, see section Combined Voltage and Timer Action". Monitoring the rough DC side of the regulator, as shown in Fig. 11, is the only way to have advanced warning of power-down. Spikes on VIN should be filtered if they are likely to exceed the value (VSL - VRL). The combination of VIN and VDD monitoring provide high system security: if VIN rises much faster than VDD , then the device starts the power-on sequence only when VDD reached VON (Fig. 10). Short circuits on the regulated supply voltage can be detected. Voltage Thresholds on VIN The H6060 is available with 3 different sets of thresholds: Version 15, 16: monitor the regulated voltage. They are suited to applications where the unregulated voltage is not available. (The tolerance is 10%, see table 4. For tighter tolerances, trimming can be used, see Fig. 9). Monitoring of the unregulated voltage requires version 14. These versions are based on the principle that VDD rises with VIN on power-up an VDD holds up for a certain time after VIN starts dropping on power-down. The versions 11 and 12 have a 100 k nominal resistance from VIN to VSS (internal voltage divider). The versions 14, 15 and 16 have high impedance VIN inputs (see Fig. 7 and Table 4) for external threshold voltage programming by a voltage divider on pin VIN. The levels obtained are proportional to the internal levels VSH, VSL and VRL on the chip itself (see Electrical Specifications). Copyright (c) 2004, EM Microelectronic-Marin SA 5 www.emmicroelectronic.com R H6060 Timer Programming With pin RC unconnected, the on-chip RC oscillator together with its divider chain give a timeout TTO of typically 100 ms. To program different TTO, an approximation for calculating component values is given by the formula: (32 + C1) 2 8.192 TTO =0.75 + V -1 5.5 + DD R1 Timer Clearing and RES /RES Action A negative edge or a negative pulse at the TCL input for longer than 150 ns will reset the timer and set RES and RES inactive. If a further TCL signal edge or pulse is applied before TTO timeout, RES and RES will remain inactive and the timer will again be reset to zero (see Fig. 5). If no TCL signal is applied before the TTO timeout, RES and RES will start to generate square waves of period 2 x TTO starting with the inactive state. The watchdog will remain in this state until the next TCL signal appears, or until a fresh power-up sequence. Combined Voltage and Timer Action The combination of voltage and timer actions is illustrated by the sequence of events shown in Fig. 6. One timeout period after VIN reaches VSH, during power-up, RES and RES go inactive. A TCL pulse will have no effect until this power-on reset delay is completed. After completing the power-up sequence the watchdog timer starts acting. If no TCL pulse occurs, RES and RES go active after one timeout period TTO. After each subsequent timeout period, without a timer clear pulse at TCL , RES and RES change polarity providing square wave signals. A TCL pulse clears the watchdog timer and causes RES and RES to go inactive. A voltage drop below the VRL level overrides the timer and immediately forces RES , RES and SAVE active. Any further TCL pulse has no effect until the next power-up sequence is completed. R1 min. = 10 k, C1 max. = 1 F If R1 is in M and C1 in pF, TTO will be in ms. A resistor decreases and a capacitor increases the interval to timeout. Excellent temperature stability of TTO can be achieved by using external components. A precise square wave of period 2 x TTO is generated at the outputs RES and RES when TCL is tied to either VDD or VSS. The oscillator and watchdog timer start running when both VIN is greater than VSH (see Fig. 6) and VDD is greater than VON (see Fig. 3). They will remain running while both VIN is greater than VRL and VDD is greater than VOFF (see Fig. 3). Typical Applications Microprocessor Watchdog with Power-On Reset and Voltage Monitor Copyright (c) 2004, EM Microelectronic-Marin SA 6 www.emmicroelectronic.com R H6060 Voltage Monitor with Spike Suppression 1) R/F shields for noisy environments. 5 VDC 1) 1) 1) VIN RC VSS H6060 11 VDD 2.7 k +12 VDC rough Voltage Regulator Z-15 330 nF SAVE RES TCL Fig. 11 Watchdog and Power-On Reset External Programming of RC Oscillator Copyright (c) 2004, EM Microelectronic-Marin SA 7 www.emmicroelectronic.com R H6060 Package Information Dimensions of 8-Pin SOIC Package D C L H Dimensions in mm Min Nom Max A 1.35 1.63 1.75 A1 0.10 0.15 0.25 B 0.33 0.41 0.51 C 0.19 0.20 0.25 D 4.80 4.93 5.00 E 3.80 3.94 4.00 e 1.27 H 5.80 5.99 6.20 L 0.40 0.64 1.27 Fig. 14 Fig. 15 E 0 - 8 A1 B A e 4 3 2 5 6 7 8 Ordering Information When ordering please specify complete part number. Part Number Version Threshold (see Table 4) Output Package Delivery Form Package Marking (first line) Temperature H6060V15SO8A H6060V15SO8B H6060V14SO8A H6060V14SO8B H6060V16SO8A H6060V16SO8B V15 V14 V16 1.95 2.00 Open drain 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC Stick Tape&Reel Stick Tape&Reel Stick Tape&Reel 606015 606015 606014 606014 606016 606016 -40C to 85C Push-pull 1.95 Note: Other versions are no longer available EM Microelectronic-Marin SA cannot assume responsibility for use of any circuitry described other than circuitry entirely embodied in an EM Microelectronic-Marin SA product. EM Microelectronic-Marin SA reserves the right to change the circuitry and specifications without notice at any time. You are strongly urged to ensure that the information given has not been superseded by a more up-to-date version. (c) EM Microelectronic-Marin SA, 07/04, Rev. I Copyright (c) 2004, EM Microelectronic-Marin SA 8 www.emmicroelectronic.com |
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