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| 1CY7C266 CY7C266 8Kx8 Power-Switched and Reprogrammable PROM Features * CMOS for optimum speed/power * Windowed for reprogrammability * High speed -- 20 ns (Commercial) * Low power -- 660 mW (Commercial) * Super low standby power -- Less than 85 mW when deselected * EPROM technology 100% programmable * 5V 10% VCC, commercial and military * TTL-compatible I/O * Direct replacement for 27C64 EPROMs powers down into a low-power standby mode. It is packaged in a 600-mil-wide package. The reprogrammable packages are equipped with an erasure window; when exposed to UV light, these PROMs are erased and can then be reprogrammed. The memory cells utilize proven EPROM floating-gate technology and byte-wide intelligent programming algorithms. The CY7C266 is a plug-in replacement for EPROM devices. The EPROM cell requires only 12.5V for the super voltage and low-current requirements allow for gang programming. The EPROM cells allow for each memory location to be tested 100%, as each location is written into, erased, and repeatedly exercised prior to encapsulation. Each PROM is also tested for AC performance to guarantee that after customer programming, the product will meet DC and AC specification limits. Reading is accomplished by placing an active LOW signal on OE and CE. The contents of the memory location addressed by the address lines (A0 through A12) will become available on the output lines (O0 through O7). Functional Description The CY7C266 is a high-performance 8192-word by 8-bit CMOS PROM. When deselected, the CY7C266 automatically Logic Block Diagram O7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 POWER DOWN O1 O2 COLUMN ADDRESS O3 ADDRESS DECODER O4 O5 ROW ADDRESS PROGRAMMABLE ARRAY O6 MULTIPLEXER Pin Configurations CerDIP Top View VCC A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND 1 2 3 4 5 6 7 8 9 7C266 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC VCC NC A8 A9 A11 OE A10 CE O7 O6 O5 O4 O3 LCC Top View A7 A 12 VCC NC VCC VCC NC A6 A5 A4 A3 A2 A1 A0 NC O0 4 3 2 1 32 31 30 29 5 28 6 27 7 26 8 25 9 24 10 23 11 7C266 22 12 21 13 14151617 181920 O1 O2 GND NC O3 O4 O5 A8 A9 A11 NC OE A10 CE O7 O6 O0 CE OE Cypress Semiconductor Corporation Document #: 38-04005 Rev. *B * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 Revised December 27, 2002 CY7C266 Selection Guide 7C266-20 Maximum Access Time Maximum Operating Current Maximum Standby Current Commercial Commercial 20 120 15 7C266-25 25 120 15 7C266-45 45 100 15 Unit ns mA mA Maximum Ratings[1] (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage to Ground Potential (Pin 28 to Pin 14) ........................................... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State ............................................... -0.5V to +7.0V DC Input Voltage............................................ -3.0V to +7.0V DC Program Voltage .................................................... 13.0V Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) Latch-Up Current.................................................... > 200 mA UV Exposure ................................................ 7258 Wsec/cm2 Operating Range Range Commercial Ambient Temperature 0C to +70C VCC 5V 10% Electrical Characteristics Over the Operating Range[2] 7C266-20 Parameter VOH VOL VIH VIL IIX VCD IOZ IOS ICC ISB Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Current Input Diode Clamp Voltage Output Leakage Current Output Short Circuit Current[3] Power Supply Current Standby Supply Current VOL < VOUT < VOH, Output Disabled VCC = Max., VOUT = GND VCC = Max., VIN = 2.0V, IOUT = 0 mA Chip Enable Inactive, CE > VIH, IOUT = 0 mA Com'l Com'l -40 -20 GND < VIN < VCC -10 Test Conditions VCC = Min., IOH = -2.0 mA VCC = Min., IOL = 8.0 mA Com'l Com'l 2.0 0.8 +10 -10 Note 3 +40 -90 120 15 -40 -20 +40 -90 120 15 A mA mA mA Min. 2.4 0.4 2.0 0.8 +10 Max. 7C266-25 Min. 2.4 2.4 0.4 V V V A Max. Unit V Notes: 1. The voltage on any input or I/O pin cannot exceed the power pin during power-up. 2. See the "Introduction to CMOS PROMs" section of the Cypress Data Book for general information on testing. 3. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds. Document #: 38-04005 Rev. *B Page 2 of 11 CY7C266 Electrical Characteristics Over the Operating Range[2] (continued) 7C266-45 Parameter VOH VOL VIH VIL IIX VCD IOZ IOS ICC ISB Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Current Input Diode Clamp Voltage Output Leakage Current Output Short Circuit Current[3] Power Supply Current Standby Supply Current VOL < VOUT < VOH, Output Disabled VCC = Max., VOUT = GND VCC = Max., VIN = 2.0V, IOUT = 0 mA Chip Enable Inactive, CE > VIH, IOUT = 0 mA Com'l Com'l GND < VIN < VCC -10 Note 3 -10 -20 +10 -90 100 15 mA mA mA mA Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 16.0 mA 2.0 0.8 +10 Min. 2.4 0.4 Max. Unit V V V V mA Capacitance[2] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 10 10 Unit pF pF Document #: 38-04005 Rev. *B Page 3 of 11 CY7C266 AC Test Loads and Waveforms Test Load for -20 through -25 speeds R1 500 (658 MIL) 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE 5V OUTPUT R2 333 (403 MIL) 5 pF INCLUDING JIG AND SCOPE R2 333 (403 MIL) R1 500 (658 MIL) 3.0V GND < 5 ns 90% 10% 90% 10% < 5 ns (a) NormalLoad Equivalent to: THE VENIN EQUIVALENT RTH 200 250 MIL (b) HighZ Load OUTPUT Test Load for -35 through -45 speeds R1250 5V OUTPUT 30pF INCLUDING JIG AND SCOPE 5V OUTPUT R2167 5 pF INCLUDING JIG AND SCOPE R2167 R1 250 (c) Normal Load Equivalent to: THE VENIN EQUIVALENT RTH 100 2.0V (d) High Z Load OUTPUT Switching Characteristics Over the Operating Range[2] 7C266-20 Parameter tAA tHZCE tHZOE tAOE tACE tOHA tPU tPD Description Address to Output Valid Chip Enable Inactive to High Z Output Enable Inactive to High Z Output Enable Active to Output Valid Chip Enable Active to Output Valid Data Hold from Address Change Chip Enable Active to Power-up Chip Enable Inactive to Power-down 3 25 25 Min. Max. 20 25 12 12 25 3 30 30 7C266-25 Min. Max. 25 30 12 12 30 3 45 45 7C266-45 Min. Max. 45 45 20 20 45 Unit ns ns ns ns ns ns ns ns Document #: 38-04005 Rev. *B Page 4 of 11 CY7C266 Erasure Characteristics Wavelengths of light less than 4000 angstroms begin to erase the devices in the windowed package. For this reason, an opaque label should be placed over the window if the EPROM is exposed to sunlight or fluorescent lighting for extended periods of time. The recommended dose of ultraviolet light for erasure is a wavelength of 2537 angstroms for a minimum dose (UV intensity multiplied by exposure time) of 25 Wsec/cm2. For an ultraviolet lamp with a 12 mW/cm2 power rating, the exposure time would be approximately 35 minutes. The CY7C266 needs to be within 1 inch of the lamp during erasure. Permanent damage may Table 1. Mode Selection Pin Function[4, 5] Normal Operation Mode Read Standby Output Disable Program Program Verify Program Inhibit Blank Check Program A8 VFY A8 X A8 VIHP VILP VIHP VILP A9 PGM A9 X A9 VILP VIHP VIHP VIHP A10 LAT A10 X A10 VILP VILP VILP VILP A11 NA A11 X A11 VILP VILP VILP VILP A12 NA A12 X A12 VILP VILP VILP VILP CE CE VIL VIH VIL VILP VILP VILP VILP OE VPP VIL X VIH VPP VPP VPP VPP D7-D0 D7-D0 O7-O0 Three-Stated Three-Stated D7-D0 O7-O0 Three-Stated O7-O0 result if the EPROM is exposed to high-intensity UV light for an extended period of time. 7258 Wsec/cm2 is the recommended maximum dosage. Programming Modes Programming support is available from Cypress as well as from a number of third party software vendors. For detailed programming information, including a listing of software packages, please see the PROM Programming Information located at the end of this section. Programming algorithms can be obtained from any Cypress representative. Notes: 4. X = "don't care" but must not exceed VCC + 5%. 5. Address A8-A12 must be latched through lines A0-A4 in Programming modes. CerDIP Top View NC NA A7 A6 A5 A4/A 12 A3/A 11 A2/A 10 A1 /A9 A0 /A8 D0 D1 D2 VSS 1 2 3 4 5 6 7C266 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VPP NC NC VFY PGM NA VPP LAT CE D7 D6 D5 D4 D3 LCC/PLCC Top View A7 NA V CC NC VCC VCC NC A6 A5 A4/A12 A3/A11 A2/A1 A1/A0 9 A0/A8 NC D0 4 3 2 1 32 31 30 29 5 28 6 7C266 27 7 26 8 25 9 24 10 23 11 22 12 21 13 14151617 181920 D1 D2 VSS NC D3 D4 D5 VFY PGM NA NC VPP LAT CE D7 D6 Figure 1. Programming Pinout Document #: 38-04005 Rev. *B Page 5 of 11 CY7C266 Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.6 CC NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 1.2 NORMALIZED ACCESS TIME 1.2 NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE CC 1.4 1.2 1.0 0.8 0.6 4.0 TA = 25C f = fMAX 4.5 5.0 5.5 6.0 NORMALIZED I 1.1 1.0 NORMALIZED I 1.0 0.8 0.9 0.6 TA = 25C 0.4 4.0 4.5 5.0 5.5 6.0 0.8 -55 25 125 SUPPLY VOLTAGE(V) AMBIENT TEMPERATURE(C) SUPPLY VOLTAGE(V) OUTPUT SOURCE CURRENT (mA) NORMALIZED ACCESS TIME vs. TEMPERATURE 1.6 NORMALIZED ACCESS TIME 1.4 1.2 1.0 0.8 0.6 -55 OUTPUT SOURCE CURRENT vs. VOLTAGE 60 50 DELTA tAA (ns) 40 30 20 10 0 0 1.0 2.0 3.0 4.0 35 30 25 20 15 10 5 0 TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING VCC = 4.5V TA = 25C 0 200 400 600 800 1000 25 125 AMBIENT TEMPERATURE (C) OUTPUT VOLTAGE (V) CAPACITANCE (pF) OUTPUT SINK CURRENT (mA) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 175 150 NORMALIZED I CC 125 100 75 50 25 0 0.0 1.0 2.0 3.0 4.0 VCC = 5.0V TA = 25C 1.05 1.00 0.95 0.90 0.85 0.80 0.75 0.70 NORMALIZED SUPPLY CURRENT vs. CYCLE PERIOD VCC = 5.5V TA = 25C 0 25 50 75 100 OUTPUT VOLTAGE (V) CYCLE PERIOD (ns) Document #: 38-04005 Rev. *B Page 6 of 11 CY7C266 Ordering Information] Speed (ns) 20 25 45 Ordering Code CY7C266-20JC CY7C266-20WC CY7C266-25JC CY7C266-45PC Package Name J64 W16 J64 P15 Package Type 28-Lead Plastic Leaded Chip Carrier 28-Lead (600-Mil) Windowed CerDIP 28-Lead Plastic Leaded Chip Carrier 28-Lead (600-Mil) Molded DIP Commercial Commercial Operating Range Commercial Package Diagrams 28-Lead (600-Mil) CerDIP D16 MIL-STD-1835 D-10 Config. A 51-80019-** Document #: 38-04005 Rev. *B Page 7 of 11 CY7C266 Package Diagrams (continued) 32-Pin Rectangular Leadless Chip Carrier L55 MIL-STD-1835 C-12 51-80068-** 28-Lead (600-Mil) Molded DIP P15 51-85017-*A Document #: 38-04005 Rev. *B Page 8 of 11 CY7C266 Package Diagrams (continued) 32-Pin Windowed Rectangular Leadless Chip Carrier Q55 MIL-STD-1835 C-12 51-80103-*A Document #: 38-04005 Rev. *B Page 9 of 11 CY7C266 Package Diagrams (continued) 28-Lead (600-Mil) Windowed CerDIP W16 MIL-STD-1835 D-10 Config. A 51-80020-** All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-04005 Rev. *B Page 10 of 11 (c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C266 Document History Page Document Title: CY7C266 8K x 8 Power Switched and Reprogrammable PROM Document Number: 38-04005 REV. ** *A *B ECN NO. 113861 118897 122246 Issue Date 03/08/02 10/09/02 12/27/02 Orig. of Change DSG GBI RBI Description of Change Change from Spec number: 38-00086 to 38-04005 Update ordering information Add power up requirements to Operating Conditions information Document #: 38-04005 Rev. *B Page 11 of 11 |
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