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TM2SJ64EPN 2097152 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES -- SODIMM
SMMS697A - AUGUST 1997 - REVISED NOVEMBER 1997
D D D D D D D D
Organization: - TM2SJ64EPN . . . 2 097 152 x 64 Bits Single 3.3-V Power Supply (10% Tolerance) Designed for 66-MHz 4-Clock Systems JEDEC 144-Pin Small-Outline Dual-In-Line Memory Module (SODIMM) Without Buffer for Use With Socket TM2SJ64EPN -- Uses Eight 16M-Bit Synchronous Dynamic RAMs (SDRAMs) (2M x 8-Bit) in Plastic Thin Small-Outline Packages (TSOP) Byte-Read/Write Capability Read Latencies 2 and 3 Supported Performance Ranges:
SYNCHRONOUS CLOCK CYCLE TIME tCK2 tCK3 (CL = 3) (CL = 2) ACCESS TIME CLOCK TO OUTPUT tCK2 tCK3 (CL = 3) (CL = 2) 7.5 ns 8 ns 8 ns 9 ns REFRESH INTERVAL
D D D D D D D D
Support Burst-Interleave and Burst-Interrupt Operations Burst Length Programmable to 1, 2, 4, and 8 Two Banks for On-Chip Interleaving (Gapless Access) Ambient Temperature Range 0C to 70C Gold-Plated Contacts Pipeline Architecture High-Speed, Low-Noise Low-Voltage TTL (LVTTL) Interface Serial Presence-Detect (SPD) Using EEPROM
'xSJ64EPN-10 'xSJ64EPN-12
10 ns 12 ns
15 ns 15 ns
64 ms 64 ms
CL = CAS latency
description
The TM2SJ64EPN is a 16M-byte, 144-pin small-outline dual-in-line memory module (SODIMM). The SODIMM is composed of eight TMS626812ADGE, 2 097 152 x 8-bit SDRAMs, each in a 400-mil, 44-pin plastic thin small-outline package (TSOP) mounted on a substrate with decoupling capacitors. See the TMS626812A data sheet (literature number SMOS691).
operation
The TM2SJ64EPN operates as eight TMS626812ADGE devices that are connected as shown in the TM2SJ64EPN functional block diagram.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright (c) 1997, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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PRODUCT PREVIEW
TM2SJ64EPN 2097152 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES -- SODIMM
SMMS697A - AUGUST 1997 - REVISED NOVEMBER 1997
DUAL-IN-LINE MEMORY MODULE ( TOP VIEW )
TM2SJ64EPN ( SIDE VIEW )
PIN NOMENCLATURE A[0:10] A[0:8] A11/BA0 CAS CKE0 CK[0:3] DQ[0:63] DQMB[0:7] NC RAS S0 SCL SDA VDD VSS WE Row Address Inputs Column Address Inputs Bank-Select Zero Column-Address Strobe Clock Enable System Clock Data-In / Data-Out Data-In/Data-Out Mask Enable No Connect Row-Address Strobe Chip-Select SPD Clock SPD Address / Data 3.3-V Supply Ground Write Enable
1
59
PRODUCT PREVIEW
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143
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NO. 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 10 11 9 8 7 6 5 4 3 2 1 PIN DQMB5 DQMB1 DQMB4 DQMB0 NAME DQ39 DQ38 DQ37 DQ36 DQ35 DQ34 DQ33 DQ32 VDD VDD VDD VDD DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 VSS VSS VSS VSS VSS VSS A5 A2 A4 A1 A3 A0 NO. 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 PIN NAME
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TM2SJ64EPN 2097152 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES -- SODIMM
Pin Assignments
DQ45
DQ13
DQ44
DQ12
DQ43
DQ42
DQ10
DQ41
DQ40
DQ11
VDD VDD
DQ9
DQ8
NO.
86
85
84
83
82
81
80
79
78
77
76
75
74
73
PIN NAME
DQ49
DQ17
DQ48
DQ16
SMMS697A - AUGUST 1997 - REVISED NOVEMBER 1997
VDD VDD
VSS VSS
CK1
NC
NC
NC
NC
NC
NO.
122
121AAAAAA DQ24
120
109
119
118
117
116
115
114
113
112AAAAAA NC
110
111
PIN NAME
DQMB7
DQMB3
DQMB6
DQMB2
DQ56
VDD VDD
VSS VSS
A10
NC
A9
PRODUCT PREVIEW
CKE0
DQ47
DQ15
DQ46
DQ14
VDD VDD
CAS
RAS
VSS VSS
CK0
WE
NC
NC
NC
NC
NC
NC
NC
NC
S0
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108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 A11/BA0 DQ55 DQ23 DQ54 DQ22 DQ53 DQ21 DQ52 DQ20 DQ51 DQ19 DQ50 DQ18 VDD VDD VSS VSS VSS VSS A8 A7 A6 144 143 142 141 140 139 138AAAAAA DQ63 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 DQ31 DQ62 DQ30 DQ61 DQ29 DQ60 DQ28 DQ59 DQ27 DQ58 DQ26 DQ57 DQ25 VDD VDD VDD VDD SDA VSS VSS SCL
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TM2SJ64EPN 2097152 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES -- SODIMM
SMMS697A - AUGUST 1997 - REVISED NOVEMBER 1997
small-outline dual-in-line memory module and components
The small-outline dual-in-line memory module and components include:
D D D
PC substrate: 1,10 0,1 mm (0.04 inch) nominal thickness Bypass capacitors: Multilayer ceramic Contact area: Nickel plate and gold plate over copper
functional block diagram for the TM2SJ64EPN
S0 RC CS CS CK: U0, UB0 CK0 UB0 DQMB4 R DQ[0:7] DQ[32:39] 8 DQM DQ[0:7] CK2 CK1 RC CK: U1, UB1 U0 DQMB0 R DQ[0:7] 8 DQM RC CK: U2, UB2 RC CK: U3, UB3 RC C RC CK3 U1 DQMB1 R DQ[8:15] 8 DQM DQ[0:7] DQMB5 R DQ[40:47] 8 DQM DQ[0:7] R = 10 RC = 10 C = 10 pF UB1 C
PRODUCT PREVIEW
CS
CS
CS
CS VDD U2 UB2 DQMB6 R DQ[48:55] 8 DQM DQ[0:7] VSS U[0:3], UB[0:3] Two 0.1 F (minimum) per SDRAM U[0:3], UB[0:3]
DQMB2 R DQ[16:23] 8
DQM DQ[0:7]
CS
CS SPD EEPROM SCL U3 UB3 DQMB7 R DQ[56:63] RAS: SDRAM UB[0:3] CAS: SDRAM UB[0:3] WE: SDRAM UB[0:3] CKE: SDRAM UB[0:3] A[0:11]: SDRAM UB[0:3] 8 DQM DQ[0:7] VSS A0 A1 A2 SDA
DQMB3 R DQ[24:31] RAS CAS WE CKE0 A[0:11] 8
DQM DQ[0:7]
Legend: CS = Chip select SPD = Serial presence detect
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TM2SJ64EPN 2097152 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES -- SODIMM
SMMS697A - AUGUST 1997 - REVISED NOVEMBER 1997
absolute maximum ratings over ambient temperature range (unless otherwise noted)
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4.6 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation: TM2SJ64EPN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 W Ambient temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 125C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
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MIN 3 2 2 0 NOM MAX 3.6 UNIT V V V V V VDD VSS Supply voltage Supply voltage 3.3 0 VIH VIH-SPD High-level input voltage VIL TA Ambient temperature VIL MIN = -1.5 V ac (pulse width High-level input voltage for the SPD device Low-level input voltage VDD + 0.3 5.5 0.8 70 -0.3
v 5 ns)
C
capacitance over recommended ranges of supply voltage and ambient temperature, f = 1 MHz (see Note 2)
PARAMETERS TM2SJ64EPN MIN MAX UNIT pF pF pF pF pF pF pF pF
Ci(CK) Ci(AC) Co
Input capacitance, CK input
18 42 42 12 22 9 7
Input capacitance, address and control inputs: A0 - A11, RASx, CASx, WEx Input capacitance, CKE input Output capacitance
Ci(CKE)
8.5
Ci(DQMBx) Ci(Sx) Ci/o(SDA)
Input capacitance, DQMBx input Input capacitance, Sx input
Input/output capacitance, SDA input
Ci(SPD) Input capacitance, SPD inputs (except SDA) NOTE 2: VDD = 3.3 V 0.3 V. Bias on pins under test is 0 V.
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PRODUCT PREVIEW
TM2SJ64EPN 2097152 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES -- SODIMM
SMMS697A - AUGUST 1997 - REVISED NOVEMBER 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (see Note 3)
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PARAMETER TEST CONDITIONS '2SJ64EPN-10 MIN 2.4 '2SJ64EPN-12 MIN 2.4 MAX MAX UNIT V V VOH VOL II High-level output voltage Low-level output voltage Input current (leakage) IOH = - 2 mA IOL = 2 mA 0.4 0.4 0 V < VI < VDD + 0.3 V, All other pins = 0 V to VDD 0 V < VO < VDD +0.3 V, IO Output current (leakage) Output disabled
TM2SJ64EPN
"10 "10
"10 "10
A A
ICC1
Operating current
Burst length = 1, CAS latency = 2 tRC tRC MIN IOH/IOL = 0 mA, one bank CAS latency = 3 activated (see Note 4) CKE VIL MAX, tCK = 15 ns (see Note 5) CKE VIH MIN, tCK = 15 ns (see Note 5) CKE VIH MIN, CK VIL MAX, tCK = (see Note 6) CKE and CK VIL MAX, tCK = (see Note 6)
760 840 16 16
720 720
mA mA mA mA mA mA mA mA mA mA mA mA mA mA
ICC2P ICC2PS ICC2N
Precharge standby current in g y power-down mode
16 16
PRODUCT PREVIEW
ICC2NS ICC3P ICC3PS ICC3N
Precharge standby current in non-power-down mode Active standby current y power-down mode
200 16 24 24
200
16 24 24
in
CKE VIL MAX, tCK = 15 ns (see Note 5) CKE VIH MIN, tCK = 15 ns (see Note 5) CKE VIH MIN, CK VIL MAX, tCK = (see Note 6)
CKE and CK VIL MAX, tCK = (see Note 6)
ICC3NS
Active standby current non-power-down mode
in
240 80
240
80
ICC4
Burst current
Page burst, IOH/IOL = 0 mA CAS latency = 2 All banks activated, , nCCD = one cycle CAS latency = 3 (see Note 7) tRC tRC MIN CAS latency = 2 CAS latency = 3
800
760
1040 680 760
1000 640 640
ICC5
Auto-refresh Auto refresh current
ICC6 Self-refresh current CKE VIL MAX 16 16 mA NOTES: 3. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid. 4. Control, DQ, and address inputs change state twice during tRC. 5. Control, DQ, and address inputs change state once every 30 ns. 6. Control, DQ, and address inputs do not change. 7. Control, DQ, and address inputs change once every cycle.
6
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TM2SJ64EPN 2097152 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES -- SODIMM
SMMS697A - AUGUST 1997 - REVISED NOVEMBER 1997
ac timing requirements
'2SJ64EPN-10 MIN tCK2 tCK3 tCH tCL tAC2 tAC3 tOH tLZ tHZ tIS tIH tCESP tRAS tRC tRCD tRP tRRD tRSA tAPR tAPW tWR tT tREF nCCD nCDD nCLE nCWL nDID nDOD nHZP2 nHZP3 Cycle time, CLK, CAS latency = 2 Cycle time, CLK, CAS latency = 3 Pulse duration, CLK high Pulse duration, CLK low Access time, CLK high to data out, CAS latency = 2 (see Note 8) Access time, CLK high to data out, CAS latency = 3 (see Note 8) Hold time, CLK high to data out Delay time, CLK high to DQ in low-impedance state (see Note 9) Delay time, CLK high to DQ in high-impedance state (see Note 10) Setup time, address, control, and data input Hold time, address, control, and data input Power-down/self-refresh exit time Delay time, ACTV command to DEAC or DCAB command Delay time, ACTV, REFR, or SLFR exit to ACTV, MRS, REFR, or SLFR command Delay time, ACTV command to READ, READ-P, WRT, or WRT-P command (see Note 11) Delay time, DEAC or DCAB command to ACTV, MRS, REFR, or SLFR command Delay time, ACTV command in one bank to ACTV command in the other bank Delay time, MRS command to ACTV, MRS, REFR, or SLFR command Final data out of READ-P operation to ACTV, MRS, SLFR, or REFR command Final data in of WRT-P operation to ACTV, MRS, SLFR, or REFR command Delay time, final data in of WRT operation to DEAC or DCAB command Transition time (see Note 12) Refresh interval Delay time, READ or WRT command to an interrupting command Delay time, CS low or high to input enabled or inhibited Delay time, CKE high or low to CLK enabled or disabled Delay time, final data in of WRT operation to READ, READ-P, WRT, WRT-P Delay time, ENBL or MASK command to enabled or masked data in Delay time, ENBL or MASK command to enabled or masked data out Delay time, DEAC or DCAB command to DQ in high-impedance state, CAS latency = 2 Delay time, DEAC or DCAB command to DQ in high-impedance state, CAS latency = 3 1 0 1 1 0 2 0 2 2 3 0 1 10 1 5 64 1 0 1 1 0 2 0 2 2 3 0 1 3 1 10 50 80 30 30 20 20 100 000 3 2 8 3 1 10 60 90 30 30 24 24 tRP - (CL -1) * tCK tRP + tCK 12 1 5 64 100 000 15 10 3 3 8 7.5 3 2 8 MAX '2SJ64EPN-12 MIN 15 12 4 4 9 8 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms cycle cycle cycle cycle cycle cycle cycle cycle
nWCD Delay time, WRT command to first data in 0 0 0 0 cycle All references are made to the rising transition of CK unless otherwise noted. NOTES: 8. tAC is referenced from the rising transition of CK that is previous to the data-out cycle. For example, the first data out tAC is referenced from the rising transition of CKx that is CAS latency - one cycle after the READ command. Access time is measured at output reference level 1.4 V. 9. tLZ is measured from the rising transition of CLK that is CAS latency - one cycle after the READ command. 10. tHZ MAX defines the time at which the outputs are no longer driven and is not referenced to output voltage levels. 11. For read or write operations with automatic deactivate, tRCD must be set to satisfy minimum tRAS. 12. Transition time, tT, is measured between VIH and VIL.
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PRODUCT PREVIEW
TM2SJ64EPN 2097152 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES -- SODIMM
SMMS697A - AUGUST 1997 - REVISED NOVEMBER 1997
serial presence detect
The serial presence detect (SPD) is contained in a 2K-bit serial EEPROM located on the module. The SPD nonvolatile EEPROM contains various data such as module configuration, SDRAM organization, and timing parameters (see Table 1). Only the first 128 bytes are programmed by Texas Instruments, while the remaining 128 bytes are available for customer use. Programming is done through a IIC bus using the clock (SCL) and data (SDA) signals. All Texas Instruments modules comply with the current JEDEC SPD Standard. See the Texas Instruments Serial Presence Detect Technical Reference (literature number SMMU001) for further details. Table 1 lists the functions of the TM2SJ64EPN. Table 1. Serial-Presence-Detect Data for the TM2SJ64EPN
BYTE NO. 0 1 DESCRIPTION OF FUNCTION Defines number of bytes written into serial memory during module manufacturing Total number of bytes of SPD memory device Fundamental memory type (FPM, EDO, SDRAM, . . .) Number of row addresses on this assembly Number of column addresses on this assembly Number of module banks on this assembly Data width of this assembly Data width continuation Voltage interface standard of this assembly SDRAM cycle time at maximum supported CAS latency (CL), CL = X SDRAM access from clock at CL = X SODIMM configuration type (non-parity, parity, error-correcting code [ECC]) Refresh rate / type SDRAM width, primary DRAM Error-checking SDRAM data width Minimum clock delay, back-to-back random column addresses Burst lengths supported Number of banks on each SDRAM device CAS latencies supported CS latency Write latency SDRAM module attributes LVTTL tCK = 10 ns tAC = 7.5 ns Non-Parity 15.6 s/ self-refresh x8 N/A 1 CK cycle 1, 2, 4, 8 2 banks 2, 3 0 0 Non-buffered/ Non-registered VDD tolerance = ("10%) , Burst read / write, precharge all, auto precharge tCK = 15 ns TM2SJ64EPN-10 ITEM 128 bytes 256 bytes SDRAM 11 9 1 bank 64 bits DATA 80h 08h 04h 0Bh 09h 01h 40h 00h 01h A0h 75h 00h 80h 08h 00h 01h 0Fh 02h 06h 01h 01h 00h LVTTL tCK = 12 ns tAC = 8 ns Non-Parity 15.6 s/ self-refresh x8 N/A 1 CK cycle 1, 2, 4, 8 2 banks 2, 3 0 0 Non-buffered/ Non-registered VDD tolerance = ("10%), Burst read / write, precharge all, auto precharge tCK = 15 ns TM2SJ64EPN-12 ITEM 128 bytes 256 bytes SDRAM 11 9 1 bank 64 bits DATA 80h 08h 04h 0Bh 09h 01h 40h 00h 01h C0h 80h 00h 80h 08h 00h 01h 0Fh 02h 06h 01h 01h 00h
PRODUCT PREVIEW
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
22
SDRAM device attributes: general
0Eh
0Eh
23
Minimum clock cycle time at CL = X - 1
F0h
F0h
8
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TM2SJ64EPN 2097152 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES -- SODIMM
SMMS697A - AUGUST 1997 - REVISED NOVEMBER 1997
serial presence detect (continued)
Table 1. Serial-Presence-Detect Data for the TM2SJ64EPN (Continued)
BYTE NO. 24 25 26 27 28 29 30 31 32 - 61 62 63 64 - 71 72 73-90 91 92 93-94 95-98 99-125 126-127 128-166 167-255 DESCRIPTION OF FUNCTION Maximum data-access time from clock at CL = X - 1 Minimum clock cycle time at CL = X - 2 Maximum data-access time from clock at CL = X - 2 Minimum row precharge time Minimum row-active to row-active delay Minimum RAS-to-CAS delay Minimum RAS pulse width Density of each bank on module Superset features (may be used in the future) SPD revision Checksum for byte 0 - 62 Manufacturer's JEDEC ID code per JEP - 106E Manufacturing location Manufacturer's part number Die revision code PCB revision code Manufacturing date Assembly serial number Manufacturer specific data Vendor specific data System integrator's specific data Open Rev. 1 158 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD 01h 9Eh 9700...00h Rev. 1 231 97h TBD TBD TBD TBD TBD TBD TBD TBD TBD 01h E7h 9700...00h TM2SJ64EPN-10 ITEM tAC = 8 ns N/A N/A tRP = 30 ns tRRD = 20 ns tRCD = 30 ns tRAS = 50 ns 16M Bytes DATA 80h 00h 00h 1Eh 14h 1Eh 32h 04h TM2SJ64EPN-12 ITEM tAC = 9 ns N/A N/A tRP = 30 ns tRRD = 24 ns tRCD = 30 ns tRAS = 60 ns 16M Bytes DATA 90h 00h 00h 1Eh 18h 1Eh 3Ch 04h
TBD indicates values are determined at manufacturing time and are module dependent. These TBD values are determined and programmed by the customer (optional).
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PRODUCT PREVIEW
TM2SJ64EPN 2097152 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES -- SODIMM
SMMS697A - AUGUST 1997 - REVISED NOVEMBER 1997
device symbolization (TM2SJ64EPN)
TM2SJ64EPN YY MM T -SS = = = =
-SS Year Code Month Code Assembly Site Code Speed Code
YYMMT
NOTE A: Location of symbolization may vary.
PRODUCT PREVIEW
10
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TM2SJ64EPN 2097152 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES -- SODIMM
SMMS697A - AUGUST 1997 - REVISED NOVEMBER 1997
MECHANICAL DATA
BDM (R-SODIMM-N144) SMALL OUTLINE DUAL IN-LINE MEMORY MODULE
2.665 (67,69) 2.655 (67,44) Notch 0.157 (4,00) x 0.079 (2,00) Deep (2 Places) Notch 0.060 (1,52) x 0.158 (4,01) Deep 0.044 (1,12) 0.036 (0,91)
0.024 (0,61) TYP 0.098 (2,49) 0.196 (4,98)
0.031 (0,79)
0.010 (0,25) MAX 0.788 (20,00) TYP 1.005 (25,53) 0.995 (25,27) 0.157 (4,00) 0.126 (3,20) 0.095 (2,41) MAX 0.150 (3,81) MAX (For Double Sided Module Only) 4088187/A 07/97
NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MO-190
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* HOUSTON, TEXAS 77251-1443
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