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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844004I-04
FEMTOCLOCKSTMCRYSTAL/LVCMOS-TOLVDS FREQUENCY SYNTHESIZER
FEATURES
* Four LVDS outputs * Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input * Supports the following applications: SONET/SDH, SATA, or 10Gb Ethernet * Output frequency range: 140MHz - 170MHz, 560MHz - 680MHz * VCO range: 560MHz - 680MHz * Crystal oscillator and CLK range: 17.5MHz - 21.25MHz * RMS phase jitter @ 622.08MHz output, using a 19.44MHz crystal (12kHz - 20MHz): 0.71ps (typical) * RMS phase jitter @ 156.25MHz output, using a 19.53125MHz crystal (1.875MHz - 20MHz): 0.51ps (typical) * RMS phase jitter @ 155.52MHz output, using a 19.44MHz crystal (12kHz - 5MHz): 0.75ps (typical) * Full 3.3V supply mode * -40C to 85C ambient operating temperature * Available in both standard and lead-free RoHS compliant packages
GENERAL DESCRIPTION
The ICS844004I-04 is a 4 output LVDS Synthesizer optimized to generate clock HiPerClockSTM frequencies for a variety of high performance applications and is a member of the HiPerClocks TM family of high perfor mance clock solutions from ICS. This device can select its input reference clock from either a crystal input or a singleended clock signal. It can be configured to generate 4 outputs with individually selectable divide-by-one or divide-by-four function via the 4 frequency select pins (F_SEL[3:0]). The ICS844004I-04 uses ICS' 3 rd generation low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter. This ensures that it will easily meet clocking requirements for SDH (STM-1/ STM-4/STM-16) and SONET (OC-3/OC12/OC-48). This device is suitable for multi-rate and multiple por t line card applications. The ICS844004I-04 is conveniently packaged in a small 24-pin TSSOP package.
IC S
BLOCK DIAGRAM
XTAL_IN
PIN ASSIGNMENT
/1 Phase Detector VCO /4 0 1
OSC
XTAL_OUT CLK Pulldown INPUT_SEL Pulldown
0
Q0 nQ0
1
M = /32
MR F_SEL0
Pulldown Pullup
0 1
Q1 nQ1
nQ1 Q1 VDDo Q0 nQ0 MR F_SEL3 nc VDDA F_SEL0 VDD F_SEL1
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
nQ2 Q2 VDDO Q3 nQ3 GND F_SEL2 INPUT_SEL CLK GND XTAL_IN XTAL_OUT
F_SEL1 Pullup
0 1
ICS844004I-04
Q2 nQ2
F_SEL2
Pullup
24-Lead TSSOP 4.40mm x 7.8mm x 0.92mm package body G Package Top View
0 1
Q3 nQ3
F_SEL3 Pullup
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
844004AGI-04
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REV. A JANUARY 26, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844004I-04
FEMTOCLOCKSTMCRYSTAL/LVCMOS-TOLVDS FREQUENCY SYNTHESIZER
Type Description Differential output pair. LVDS interface levels. Output supply pins. Differential output pair. LVDS interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs nQx Pulldown to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Pullup Frequency select pins. LVCMOS/LVTTL interface levels. See Table 3. No connect. Analog supply pin. Core supply pin. Parallel resonant cr ystal interface. XTAL_OUT is the output, XTAL_IN is the input. Power supply ground. Pulldown LVCMOS/LVTTL clock input. Selects between cr ystal or CLK inputs as the the PLL Reference source. Pulldown Selects XTAL inputs when LOW. Selects CLK when HIGH. LVCMOS/LVTTL interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 22 4, 5 6 7, 10, 12, 18 8 9 11 13, 14 15, 19 16 17 20, 21 23, 24 Name nQ1, Q1 VDDO Q0, nQ0 MR F_SEL3, F_SEL0, F_SEL1, F_SEL2 nc VDDA VDD XTAL_OUT, XTAL_IN GND CL K INPUT_SEL nQ3, Q3 Q2, nQ2 Output Power Ouput Input
Input Unused Power Power Input Power Input Input Output Output
NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLDOWN RPULLUP Parameter Input Capacitance Input Pulldown Resistor Input Pullup Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
TABLE 3. OUTPUT CONFIGURATION
Inputs F_SELx 0 1 0 1 0 1 0 1 XTAL (MHz) 19.44 19.44 18.75 18.75 19.53125 19.53125 20.141601 20.141601
AND
FREQUENCY RANGE FUNCTION TABLE
N Divider Value N0:N3 1 4 1 4 1 4 1 4 Output Frequency (MHz) Q0/nQ0:Q3/nQ3 622.08 155.52 600 150 625 156.25 644.5312 161.13 Application SONET/SDH SATA 10 Gigabit Ethernet 10 Gigabit Ethernet 66B/64B FEC
VCO (MHz) 622.08 622.08 60 0 600 625 625 644.5312 644.5312
844004AGI-04
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REV. A JANUARY 26, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844004I-04
FEMTOCLOCKSTMCRYSTAL/LVCMOS-TOLVDS FREQUENCY SYNTHESIZER
4.6V -0.5V to VCC + 0.5V 10mA 15mA 70C/W (0 mps) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = -40C TO 85C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 80 8 87 Maximum 3.465 3.465 3.465 Units V V V mA mA mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = -40C TO 85C
Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage Input High Current CLK, MR, INPUT_SEL F_SEL0:F_SEL3 IIL V/T Input Low Current Input Edge Rate CLK, MR, INPUT_SEL F_SEL0:F_SEL3 CLK VDD = VIN = 3.465 VDD = VIN = 3.465 VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V 20% - 80% -5 -150 TBD Test Conditions Minimum Typical 2 -0.3 Maximum VDD + 0.3 0.8 150 5 Units V V A A A A V/ns
TABLE 4C. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = -40C TO 85C
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change Test Conditions Minimum Typical 350 40 1.35 50 Maximum Units mV mV V mV
844004AGI-04
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REV. A JANUARY 26, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844004I-04
FEMTOCLOCKSTMCRYSTAL/LVCMOS-TOLVDS FREQUENCY SYNTHESIZER
Test Conditions Minimum 17.5 Typical Maximum 21.25 50 7 1 Units MHz pF mW
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level NOTE: Characterized using an 18pF parallel resonant crystal. Fundamental
TABLE 6. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = -40C TO 85C
Symbol fOUT tsk(o) Parameter Output Frequency Output Skew; NOTE 1, 2 155.52MHz, Integration Range: 12kHz - 20MHz 156.25MHz, Integration Range: 1.875MHz - 20MHz 622.08MHz, Integration Range: 12kHz - 20MHz 20% to 80% Test Conditions Output Divider = /1 Output Divider = /4 Minimum 560 140 TBD 0.75 0.51 0.71 29 0 Typical Maximum 680 170 Units MHz MH z ps ps ps ps ps %
tjit(O)
RMS Phase Jitter (Random); NOTE 3
t R / tF
Output Rise/Fall Time
odc Output Duty Cycle 50 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot.
844004AGI-04
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REV. A JANUARY 26, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844004I-04
FEMTOCLOCKSTMCRYSTAL/LVCMOS-TOLVDS FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE AT 155.52MHZ AT 3.3V
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100
OC3 SONET Filter 155.52MHz
RMS Phase Jitter (Random) 12kHz to 5MHz = 0.75ps (typical)
NOISE POWER dBc Hz
Raw Phase Noise Data
-110 -120 -130 -140 -150 -160 -170 -180 -190 10 100
1k
Phase Noise Result by adding OC3 SONET Filter to raw data
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 622.08MHZ AT 3.3V
0 -10 -20 -30 -40 -50 -60
OC 12 SONET Filter 622.08MHz
RMS Phase Jitter (Random) 12kHz to 20MHz = 0.71ps (typical)
NOISE POWER dBc Hz
-70 -80 -90 -100 -110 -120 -140 -150 -160 -170 -180 -190 10 100 1k 10k
Raw Phase Noise Data
Phase Noise Result by adding OC 12 SONET Filter to raw data
-130
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
844004AGI-04
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REV. A JANUARY 26, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844004I-04
FEMTOCLOCKSTMCRYSTAL/LVCMOS-TOLVDS FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
V DD nQx
SCOPE
Qx
Qx nQy
Power Supply +
Float GND
-
LVDS
nQx
Qy
tsk(o)
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
OUTPUT SKEW
Noise Power
nQ0:nQ3 Q0:Q3
Phase Noise Mask
t PW
t
PERIOD
f1
Offset Frequency
odc =
f2
t PW t PERIOD
x 100%
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
VDD out
80% Clock Outputs
80% VSW I N G
DC Input
LVDS
out
20% tR tF
20%
VOS/ VOS
OUTPUT RISE/FALL TIME
VDD out
OFFSET VOLTAGE SETUP
DC Input
LVDS
100
VOD/ VOD out
DIFFERENTIAL OUTPUT VOLTAGE SETUP
844004AGI-04
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REV. A JANUARY 26, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844004I-04
FEMTOCLOCKSTMCRYSTAL/LVCMOS-TOLVDS FREQUENCY SYNTHESIZER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS844004I-04 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA.
3.3V VDD .01F VDDA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS844004I-04 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 19.44MHz 18pF parallel resonant crystal and were chosen to minimize the ppm error.
XTAL_IN C1 22p X1 18pF Parallel Cry stal XTAL_OUT C2 22p ICS84332 ICS844004I-04
Figure 2. CRYSTAL INPUt INTERFACE
844004AGI-04
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REV. A JANUARY 26, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844004I-04
FEMTOCLOCKSTMCRYSTAL/LVCMOS-TOLVDS FREQUENCY SYNTHESIZER
AND
RECOMMENDATIONS FOR UNUSED INPUT
INPUTS:
OUTPUT PINS
OUTPUTS:
LVDS All unused LVDS outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
CRYSTAL INPUT: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. CLK INPUT: For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the CLK input to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
3.3V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 3. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs.
3.3V 3.3V LVDS + R1 100
-
100 Ohm Differential Transmission Line
FIGURE 3. TYPICAL LVDS DRIVER TERMINATION
844004AGI-04
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REV. A JANUARY 26, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844004I-04
FEMTOCLOCKSTMCRYSTAL/LVCMOS-TOLVDS FREQUENCY SYNTHESIZER
Each decoupling capacitor should be located as close as possible to the power pin. The low pass filter R2, C3 and C4 should also be located as close to the VCCA pin as possible. For LVDS driver, the unused output pairs should be terminated with a 100 resistor across.
SCHEMATIC EXAMPLE
Figure 4 shows a schematic example for ICS844004i-04. In this example, the input is a 19.44MHz parallel resonant crystal with load capacitor CL=18pF. The 22pF frequency fine tuning capacitors are used C1 and C2. This example also shows general logic control input handling. For decoupling capacitors, it is recommended to have one decouple capacitor per power pin.
VCC R2 10
VCCA Zo = 50 Ohm C3 10uF C4 0.01u VCC VCCO C6 0.1u 12 11 10 9 8 7 6 5 4 3 2 1 Zo = 50 Ohm C7 0.1u R3 100 +
Logic Control Input Examples
VCC
Set Logic Input to '1'
RU1 1K
VCC
Set Logic Input to '0'
RU2 Not Install
To Logic Input pins
RD1 Not Install RD2 1K
To Logic Input pins
XTAL_OUT XTAL_IN GND CLK INPUT_SEL F_SEL2 GND nQ3 Q3 VDDO Q2 nQ2
F_SEL1 VDD F_SEL0 VDDA NC F_SEL3 MR nQ0 Q0 VDDO Q1 nQ1
VCC=3.3V VCCO=3.3V
U1 844004i-04
13 14 15 16 17 18 19 20 21 22 23 24
Zo = 50 Ohm + VCC R4 100 Zo = 50 Ohm VCCO C8 0.1u -
C2 33pF
X1 19.44MHz 18pF C1 27pF
C9 0.1u
FIGURE 4. ICS844004I-04 SCHEMATIC EXAMPLE
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REV. A JANUARY 26, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844004I-04
FEMTOCLOCKSTMCRYSTAL/LVCMOS-TOLVDS FREQUENCY SYNTHESIZER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS844004I-04. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS844004I-04 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
* *
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (80mA + 8mA) = 304.92mW Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 87mA = 301.45mW
Total Power_MAX = 304.92mW + 301.45mW = 606.37mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature qJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 65C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.606W * 65C/W = 124C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE JA FOR 24-LEAD TSSOP, FORCED CONVECTION
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 70C/W
1
65C/W
2.5
62C/W
844004AGI-04
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REV. A JANUARY 26, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844004I-04
FEMTOCLOCKSTMCRYSTAL/LVCMOS-TOLVDS FREQUENCY SYNTHESIZER RELIABILITY INFORMATION
TABLE 8. JAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 70C/W
1
65C/W
2.5
62C/W
TRANSISTOR COUNT
The transistor count for ICS844004I-04 is: 2285
844004AGI-04
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REV. A JANUARY 26, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844004I-04
FEMTOCLOCKSTMCRYSTAL/LVCMOS-TOLVDS FREQUENCY SYNTHESIZER
24 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 9. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 7.70 6.40 BASIC 4.50 Millimeters Minimum 24 1.20 0.15 1.05 0.30 0.20 7.90 Maximum
Reference Document: JEDEC Publication 95, MO-153
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REV. A JANUARY 26, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844004I-04
FEMTOCLOCKSTMCRYSTAL/LVCMOS-TOLVDS FREQUENCY SYNTHESIZER
Marking Package 24 Lead TSSOP 24 Lead TSSOP 24 Lead "Lead-Free" TSSOP 24 Lead "Lead-Free" TSSOP Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
TABLE 10. ORDERING INFORMATION
Part/Order Number ICS844004AGI-04 ICS844004AGI-04T ICS844004AGI-04LF ICS844004AGI-04LFT ICS844004AI04 ICS844004AI04 ICS44004AI04L ICS44004AI04L
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FEMTOCLOCKS are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 844004AGI-04
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