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TLV2401, TLV2402, TLV2404 FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION
SLOS244A - FEBRUARY 2000 - REVISED JUNE 2000
D D D D D D D D
I CC - Supply Current - A/Ch
Micro-Power Operation . . . < 1 A/Channel Input Common-Mode Range Exceeds the Rails . . . -0.1 V to VCC + 5 V Rail-to-Rail Input/Output Gain Bandwidth Product . . . 5.5 kHz Supply Voltage Range . . . 2.5 V to 16 V Specified Temperature Range - TA = 0C to 70C . . . Commercial Grade - TA = -40C to 125C . . . Industrial Grade Ultra-Small Packaging - 5-Pin SOT-23 (TLV2401) - 8-Pin MSOP (TLV2402) Universal OpAmp EVM
TLV2402 D, DGK, OR P PACKAGE (TOP VIEW)
1OUT 1IN - 1IN + GND
1 2 3 4
8 7 6 5
VCC 2OUT 2IN - 2IN+
SUPPLY CURRENT vs SUPPLY VOLTAGE
1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 2 4 6 8 10 12 14 16 VCC - Supply Voltage - V AV = 1 VIN = VCC / 2 TA =25 C
description
The TLV240x family of single-supply operational amplifiers has the lowest supply current available today at only 880 nA per channel. Added to this is reverse battery protection making the device even more ideal for battery powered systems. And for harsh environments, the inputs can be taken 5 V above the positive supply rail without damage to the device.
The low supply current is coupled with extremely low input bias currents enabling them to be used with mega- resistors making them ideal for portable, long active life, applications. DC accuracy is ensured with a low typical offset voltage as low as 390 V, CMRR of 120 dB and minimum open loop gain of 130 V/mV at 2.7 V. The maximum recommended supply voltage is as high as 16 V and ensured operation down to 2.5 V, with electrical characteristics specified at 2.7 V, 5 V and 15 V. The 2.5-V operation makes it compatible with Li-Ion battery-powered systems and many micro-power microcontrollers available today including TI's MSP430. All members are available in PDIP and SOIC with the singles in the small SOT-23 package, duals in the MSOP, and quads in TSSOP.
FAMILY PACKAGE TABLE DEVICE TLV2401 TLV2402 TLV2404 NO OF Ch NO. 1 2 4 PACKAGE TYPES PDIP 8 8 14 SOIC 8 8 14 SOT-23 5 -- -- TSSOP -- -- 14 MSOP -- 8 -- UNIVERSAL EVM Refer to the EVM Selection Guide (Lit# SLOU060)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2000, Texas Instruments Incorporated
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SLOS244A - FEBRUARY 2000 - REVISED JUNE 2000
TLV2401 AVAILABLE OPTIONS TA 0C to 70C - 40C to 125C VIOmax AT 25C 1500 V SMALL OUTLINE (D) TLV2401CD TLV2401ID PACKAGED DEVICES SOT-23 SYMBOLS (DBV) TLV2401CDBV TLV2401IDBV VAWC VAWI PLASTIC DIP (P) -- TLV2401IP
This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2401CDR). TLV2402 AVAILABLE OPTIONS TA 0C to 70C - 40C to 125C VIOmax AT 25C 1500 V SMALL OUTLINE (D) TLV2402CD TLV2402ID PACKAGED DEVICES MSOP SYMBOLS (DGK) TLV2402CDGK TLV2402IDGK xxTIAIX xxTIAIY PLASTIC DIP (P) -- TLV2402IP
This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2402CDR). TLV2404 AVAILABLE OPTIONS TA 0C to 70C - 40C to 125C VIOmax AT 25C 1500 V PACKAGED DEVICES SMALL OUTLINE PLASTIC DIP (N) (D) TLV2404CD TLV2404ID TLV2404CN TLV2404IN TSSOP (PW) TLV2404CPW
TLV2404IPW This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2404CDR).
TLV240x PACKAGE PINOUTS
TLV2401 DBV PACKAGE (TOP VIEW) OUT GND IN+ 1 2 3 4 IN - 5 VCC TLV2401 D OR P PACKAGE (TOP VIEW) TLV2402 D, DGK, OR P PACKAGE (TOP VIEW)
NC IN - IN + GND
1 2 3 4
8 7 6 5
NC VCC OUT NC
1OUT 1IN - 1IN + GND
1 2 3 4
8 7 6 5
VCC 2OUT 2IN - 2IN+
TLV2404 D, N, OR PW PACKAGE (TOP VIEW)
1OUT 1IN - 1IN+ VCC 2IN+ 2IN - 2OUT
NC - No internal connection
1 2 3 4 5 6 7
14 13 12 11 10 9 8
4OUT 4IN - 4IN+ GND 3IN+ 3IN - 3OUT
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TLV2401, TLV2402, TLV2404 FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION
SLOS244A - FEBRUARY 2000 - REVISED JUNE 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 V Differential input voltage, VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V Input current, II (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA: C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 125C Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values, except differential voltages, are with respect to GND DISSIPATION RATING TABLE PACKAGE D (8) D (14) DBV (5) DGK (8) N (14) P (8) PW (14) JC (C/W) 38.3 26.9 55 54.2 32 41 29.3 JA (C/W) 176 122.6 324.1 259.9 78 104 173.6 TA 25C POWER RATING 710 mW 1022 mW 385 mW 481 mW 1600 mW 1200 mW 720 mW TA = 125C POWER RATING 142 mW 204.4 mW 77.1 mW 96.2 mW 320.5 mW 240.4 mW 144 mW
recommended operating conditions
MIN Supply voltage VCC voltage, Common-mode input voltage range, VICR Operating free-air temperature, TA free air temperature C-suffix I-suffix Single supply Split supply 2.5 1.25 -0.1 0 - 40 MAX 16 8 VCC+5 70 125 UNIT V V C
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electrical characteristics at recommended operating conditions, VCC = 2.7, 5 V, and 15 V (unless otherwise noted)
dc performance
PARAMETER VIO VIO Input offset voltage Offset voltage draft TEST CONDITIONS VO = VCC/2 V, VIC = VCC/2 V, RS = 50 VCC = 2 7 V 2.7 CMRR Common mode rejection ratio Common-mode VIC = 0 to VCC, RS = 50 VCC = 5 V VCC = 15 V VCC = 2 7 V VO( ) = 1 V RL = 500 k 2.7 V, O(pp) V, AVD Large-signal differential voltage g g g amplification VCC = 5 V V, VCC = 15 V V, VO( ) = 3 V RL = 500 k V, O(pp) VO( ) = 6 V RL = 500 k V, O(pp) TA 25C Full range 25C 25C Full range 25C Full range 25C Full range 25C Full range 25C Full range 25C Full range 63 60 70 63 80 75 130 30 300 100 1000 120 1800 1000 V/mV 400 120 120 dB 3 120 MIN TYP 390 MAX 1200 1500 UNIT V V/C
Full range is 0C to 70C for the C suffix and -40C to 125C for the I suffix. If not specified, full range is - 40C to 125C.
input characteristics
PARAMETER TEST CONDITIONS TA 25C Full range 25C TLV240xC TLV240xI ri(d) Differential input resistance Full range 25C 300 100 MIN TYP 25 MAX 250 300 400 300 350 900 M pF pA pA UNIT
IIO
Input offset current VO = VCC/2 V, V, VIC = VCC/2 V RS = 50
TLV240xC TLV240xI
IIB
Input bias current
Ci(c) Common-mode input capacitance f = 100 kHz 25C 3 Full range is 0C to 70C for the C suffix and -40C to 125C for the I suffix. If not specified, full range is - 40C to 125C.
4
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electrical characteristics at recommended operating conditions, VCC = 2.7, 5 V, and 15 V (unless otherwise noted) (continued)
output characteristics
PARAMETER TEST CONDITIONS VCC = 2 7 V 2.7 VIC = VCC/2, , IOH = -2 A VCC = 5 V VCC = 15 V VOH High-level High level output voltage VCC = 2 7 V 2.7 , VIC = VCC/2, IOH = -50 A VCC = 5 V VCC = 15 V VIC = VCC/2 IOL = 2 A /2, VOL Low-level Low level output voltage VIC = VCC/2 IOL = 50 A /2, TA 25C Full range 25C Full range 25C Full range 25C Full range 25C Full range 25C Full range 25C Full range 25C Full range 180 MIN 2.65 2.63 4.95 4.93 14.95 14.93 2.62 2.6 4.92 4.9 14.92 14.9 90 150 180 230 260 A mV 14.95 4.95 2.65 14.98 V 4.98 TYP 2.68 MAX UNIT
IO Output current VO = 0.5 V from rail 25C 200 Full range is 0C to 70C for the C suffix and -40C to 125C for the I suffix. If not specified, full range is - 40C to 125C.
power supply
PARAMETER TEST CONDITIONS VCC = 2.7 V or 5 V 27 ICC Supply current (per channel) VO = VCC/2 VCC = 15 V Reverse supply current VCC = -18 V, VIN = 0 V, VO = Open circuit VCC = 2.7 to 5 V, VIC = VCC/2 V, No load, VCC = 5 to 15 V, No load TLV240xC TLV240xI VIC = VCC/2 V, TA 25C Full range 25C Full range 25C 25C Full range 25C Full range 100 96 85 100 100 120 50 120 900 MIN TYP 880 MAX 950 1290 990 1350 nA dB dB dB nA UNIT
PSRR
Power supply rejection ratio (VCC/VIO)
Full range is 0C to 70C for the C suffix and -40C to 125C for the I suffix. If not specified, full range is - 40C to 125C.
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electrical characteristics at recommended operating conditions, VCC = 2.7, 5 V, and 15 V (unless otherwise noted) (continued)
dynamic performance
PARAMETER UGBW SR M Unity gain bandwidth Slew rate at unity gain Phase margin Gain margin RL = 500 k, VO(pp) = 0.8 V, RL = 500 k k, VCC = 2.7 or 5 V, V(STEP)PP = 1 V, AV = -1, VCC = 15 V, V(STEP)PP = 1 V V, AV = -1, RL = 500 k, CL = 100 pF TEST CONDITIONS CL = 100 pF CL = 100 pF TA 25C 25C 25C MIN TYP 5.5 2.5 60 15 1.84 25C 0.1% CL = 100 pF F, RL = 100 k 0.01% 6.1 32 ms dB MAX UNIT kHz V/ms
ts
Settling time
CL = 100 pF, RL = 100 k
0.1%
noise/distortion performance
PARAMETER Vn In Equivalent input noise voltage Equivalent input noise current TEST CONDITIONS f = 10 Hz f = 100 Hz f = 100 Hz 25C TA MIN TYP 800 500 8 MAX UNIT nV/Hz fA/Hz
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TYPICAL CHARACTERISTICS Table of Graphs
FIGURE VIO IIB IIO CMRR VOH VOL VO(PP) Zo ICC PSRR AVD Input Offset Voltage Input Bias Current Input Offset Current Common-mode rejection ratio High-level output voltage Low-level output voltage Output voltage peak-to-peak Output impedance Supply current Power supply rejection ratio Differential voltage gain Phase Gain-bandwidth product SR m Slew rate Phase margin Gain margin Supply current Voltage noise over a 10 Second Period Large-signal voltage follower Small-signal voltage follower Large-signal inverted pulse response Small-signal inverted pulse response Crosstalk vs Frequency vs Common-mode input voltage vs Free-air temperature vs Common-mode input voltage vs Free-air temperature vs Common-mode input voltage vs Frequency vs High-level output current vs Low-level output current vs Frequency vs Frequency vs Supply voltage vs Frequency vs Frequency vs Frequency vs Supply voltage vs Free-air temperature vs Load capacitance vs Load capacitance vs Reverse voltage 1, 2, 3 4, 6, 8 5, 7, 9 4, 6, 8 5, 7, 9 10 11, 13, 15 12, 14, 16 17 18 19 20 21 21 22 23 24 25 26 27 28, 29, 30 31 32, 33, 34 35 36
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TYPICAL CHARACTERISTICS
INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE
1400 V IO - Input Offset Voltage - V V IO - Input Offset Voltage - V 1200 1000 800 600 400 200 0 -200 -0.20 0.20 0.60 1.00 1.40 1.80 2.20 2.60 2.9 -0.1 VICR - Common-Mode Input Voltage - V VCC = 2.7 V TA = 25C 100 V IO - Input Offset Voltage - V
INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE
400 300 200 100 0 -100 -200 -300 -400 -0.2 -0.1
INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE
VCC =15 V TA = 25 C
0
-100
-200
-300 VCC = 5 V TA = 25 C
-400 -0.2 0.4 1.0 1.6 2.2 2.8 3.4 4.0 4.6 5.2 -0.1 VICR - Common-Mode Input Voltage - V
2.0
4.2
6.4
8.6
10.8 13.0 15.2
VICR - Common-Mode Input Voltage -V
Figure 1 INPUT BIAS / OFFSET CURRENT vs FREE-AIR TEMPERATURE
600 I IB / I IO - Input Bias / Offset Current - pA I IB / I IO - Input Bias / Offset Current - pA 500 400 300 200 100 0 -100 -200 -40 -25 -10 5 IIO IIB VCC = 2.7 V VIC = 1.35 V 400 350 300 250 200 150 100 50 0 -50 -100 -150 -0.2 0.2 -0.1 0.6
Figure 2 INPUT BIAS / OFFSET CURRENT vs COMMON MODE INPUT VOLTAGE
600 I IB / I IO - Input Bias / Offset Current - pA VCC = 2.7 V TA = 25 C 500 400 300 200 100 0 -100 -200 -40 -25 -10 5
Figure 3 INPUT BIAS / OFFSET CURRENT vs FREE-AIR TEMPERATURE
VCC = 5 V VIC = 2.5 V
IIO
IIO IIB
IIB
20 35 50 65 80 95 110 125
1.0
1.4
1.8
2.2
2.6 2.9
20 35 50 65 80 95 110 125
TA - Free-Air Temperature - C
VICR - Common Mode Input Voltage - V
TA - Free-Air Temperature - C
Figure 4 INPUT BIAS / OFFSET CURRENT vs COMMON-MODE INPUT VOLTAGE
I IB / I IO - Input Bias / Offset Current - pA 200 I IB / I IO - Input Bias / Offset Current - pA 150 100 50 0 -50 IIB -100 -150 -0.2 -0.1 0.4 1.0 1.6 2.2 2.8 3.4 4.0 4.6 5.2 VICR - Common Mode Input Voltage - V IIO VCC = 5 V TA = 25 C 700 600 500 400 300 200 100 0 -100 -200 -40 -25 -10 5
Figure 5 INPUT BIAS / OFFSET CURRENT vs FREE-AIR TEMPERATURE
250 VCC = 15 V VIC = 7.5 V I IB / I IO - Input Bias / Offset Current - pA 200 150 100 50
Figure 6 INPUT BIAS / OFFSET CURRENT vs COMMON-MODE INPUT VOLTAGE
VCC =15 V TA = 25 C
IIO 0 -50 -100 -150 -0.2 -0.1
IIO
IIB
IIB 20 35 50 65 80 95 110 125
2.0
4.2
6.4
8.6
10.8 13.0 15.2
TA - Free-Air Temperature - C
VICR - Common-Mode Input Voltage -V
Figure 7
Figure 8
Figure 9
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TYPICAL CHARACTERISTICS
COMMON-MODE REJECTION RATIO vs FREQUENCY
CMRR - Common-Mode Rejection Ratio - dB 120 VCC=2.7, 5, 15 V 100 RF=100 k RI=1 k 80 V OH - High-Level Output Voltage - V 2.7 VCC = 2.7 V 2.4 TA = -40C TA = -0C TA = 25 C TA = 70 C TA = 125 C VOL - Low-Level Output Voltage - V
HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT
1.50
LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT
VCC = 2.7 V 1.25 1.00 0.75 0.50 0.25 0 TA = 70 C TA = 125 C TA =25 C TA = 0 C TA = -40C
2.1
60 40
1.8
1.5
20 0 1 10 100 1k f - Frequency - Hz 10k
1.2 0 50 100 150 200 IOH - High-Level Output Current - A
0
50
100
150
200
IOL - Low-Level Output Current - A
Figure 10 HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT
5.0 VOL - Low-Level Output Voltage - V V OH - High-Level Output Voltage - V VCC = 5 V 4.5 TA = -40C 1.50 1.25 1.00 0.75 0.50 0.25 0 0 50 100 150 200 0 50
Figure 11 LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT
15.0 V OH - High-Level Output Voltage - V VCC = 5 V TA = 0 C TA = -40C
Figure 12 HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT
14.5
4.0
TA = -0C TA = 25 C TA = 70 C TA = 125 C
TA = 25 C TA = 70 C TA = 125 C
14.0
TA = -0C TA = 25 C TA = 70 C TA = 125 C TA = -40C VCC = 15 V
3.5
13.5
3.0 IOH - High-Level Output Current - A
13 100 150 200 0 50 100 150 200 IOL - Low-Level Output Current - A IOH - High-Level Output Current - A
Figure 13 LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT
VCC = 15 V 1.25 1.00 0.75 0.50 0.25 0 0 50 100 150 200 IOL - Low-Level Output Current - A TA = -40C TA = -0C TA = 25 C TA = 70 C TA = 125 C V O(PP) - Output voltage Peak-to-Peak - V 1.50 VOL - Low-Level Output Voltage - V 16 14 12 10 8 6 4 2
Figure 14 OUTPUT VOLTAGE PEAK-TO-PEAK vs FREQUENCY
10k VCC = 15 V Z o - Output Impedance - AV=10 1k
Figure 15 OUTPUT IMPEDANCE vs FREQUENCY
AV=1
VCC = 5 V VCC = 2.7 V
RL = 100 k CL = 100 pF TA = 25C
100
0 -2 10 100 f - Frequency - Hz 1k 10 100
VCC=2.7, 5, 15 V TA=25C 1k f - Frequency - Hz 10k
Figure 16
Figure 17
Figure 18
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TYPICAL CHARACTERISTICS
SUPPLY CURRENT vs SUPPLY VOLTAGE
PSRR - Power Supply Rejection Ratio - dB 1.4 I CC - Supply Current - A/Ch 1.2 1.0 0.8 0.6 0.4 0.2 0 0 2 AV = 1 VIN = VCC / 2 4 6 8 10
POWER SUPPLY REJECTION RATIO vs FREQUENCY
120 110 100 90 80 70 60 50 40 10 100 1k f - Frequency - Hz 10k VCC = 2.7, 5, & 15 V TA = 25C
TA = 125C TA = 70 C TA =25 C TA = 0 C TA = -40C
12
14
16
VCC - Supply Voltage - V
Figure 19 DIFFERENTIAL VOLTAGE GAIN AND PHASE vs FREQUENCY
AVD - Differential Voltage Gain - dB GBWP -Gain Bandwidth Product - kHz 60 50 40 30 20 10 0 -10 -20 10 100 1k f - Frequency - Hz VCC=2.7, 5, 15 V RL=500 k CL=100 pF TA=25C 0 45 90 Phase - 135 7 6 5 4 3 2 1
Figure 20 GAIN BANDWIDTH PRODUCT vs SUPPLY VOLTAGE
TA = 25C RL = 100 k CL = 100 pF f = 1kHz
-45 10k
0 2.5 4.0 5.5 7.0 8.5 10.0 11.5 13.0 14.5 16.0 VCC - Supply Voltage -V
Figure 21 SLEW RATE vs FREE-AIR TEMPERATURE
3.5 3.0 SR - Slew Rate - V/ ms 2.5 2.0 1.5 1.0 0.5 0 -40 -25 -10 5 SR- VCC = 2.7, 5, 15 V VCC = 5, 15 V VCC = 2.7 V Phase Margin - SR+ 80 70 60 50 40 30 20 10 0 20 35 50 65 80 95 110 125 10
Figure 22 PHASE MARGIN vs CAPACITIVE LOAD
VCC = 2.7, 5, & 15 V RL= 500 k TA = 25C
TA - Free-Air Temperature - C
100 1k CL - Capacitive Load - pF
10k
Figure 23
Figure 24
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TYPICAL CHARACTERISTICS
GAIN MARGIN vs CAPACITIVE LOAD
25 RL= 500 k TA = 25C I CC - Supply Current - nA 20 Gain Margin - dB VCC = 15 V 60 55 50 45 40 35 30 25 20 15 10 5 0 10 100 1k CL - Capacitive Load - pF 10k 0 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 TA = 25C
SUPPLY CURRENT vs REVERSE VOLTAGE
15
10 VCC = 2.7, 5 V 5
VCC - Reverse Voltage - V
Figure 25
Figure 26
4 Input Referred Voltage Noise - V 3 2 1 0 -1 -2 -3 -4 0
VOLTAGE NOISE OVER A 10 SECOND PERIOD
VCC = 5 V f = 0.1 Hz to 10 Hz TA = 25C V - Output Voltage - V O
LARGE SIGNAL FOLLOWER PULSE RESPONSE
5 4 3 2 1 0 -1 VCC = 2.7 V AV = 1 RL = 100 k CL = 100 pF TA = 25C 2
VIN
1 0 -1 V IN - Input Voltage - V V IN 8 10 12 14 16 - Input Voltage - V
VO
1
2
3
4
5
6
7
8
9
10
-1
0
1
2
3
4
5
6
t - Time - s
t - Time - ms
Figure 27 LARGE SIGNAL FOLLOWER PULSE RESPONSE
8 7 6 V - Output Voltage - V O 5 4 3 2 1 0 -1 -1 0 1 2 3 4 5 6 t - Time - ms VO VIN VCC = 5 V AV = 1 RL = 100 k CL = 100 pF TA = 25C 4 3 2 - Input Voltage - V 1 0 -1 V - Output Voltage - V O 30 25
Figure 28 LARGE SIGNAL FOLLOWER PULSE RESPONSE
15 VCC = 15 V AV = 1 RL = 100 k CL = 100 pF TA = 25C 10 5 0 -5 VO
VIN 20 15 10 5 0 -5 -2 0 2 4 6 t - Time - ms
Figure 29
V
IN
Figure 30
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TYPICAL CHARACTERISTICS
SMALL SIGNAL FOLLOWER PULSE RESPONSE
180 160 V - Output Voltage - mV O 140 120 100 80 60 40 20 0 -20 -50 0 50 100 150 200 250 300 350 400 450 500 t - Time - s VO VCC = 2.7, 5, & 15 V AV = 1 RL = 100 k CL = 100 pF TA = 25C VIN 300 150 V IN - Input Voltage - mV V - Output Voltage - V O 0 -150 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2 -1 0 1 2 3 4 5 6 7 t - Time - ms VO VCC = 2.7 V AV = -1 RL = 100 k CL = 100 pF TA = 25C VIN
LARGE SIGNAL INVERTING PULSE RESPONSE
3 2 - Input Voltage - V V V -8 -10 -12 VO -5 0 5 10 15 20 25 30 35 t - Time - ms IN - Input Voltage - V IN 1 0 -1
Figure 31
Figure 32
LARGE SIGNAL INVERTING PULSE RESPONSE
2.5 2.0 1.5 V - Output Voltage - V O 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -1 0 1 2 3 4 5 6 7 t - Time - ms VO VCC = 5 V AV = -1 RL = 100 k CL = 100 pF TA = 25C VIN 4 3 2 V - Output Voltage - V O - Input Voltage - V 1 0 -1 12 10 8 6 4 2 0 -2 -4 -6
LARGE SIGNAL INVERTING PULSE RESPONSE
12 9 VIN 6 3 VCC = 15 V AV = -1 RL = 100 k CL = 100 pF TA = 25C 0 -3
Figure 33
V
IN
Figure 34 CROSSTALK vs FREQUENCY
200 0 -20 - Input Voltage - mV -40 Crosstalk -dB -60 -80 -100 -120 -140 VCC = 2.7, 5 V VCC = 2.7, 5, & 15 V All Channels RL = 100 k CL = 100 pF VIN = 1 VPP
SMALL SIGNAL INVERTING PULSE RESPONSE
200 VIN 150 VO - Output Voltage - mV 100 50 0 -50 VO -100 -150 -200 VCC = 2.7, 5, & 15 V AV = -1 RL = 100 k CL = 100 pF TA = 25C 100 0 -100
VCC = 15 V
0
200
400
600
800 1000 1200
V
IN
10
t - Time - ms
100 1k f - Frequency -Hz
10k
Figure 35
Figure 36
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TLV2401, TLV2402, TLV2404 FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION
SLOS244A - FEBRUARY 2000 - REVISED JUNE 2000
APPLICATION INFORMATION reverse battery protection
The TLV2401/2/4 are protected against reverse battery voltage up to 18 V. When subjected to reverse battery condition the supply current is typically less than 100 nA at 25C (inputs grounded and outputs open). This current is determined by the leakage of 6 Schottky diodes and will therefore increase as the ambient temperature increases. When subjected to reverse battery conditions and negative voltages applied to the inputs or outputs, the input ESD structure will turn on--this current should be limited to less than 10 mA. If the inputs or outputs are referred to ground, rather than midrail, no extra precautions need be taken.
common-mode input range
The TLV2401/2/4 has rail-rail input and outputs. For common-mode inputs from -0.1 V to VCC - 0.8 V a PNP differential pair will provide the gain. For inputs between VCC - 0.8 V and VCC, two NPN emitter followers buffering a second PNP differential pair provide the gain. This special combination of NPN/PNP differential pair enables the inputs to be taken 5 V above the rails; because as the inputs go above VCC, the NPNs switch from functioning as transistors to functioning as diodes. This will lead to an increase in input bias current. The second PNP differential pair continues to function normally as the inputs exceed VCC. The TLV2401/2/4 has a negative common-input range that exceeds ground by 100 mV. If the inputs are taken much below this, reduced open loop gain will be observed with the ultimate possibility of phase inversion.
offset voltage
The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage:
RF RG IIB-
+ VI RS IIB+ V
- +
VO
OO
+ VIO 1 )
R R
F
G
" IIB) RS
1
)
R R
F
G
" IIB- RF
Figure 37. Output Offset Voltage Model
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APPLICATION INFORMATION general configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (see Figure 38).
RG RF
- VI + R1 C1 f V R + 1 ) RF -3dB VO 1 + 2pR1C1
O V I
G
1
) sR1C1
1
Figure 38. Single-Pole Low-Pass Filter If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth. Failure to do this can result in phase shift of the amplifier.
C1 R1 = R2 = R C1 = C2 = C Q = Peaking Factor (Butterworth Q = 0.707) f -3dB 1 + 2pRC RF 1 2- Q
VI R1 R2 C2
+ _
RG
RF
RG =
(
)
Figure 39. 2-Pole Low-Pass Sallen-Key Filter
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APPLICATION INFORMATION circuit layout considerations
To achieve the levels of high performance of the TLV240x, follow proper printed-circuit board design techniques. A general set of guidelines is given in the following.
D D
Ground planes - It is highly recommended that a ground plane be used on the board to provide all components with a low inductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane can be removed to minimize the stray capacitance. Proper power supply decoupling - Use a 6.8-F tantalum capacitor in parallel with a 0.1-F ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the application, but a 0.1-F ceramic capacitor should always be used on the supply terminal of every amplifier. In addition, the 0.1-F capacitor should be placed as close as possible to the supply terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less effective. The designer should strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors. Sockets - Sockets can be used but are not recommended. The additional lead inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board is the best implementation. Short trace runs/compact part placements - Optimum high performance is achieved when stray series inductance has been minimized. To realize this, the circuit layout should be made as compact as possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at the input of the amplifier. Surface-mount passive components - Using surface-mount passive components is recommended for high performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept as short as possible.
D D
D
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APPLICATION INFORMATION general power dissipation considerations
For a given JA, the maximum power dissipation is shown in Figure 40 and is calculated by the following formula: P Where:
+ D
T
-T MAX A
q JA
PD = Maximum power dissipation of THS240x IC (watts) TMAX = Absolute maximum junction temperature (150C) TA = Free-ambient air temperature (C) JA = JC + CA JC = Thermal coefficient from junction to case CA = Thermal coefficient from case to ambient air (C/W)
MAXIMUM POWER DISSIPATION vs FREE-AIR TEMPERATURE
2 1.75 Maximum Power Dissipation - W 1.5 1.25 1 0.75 0.5 0.25
SOT-23 Package Low-K Test PCB JA = 324C/W SOIC Package Low-K Test PCB JA = 176C/W PDIP Package Low-K Test PCB JA = 104C/W TJ = 150C
MSOP Package Low-K Test PCB JA = 260C/W
0 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 TA - Free-Air Temperature - C NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.
Figure 40. Maximum Power Dissipation vs Free-Air Temperature
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APPLICATION INFORMATION macromodel information
Macromodel information provided was derived using Microsim PartsTM Release 8, the model generation software used with Microsim PSpiceTM. The Boyle macromodel (see Note 2) and subcircuit in Figure 41 are generated using the TLV240x typical electrical and operating characteristics at TA = 25C. Using this information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):
D D D D D D
Maximum positive output voltage swing Maximum negative output voltage swing Slew rate Quiescent power dissipation Input bias current Open-loop voltage amplification
D D D D D D
Unity-gain frequency Common-mode rejection ratio Phase margin DC output resistance AC output resistance Short-circuit output current limit
NOTE 2: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, "Macromodeling of Integrated Circuit Operational Amplifiers", IEEE Journal of Solid-State Circuits, SC-9, 353 (1974). 3 99 VCC+ + egnd ree ro2 cee fb rp rc1 rc2 - c1 7 11 12 + 1 c2 vlim IN+ r2 + 9 6 - vc 2 8 + q1 q2 IN- - vb ga - ro1 gcm ioff 53 dp 13 14 re1 10 iee VCC- 4 - + 54 dc re2 91 + vlp - ve de rc1 rc2 re1 re2 ree ro1 ro2 rp vb vc ve vlim vlp vln .model .model .model .model .ends 3 3 13 14 10 8 7 3 9 3 54 7 91 0 dx dy qx1 qx2 11 978.81E3 12 978.81E3 10 30.364E3 10 30.364E3 99 3.6670E9 5 10 99 10 4 1.4183E6 0 dc 0 53 dc .88315 4 dc .88315 8 dc 0 0 dc 540 92 dc 540 D(Is=800.00E-18) D(Is=800.00E-18 Rs=1m Cjo=10p) NPN(Is=800.00E-18 Bf=27.270E21) NPN(Is=800.0000E-18 Bf=27.270E21) - VOUT dlp 90 + hlim + dln 92 - vln 5
.subckt 240X_5V-X 1 2 3 4 5 * c1 11 12 9.8944E-12 c2 6 7 30.000E-12 cee 10 99 8.8738E-12 dc 5 53 dy de 54 5 dy dlp 90 91 dx dln 92 90 dx dp 4 3 dx egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5 fb 7 99 poly(5) vb vc ve vlp vln 0 61.404E6 -1E3 1E3 61E6 -61E6 ga 6 0 11 12 1.0216E-6 gcm 0 6 10 99 10.216E-12 iee 10 4 dc 54.540E-9 ioff 0 6 dc 5e-12 hlim 90 0 vlim 1K q1 11 2 13 qx1 q2 12 1 14 qx2 r2 6 9 100.00E3
Figure 41. Boyle Macromodels and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
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MECHANICAL DATA
D (R-PDSO-G**)
14 PIN SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) 0.010 (0,25) M
Gage Plane
0.010 (0,25) 1 A 7 0- 8 0.044 (1,12) 0.016 (0,40)
Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.004 (0,10)
PINS ** DIM A MAX
8 0.197 (5,00) 0.189 (4,80)
14 0.344 (8,75) 0.337 (8,55)
16 0.394 (10,00) 0.386 (9,80) 4040047 / D 10/96
A MIN
NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
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MECHANICAL INFORMATION
DBV (R-PDSO-G5)
0,40 0,20 5 4
PLASTIC SMALL-OUTLINE PACKAGE
0,95
0,25 M
1,80 1,50
3,00 2,50
0,15 NOM
1 3,10 2,70
3
Gage Plane
0,25 0- 8 0,55 0,35
Seating Plane 1,30 1,00 0,05 MIN 0,10
4073253-4/B 10/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions include mold flash or protrusion.
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MECHANICAL INFORMATION
DGK (R-PDSO-G8)
0,38 0,25 8 5
PLASTIC SMALL-OUTLINE PACKAGE
0,65
0,25 M
0,15 NOM 3,05 2,95 4,98 4,78
Gage Plane 0,25 1 3,05 2,95 4 0- 6 0,69 0,41
Seating Plane 1,07 MAX 0,15 0,05 0,10
4073329/B 04/98 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-187
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MECHANICAL INFORMATION
N (R-PDIP-T**)
16 PIN SHOWN PINS ** DIM A 16 9 A MAX
PLASTIC DUAL-IN-LINE PACKAGE
14 0.775 (19,69) 0.745 (18,92)
16 0.775 (19,69) 0.745 (18,92)
18 0.920 (23.37) 0.850 (21.59)
20 0.975 (24,77) 0.940 (23,88)
A MIN
0.260 (6,60) 0.240 (6,10)
1
8 0.070 (1,78) MAX
0.035 (0,89) MAX
0.020 (0,51) MIN
0.310 (7,87) 0.290 (7,37)
0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN
0.100 (2,54) 0.021 (0,53) 0.015 (0,38)
0- 15 0.010 (0,25) NOM
0.010 (0,25) M
14/18 PIN ONLY 4040049/C 08/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001.)
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MECHANICAL INFORMATION
P (R-PDIP-T8)
0.400 (10,60) 0.355 (9,02) 8 5
PLASTIC DUAL-IN-LINE PACKAGE
0.260 (6,60) 0.240 (6,10)
1
4 0.070 (1,78) MAX 0.020 (0,51) MIN 0.310 (7,87) 0.290 (7,37)
0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN
0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M 0.010 (0,25) NOM
0- 15
4040082 / B 03/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001
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MECHANICAL INFORMATION
PW (R-PDSO-G**)
14 PINS SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0,65 14 8
0,30 0,19
0,10 M
0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 A 7 0- 8 0,75 0,50
Seating Plane 1,20 MAX 0,15 0,05 0,10
PINS ** DIM A MAX
8
14
16
20
24
28
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153
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Copyright (c) 2000, Texas Instruments Incorporated

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