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SN65LVDS96 LVDS SERDES RECEIVER
SLLS296F - MAY 1998 - REVISED FEBRUARY 2000
D D D D D D D D D D D D D D
3:21 Data Channel Expansion at up to 1.3 Gigabits per Second Throughput Suited for Point-to-Point Subsystem Communication With Very Low EMI 3 Data Channels and Clock Low-Voltage Differential Channels in and 21 Data and Clock Low-Voltage TTL Channels Out Operates From a Single 3.3-V Supply and 250 mW (Typ) 5-V Tolerant SHTDN Input Rising Clock Edge Triggered Outputs Bus Pins Tolerate 4-kV HBM ESD Packaged in Thin Shrink Small-Outline Package With 20 Mil Terminal Pitch Consumes <1 mW When Disabled Wide Phase-Lock Input Frequency Range 20 MHz to 67 MHz No External Components Required for PLL Inputs Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard Industrial Temperature Qualified TA = - 40C to 85C Replacement for the DS90CR216
DGG PACKAGE (TOP VIEW)
D17 D18 GND D19 D20 NC LVDSGND A0M A0P A1M A1P LVDSVCC LVDSGND A2M A2P CLKINM CLKINP LVDSGND PLLGND PLLVCC PLLGND SHTDN CLKOUT D0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
VCC D16 D15 D14 GND D13 VCC D12 D11 D10 GND D9 VCC D8 D7 D6 GND D5 D4 D3 VCC D2 D1 GND
description
The SN65LVDS96 LVDS serdes (serializer/deserializer) receiver contains three serial-in 7-bit parallel-out shift registers, a 7x clock synthesizer, and four low-voltage differential signaling (LVDS) line receivers in a single integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such as the SN65LVDS95, over four balanced-pair conductors and expansion to 21 bits of single-ended LVTTL synchronous data at a lower transfer rate. When receiving, the high-speed LVDS data is received and loaded into registers at the rate of seven times the LVDS input clock (CLKIN). The data is then unloaded to a 21-bit wide LVTTL parallel bus at the CLKIN rate. A phase-locked loop clock synthesizer circuit generates a 7x clock for internal clocking and an output clock for the expanded data. The SN65LVDS96 presents valid data on the rising edge of the output clock (CLKOUT). The SN65LVDS96 requires only four line termination resistors for the differential inputs and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with data transmission transparent to the user(s). The only user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low level on this signal clears all internal registers to a low level. The SN65LVDS96 is characterized for operation over ambient air temperatures of - 40C to 85C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2000, Texas Instruments Incorporated
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1
SN65LVDS96 LVDS SERDES RECEIVER
SLLS296F - MAY 1998 - REVISED FEBRUARY 2000
functional block diagram
Serial-In/Parallel-Out Shift Register A0P Serial In A0M CLK A,B, ...G D0 D1 D2 D3 D4 D5 D6
Serial-In/Parallel-Out Shift Register A1P Serial In A1M CLK A,B, ...G
Serial-In/Parallel-Out Shift Register A2P Serial In A2M CLK A,B, ...G
D7 D8 D9 D10 D11 D12 D13
Control Logic SHTDN
D14 D15 D16 D17 D18 D19 D20
7x Clock/PLL CLK CLKINP Clock In CLKINM Clock Out CLKOUT
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SN65LVDS96 LVDS SERDES RECEIVER
SLLS296F - MAY 1998 - REVISED FEBRUARY 2000
CLKIN
Previous Cycle A0
D0-1 D6 D5
Current Cycle
D4 D3 D2 D1 D0 D6+1
Next Cycle
A1
D7-1
D13
D12
D11
D10
D9
D8
D7
D13+1
A2
D14-1
D20
D19
D18
D17
D16
D15
D14
D20+1
CLKOUT
Dn
Dn-1
Dn
Dn+1
Figure 1. Typical 'LVDS96 Load and Shift Sequences
equivalent input and output schematic diagrams
VCC VCC VCC
300 k
300 k SHTDN
50
5 D Output
AnP
AnM 7V
7V 7V 7V 300 k
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SN65LVDS96 LVDS SERDES RECEIVER
SLLS296F - MAY 1998 - REVISED FEBRUARY 2000
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4 V Voltage range at any terminal (except SHTDN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Voltage range at SHTDN terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 5.5 V Electrostatic discharge (see Note 2): Bus pins (Class 3A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 KV Bus pins (Class 2B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 V All pins (Class 3A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 KV All pins (Class 2B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (see Dissipation Rating Table) Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 85C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to the GND terminals unless otherwise noted. 2. This rating is measured using MIL-STD-883C Method, 3015.7. DISSIPATION RATING TABLE PACKAGE TA 25C POWER RATING DERATING FACTOR ABOVE TA = 25C TA = 70C POWER RATING TA = 85C POWER RATING
DGG 1316 mW 13.1 mW/C 724 mW 526 mW This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
recommended operating conditions
MIN Supply voltage, VCC High-level input voltage, VIH Low-level input voltage, VIL Magnitude of differential input voltage, |VID| V Common-mode input voltage, VIC Operating free-air temperature, TA SHTDN SHTDN 0.1 ID 2 - 40 2.4 3 2 0.8 0.6 ID 2 VCC-0.8 85 V NOM 3.3 MAX 3.6 UNIT V V V V
V C
timing requirements
PARAMETERS tc Input clock period tc is defined as the mean duration of a minimum of 32,000 clock periods. MIN 15.4 NOM tc MAX 50 UNIT ns
4
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SN65LVDS96 LVDS SERDES RECEIVER
SLLS296F - MAY 1998 - REVISED FEBRUARY 2000
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER VIT+ VIT- VOH VOL Positive-going differential Input voltage threshold Negative-going differential Input voltage threshold High-level output voltage Low-level output voltage IOH = -4 mA IOH = 4 mA Disabled, all inputs open Enabled, AnP at 1 V and AnM at 1.4 V, tc = 15.38 ns Enabled, CL = 8 pF, Worst-case pattern (see Figure 4), tc = 15.38 ns VIH = VCC VIL = 0 V 0 V VI 2.4 V 60 -100 2.4 0.4 280 82 mA 94 20 20 A A TEST CONDITIONS MIN TYP MAX 100 UNIT mV mV V V A
ICC
Quiescent current (average)
IIH IIL
High-level input current (SHTDN) Low-level input current (SHTDN)
IIN Input current (A inputs) 20 A IOZ High-impedance output current VO = 0 V to VCC 10 A All typical values are VCC = 3.3 V, TA = 25C. The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for the negative-going input voltage threshold only.
switching characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER tsu th tRSKM td Data setup time, D0 through D20 to CLKOUT Data hold time, CLKOUT to D0 through D20 Receiver in ut skew margin input (see Figure 7) Delay time, input clock to output clock (see Figure 7) out ut eriod Change in output clock period from cycle to cycle# Enable time, SHTDN to phase lock Disable time, SHTDN to Off state TEST CONDITIONS MIN 4 CL = 8 pF pF, See Figure 5 4 tc = 15.38 ns ( (0.2%), ), |Input clock jitter| <50 ps tc = 15.38 ns (0.2%) tc = 15.38 + 0.75 sin (2500E3t) 0.05 ns, See Figure 7 tc = 15.38 + 0.75 sin (23E6t) 0.05 ns, See Figure 7 See Figure 8 See FIgure 9 TA = 0C to 85C TA = - 40C to 0C 490 350 3.7 80 ps 300 1 400 ms ns 6 800 ps ps ns TYP 6 ns MAX UNIT
tC(O)
ten tdis
tt Output transition time (10% to 90% tr or tf) CL = 8 pF 3 ns tw Output clock pulse duration 0.43 tc ns tRSKM is the timing margin available to allocate to the transmitter and interconnection skews and clock jitter. The value of this parameter at clock periods other than 15.38 ns can be calculated from tc -600 ps. 14 |Input clock jitter| is the magnitude of the change in the input clock period. # tC(O) is the change in the output clock period from one cycle to the next cycle observed over 15,000 cycles.
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SN65LVDS96 LVDS SERDES RECEIVER
SLLS296F - MAY 1998 - REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
AP VID (VIAP + VIAM)/2 VIAP VIAM
AM
VIC
Figure 2. Voltage Definitions
COMMON-MODE INPUT VOLTAGE vs DIFFERENTIAL INPUT VOLTAGE AND VCC
2.5 MAX at >3.15 V VIC - Common-Mode Input Voltage - V MAX at 3 V
2
1.5
1
0.5 MIN 0 0 0.1 0.2 0.3 0.4 0.5 0.6 |VID|- Differential Input Voltage and VCC - V
Figure 3. Maximum VIC versus VID and VCC
6
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SN65LVDS96 LVDS SERDES RECEIVER
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PARAMETER MEASUREMENT INFORMATION
T CLKIN/ CLKOUT EVEN Dn ODD Dn
Figure 4. Worst-Case Test Pattern
The worst-case test pattern produces nearly the maximum switching frequency for all of the LV-TTL outputs.
tsu VOH 2.4 V D0-27 0.4 V VOL th VOH 2.4 V CLKOUT 0.4 V VOL
Figure 5. Setup and Hold-Time Measurements
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SN65LVDS96 LVDS SERDES RECEIVER
SLLS296F - MAY 1998 - REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
Tektronix HFS9003/HFS9DG1 Stimulus System (Repeating Patterns 1110111 and 0001000) An DUT D0-D20 Tektronix Microwave Logic Multi-BERT-100RX Word Error Detector
CLKIN
CLKOUT
NOTES: A. CLKIN is advanced or delayed with respect to data until errors are observed at the receiver outputs. B. The advance or delay is then reduced until there are no data errors observed. C. The magnitude of the advance or delay from step 2 is tRSKM.
tc 4/7 tc tRSKM 3/7 tc tRSKM An and An ts th
CLKIN 7xCLK (Internal) td tw CLKOUT tr < 1 ns 90% CLKIN or An -300 mV 10% td tw CLKOUT VOH 1.4 V VOL 300 mV 0V
Figure 6. Receiver Input Skew Margin, Setup/Hold Time, and td Definitions
8
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PARAMETER MEASUREMENT INFORMATION
+ Device Under Test
Reference
+
VCO
Modulation v(t) = A sin(2fmodt) HP8656B Signal Generator, 0.1 MHz-990 MHz RF Output HP8665A Synthesized Signal Generator, 0.1 MHz-4200 MHz Modulation Input Output Device Under Test DTS2070C Digital Time Scope Input
CLKIN
CLKOUT
Figure 7. Output Clock Jitter Test Setup
CLKIN
An ten SHTDN
Dn
Invalid
Valid
Figure 8. Enable Time Waveforms
CLKIN tdis SHTDN CLKOUT
Figure 9. Disable Time Waveforms
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SN65LVDS96 LVDS SERDES RECEIVER
SLLS296F - MAY 1998 - REVISED FEBRUARY 2000
TYPICAL CHARACTERISTICS
WORST-CASE SUPPLY CURRENT vs FREQUENCY
120
100 I CC - Supply Current - mA VCC = 3.6 V 80 VCC = 3.3 V
60
VCC = 3 V
40
10
AA AA
20
0 30
40
50 60 f - Frequency - MHz
70
Figure 10
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SN65LVDS96 LVDS SERDES RECEIVER
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APPLICATION INFORMATION 16-bit bus extension
In a 16-bit bus application (Figure 11), TTL data and clock coming from bus transceivers that interface the backplane bus arrive at the Tx parallel inputs of the LVDS serdes transmitter. The clock associated with the bus is also connected to the device. The on-chip PLL synchronizes this clock with the parallel data at the input. The data is then multiplexed into three different line drivers which perform the TTL to LVDS conversion. The clock is also converted to LVDS and presented to a separate driver. This synchronized LVDS data and clock at the receiver, which recovers the LVDS data and clock, performs a conversion back to TTL. Data is then demultiplexed into a parallel format. An on-chip PLL synchronizes the received clock with the parallel data, and then all are presented to the parallel output port of the receiver.
16-Bit BTL Bus Interface TTL Interface LVDS Interface 0 To 10 Meters (Media Dependent) SN65LVDS95 SN65LVDS96 TTL Interface 16-Bit BTL Bus Interface
SN74FB2032
D0-D7 8
8
D0-D7
SN74FB2032
SN74FB2032
D8-D15 8
8 D8-D15 SN74FB2032
CLK Backplane Bus
XMIT Clock
RCV Clock
CLK Backplane Bus
Figure 11. 16-Bit Bus Extension
16-bit bus extension with parity
In the previous application we did not have a checking bit that would provide assurance that the data crosses the link. If we add a parity bit to the previous example, we would have a diagram similar to the one in Figure 12. The device following the SN74FB2032 is a low cost parity generator. Each transmit-side transceiver/parity generator takes the LVTTL data from the corresponding transceiver, performs a parity calculation over the byte, and then passes the bits with its calculated parity value on the parallel input of the LVDS serdes transmitter. Again, the on-chip PLL synchronizes this transmit clock with the eighteen parallel bits (16 data + 2 parity) at the input. The synchronized LVDS data/parity and clock arrive at the receiver. The receiver performs the conversion from LVDS to LVTTL and the transceiver/parity generator performs the parity calculations. These devices compare their corresponding input bytes with the value received on the parity bit. The transceiver/parity generator will assert its parity error output if a mismatch is detected.
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SN65LVDS96 LVDS SERDES RECEIVER
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APPLICATION INFORMATION
16-Bit BTL Bus Interface TTL Interface W/Parity LVDS Interface 0 To 10 Meters (Media Dependent) SN65LVDS95 D0-D7 9 Bit Latchable Transceiver/ With Parity Generator 8 Parity SN65LVDS96 8 Parity 9 Bit Latchable Transceiver/ With Parity Generator D0-D7 TTL Interface W/Parity 16-Bit BTL Bus Interface
TTL Interface
TTL Interface
SN74FB2032
SN74FB2032
D8-D15 SN74FB2032 9 Bit Latchable Transceiver/ With Parity Generator
8 Parity
8 Parity 9 Bit Latchable Transceiver/ With Parity Generator
D8-D15 SN74FB2032
Parity Error CLK Backplane Bus XMIT Clock RCV Clock CLK Backplane Bus
Figure 12. 16-Bit Bus Extension With Parity
low cost virtual backplane transceiver
Figure 13 represents LVDS serdes in an application as a virtual backplane transceiver (VBT). The concept of a VBT can be achieved by implementing individual LVDS serdes chipsets in both directions of subsystem serialized links. Depending on the application, the designer will face varying choices when implementing a VBT. In addition to the devices shown in Figure 13, functions such as parity and delay lines for control signals could be included. Using additional circuitry, half-duplex or full-duplex operation can be achieved by configuring the clock and control lines properly. The designer may choose to implement an independent clock oscillator at each end of the link and then use a PLL to synchronize LVDS serdes's parallel I/O to the backplane bus. Resynchronizing FIFOs may also be required.
Bus Transceivers Backplane Bus Bus Transceivers TTL Inputs Up To 21 or 28 Bits LVDS Serdes Transmitter LVDS Serdes Transmitter LVDS Serial Links 4 or 5 Pairs LVDS Serdes Receiver LVDS Serdes Receiver TTL Outputs Up To 21 or 28 Bits Bus Transceivers Bus Transceivers Backplane Bus
Figure 13. Virtual Backplane Transceiver
12
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SN65LVDS96 LVDS SERDES RECEIVER
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MECHANICAL DATA
DGG (R-PDSO-G**)
48 PIN SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0,50 48
0,27 0,17 25
0,08 M
6,20 6,00
8,30 7,90
0,15 NOM
Gage Plane 0,25 0- 8 A 0,75 0,50
1
24
Seating Plane 1,20 MAX 0,15 0,05 0,10
PINS ** DIM A MAX
48
56
64
12,60
14,10
17,10
A MIN
12,40
13,90
16,90 4040078 / F 12/97
NOTES: A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. Falls within JEDEC MO-153
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Copyright (c) 2000, Texas Instruments Incorporated

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