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| Features * Comprehensive Library of Standard Logic Cells * MH2RT I/O Cells Designed to Operate With VDD 2.5V + 0.2V as Main Target Operating * * * * * * * * * * * * * * * Conditions IO33 Pad Library Provides Interface to 3.3V Environment Memory Cells Compiled to Precise Design Requirements Processed on Radiation Hard 0.25 m CMOS Process, 5 Metal Layers Cold Sparing Buffers Pre-defined Pads Frames SEU Free Cells Latch-up Immune 200 Krads Total Dose LVDS, LVTTL, PCI, PECL Buffers 75 m Buffer Pitch Allowing up to 750 pads High Speed: <100 ps Typical Propagation Gate Delay (NAND2 with FO = 2) Integration Capability With up to 5 Mgates Up to 2.25-Mbit Memory Compiler MQFP Package With Pin Count up to 352 CLGA Packages With 1.25 mm and 1 mm Column Pitches and Pin Count up to 613 Rad. Hard 5M Gates 0.25 m CMOS Cell-based MH2RT Advance Information Description The Atmel MH2RT cell-based ASIC series are fabricated on a 0.25 micron CMOS process, with up to five levels of metal. This family allows up to 5 million gates and 800 pads. The high density and high pin count capabilities of the MH2RT family, coupled with the ability to embed processor cores or memories on the same silicon, make the MH2RT series an ideal choice for System Level Integration. The MH2RT series is supported by an advanced software environment based on industry standards linking proprietary and commercial tools. Verilog(R), DFT, Synopsys(R) and Vital are the reference front-end tools. The CadenceTM "Logic Design Planner" floor planning associated with timing driven layout provides an efficient back-end cycle. The MH2RT series comes as a dual use of the MH2 series adding: - through process changes, the 100 MeV latch up immunity and the 200 Krads+ total dose capability as required by most of the space programs, - through cells layout, an SEU immunity allowing to SEU harden only where it is actually necessary with respect to function requirements. The MH2RT series comes as the Atmel 8th generation of ASIC series designed for radiation hardened applications in 19 years. It will be made available to any of the currently available quality grades, including QML Q and V. The Atmel MH2RT family is fabricated on a proprietary 0.25 micron five-layer-metal CMOS process intended for use with a supply voltage of 2.5V 0.2V. The MH2RT Series is offered with a mutli-project wafer service. Rev. 4142B-AERO-06/02 1 The following table shows the range for which Atmel library cells have been characterized. Table 1. Recommended Operating Conditions Symbol VDD VDD3 VI VO TEMP Parameter DC Supply Voltage DC Supply Voltage DC Input Voltage DC Output Voltage Operating Free Air Temperature Range Military Conditions Core and Standard I/Os 3V Interface I/Os Min 2.3 3 0 0 -55 Typ 2.5 3.3 Max 2.7 3.6 VDD VDD +125 Unit V V V V C The Atmel cell libraries and megacell compilers have been designed to be compatible with each other. Simulation representations exist for three types of operating conditions. They correspond to three characterization conditions defined as follows: * MIN conditions: TJ = -55C VDD (cell) = 2.7V Process = fast (military best case) * TYP conditions: TJ = +25C VDD (cell) = 2.5V Process = typ (military typical case) * MAX conditions: TJ = +125C VDD (cell) = 2.3V Process = slow (military worst case) Delays to tri-state are defined as delays to turn off (VGS < VT) the driving devices. Output pad drain current corresponds to the output current of the pad when the output voltage is VOL or VOH. The output resistor of the pad and the voltage drop due to access resistors (in and out of the die) are taken into account. In order to have accurate timing estimates, all characterization has been run on electrical netlists extracted from the layout database. 2 MH2RT 4142B-AERO-06/02 MH2RT Standard Cell Library The Atmel Standard Cell Library, contains a comprehensive set of combinational logic and storage cells. The library includes cells which belong to the following categories: * * * * * * Buffers and Gates Multiplexers Flip-flops Scan Flip-flops Latches Adders and Subtractors Decoding the Cell Name The table below shows the naming conventions for the cells in the library. Each cell name begins with either a two-, three-, or four-letter code that defines the type of cell. This indicates the range of standard cells available. Table 2. Cell Codes Code AD AH AS AN AOI AON AOR BH BUFB BUFF BUFT CG CLK2 DE DF INV0 INVB Description Adder Half Adder Adder/Subtractor AND Gate AND-OR-Invert Gate AND-OR-AND-Invert Gates AND-OR Gate Bus Holder Balanced Buffer Non-Inverting Buffer Non-Inverting 3-State Buffer Carry Generator Clock Buffer D-Enabled Flip-Flop D Flip-Flop Inverter Balanced Inverter Code INVT JK LA MI MX ND NR OAI OAN OR ORA SD SE SRLA SU XN XR Description Inverting 3-State Buffer JK Flip-Flop D Latch Inverting Multiplexer Multiplexer NAND Gate NOR Gate OR-AND-Invert Gate OR-AND-OR-Invert Gates OR Gate OR-AND Gate Multiplexed Scan D Flip-Flop Multiplexed Scan Enable D Flip-Flop Set/Reset Latches with NAND input Subtractor Exclusive NOR Gate Exclusive OR Gate 3 4142B-AERO-06/02 Cell Matrices The following three tables provide a quick reference to the storage elements in the library. Note that all storage elements feature buffered clock inputs and buffered output. Table 3. JK Flip-flops Macro Name JKBRBx Set * Clear * 1x Drive * 2 x Drive * Table 4. D Flip-flops Macro Name DFBRBx DFCRBx DFCRQx DFCRNx DFNRBx DFNRQx DFPRBx DEPRQx DENRQx DENRBx DECRQx * * * * * * * Set * Clear * * * * Enabled D Input 1 x Drive * * * * * * * * * * * 2 x Drive * * * * * * * * * * * * * * * * Single Output Table 5. Scan Flip-flops Macro Name SDBRBx SDCRBx SDCRNx SDCRQx SDNRBx SDNRNx SDNRQx SDPRBx SECRQx SENRQx SEPRQx * * * Set * Clear * * * * 1x Drive * * * * * * * * * * * 2x Drive * * * * * * * * * * * * * * * * * * Single Output 4 MH2RT 4142B-AERO-06/02 MH2RT Input/Output Pad Cell Libraries IO25lib and IO33lib Voltage Levels The Atmel Input/Output Cell Library, IO25lib, contains a comprehensive list of input, output, bi-directional and tri-state cells. The MH2RT (2.5V) cell library includes a special set of I/O cells, IO33lib, for interfacing with external 3.3V devices. The IO25lib library is made up exclusively of low-voltage chip interface circuits powered by a voltage in the range of 2.3V to 2.7V. The library is compatible with the 2.5V standard cells library. Designers are strongly encouraged to provide three kinds of power pairs for the IO25lib library. These are "AC", "DC" and core power pairs. AC power is used by the I/O to switch its output from one state to the other. This switching generates noise in the AC power buses on the chip. DC power is used by the I/O to maintain its output in a steady state. The best noise performance is achieved when the DC power buses on the chip are free of noise; designers are encouraged to use separate power pairs for AC and DC power to prevent most of the noise in the AC power buses from reaching the DC power buses. The same power pairs can be used to supply both DC power to the I/Os and power to the core without affecting noise performance. Power and Ground Pads Table 6. VSS Power Pad Combinations Core Vssi * * * * * * * * * * Switching I/O VssAC Quiet I/O VssDC Library Cell Name pv25i00 pv25a00 pv25d00 pv25e00 pv25b00 pv25f00 Signal Name VSS VSS VSS VSS VSS VSS Table 7. VDD Power Pad Combinations Core Vddi * * * * * * * * * * Switching I/O VddAC Quiet I/O VddDC Library Cell Name pv25i25 pv25a25 pv25d25 pv25e25 pv25b25 pv25f25 Signal Name VDD VDD VDD VDD VDD VDD 5 4142B-AERO-06/02 Cell Matrices Table 8. CMOS Pads CMOS Cell Name PC25B01 PC25B02 PC25B03 PC25B04 PC25B05 PC25O01 PC25O02 PC25O03 PC25O04 PC25O05 PC25T01 PC25T02 PC25T03 PC25T04 PC25T05 3-State I/O * * * * * * * * * * * * * * * Output Only 3-State Output Only Drive Strength 1x 2x 3x 4x 5x 1x 2x 3x 4x 5x 1x 2x 3x 4x 5x Pad Sites Used 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Table 9. TTL Pads TTL Cell Name PT25B01 PT25B02 PT25B03 PT25O01 PT25O02 PT25O03 PT25T01 PT25T02 PT25T03 3-State I/O * * * * * * * * * Output Only 3-State Output Only Drive Strength 2 mA 4 mA 8 mA 2 mA 4 mA 8 mA 2 mA 4 mA 8 mA Pad Sites Used 1 1 1 1 1 1 1 1 1 6 MH2RT 4142B-AERO-06/02 MH2RT Table 10. CMOS/TTL Input Only Pad CMOS Cell Name PC25D01 PC25D11 PC25D21 PC25D31 Note: Input Levels CMOS CMOS CMOS CMOS * * * * Schmitt Input Level Shifter Non-Inverting * * Inverting Pad Sites Used 1 1 1 1 1. All 3-state I/Os, 3-state output only and input pads are also available with pull-up and pull-down device. IO33lib Low Slew Rate Cells The IO33lib cells comprise a series of 2.5V/3.3V input/output pads developed for low supply voltage processes in order to interface 2.5V ASICs to 3.3V environments. All IO33lib cells are slew rate controlled. Advantage has been taken of the 2.5V to 3.3V level shifter (slow by construction) to reduce the slew rate without reducing speed. Table 11. IO33lib Pads 3V Interface Pad Name pc33b0x pc33d00 pc33o0x pc33t0x Note: * * 3-State I/O * * 2 mA, 4 mA, 8 mA, 16 mA 2 mA, 4 mA, 8 mA, 16 mA Output Only 3-State Output Only Input Only Drive Strength 2 mA, 4 mA, 8 mA, 16 mA Pad Sites Used 1 1 1 1 1. All 3-state I/Os, 3-state output only and input pads are also available with pull-up and pull-down device. Table 12. IO33lib Power Pads Power Bus Connections Cell Name pv33e00 pv33i00 pv33i25 pv33e33 pv33ecrn * * * * * vssi mixvss * vddi mixvdd Pad Sites Used 1 1 1 1 2 7 4142B-AERO-06/02 Atmel Compiled Megacell Library The Atmel Compiled Megacell Library enables compilation of megacells for the functions Synchronous RAM, High-range Synchronous RAM, Asynchronous RAM, Asynchronous Dual-port RAM, Asynchronous Two-port RAM and Synchronous ROM, according to the user's precise requirements. The Atmel megacells can be instanced as often as required in designs and can be used in parallel with cells from all other Atmel libraries. All the megacell representations required for schematic entry, simulation, place and route, layout generation, and verification are created automatically. General Characteristics of the Atmel Megacell Compilers Compiled Synchronous RAM Megacells General Synchronous RAM Characteristics Synchronous RAM Configurations The Atmel Synchronous RAM compiler has bi-directional or separate I/O ports, and can be configured in multi-bank form, with a maximum of four banks. The range of permitted Synchronous RAM megacell configurations is as follows: Number of bits:128,...144K bits Number of words:32,... 8K Word Size: 4,... 36 bits Synchronous RAM Example Characteristics Configuration Density (Kbits/mm2) Frequency (MHz) Dynamic Power (mW/MHz) The following table shows the range of performances for particular Synchronous RAM configurations under typical conditions. 1K x 8 (8K bits) 51 255 0.17 2K x 16 (32K bits) 58 205 0.36 4K x 32 (128K bits) 62 145 0.73 8 MH2RT 4142B-AERO-06/02 MH2RT Compiled High-range Synchronous RAM Megacells General High-range Synchronous RAM Characteristics High-range Synchronous RAM Configurations The Atmel High-range Synchronous RAM compiler has bi-directional or separate I/O ports, and can be configured in multi-bank form, with a maximum of four banks. The range of permitted High-range Synchronous RAM megacell configurations is as follows: Number of bits: 16K,... 2.25M bits Number of words: 2K,... 32K Word Size: 8,... 72 bits High-range Synchronous RAM Example Characteristics Configuration Density (Kbits/mm2) Frequency (MHz) Dynamic Power (mW/MHz) The following table shows the range of performances for particular High-range Synchronous RAM configurations under typical conditions. 8K x 8 (64K bits) 80 150 0.29 16K x 16 (256K bits) 84 100 0.55 32K x 32 (1M bits) 87 60 1.22 Compiled Asynchronous RAM Megacells General Asynchronous RAM Characteristics Asynchronous RAM Configurations The Atmel Asynchronous RAM compiler has bi-directional or separate I/O ports, and can be configured in multi-bank form, with a maximum of four banks. The range of permitted Asynchronous RAM megacell configurations is as follows: Number of bits:128,... 128K bits Number of words:16,... 4K Word Size: 8,... 36 bits Asynchronous RAM Example Characteristics Configuration Density (Kbits/mm ) Frequency (MHz) Dynamic Power (mW/MHz) 2 The following table shows the range of performances for particular Asynchronous RAM configurations under typical conditions. 1K x 8 (8K bits) 40 415 0.24 2K x 16 (32K bits) 40 405 0.38 4K x 32 (128K bits) 50 265 0.63 9 4142B-AERO-06/02 Compiled Asynchronous Dual-port RAM Megacells General Asynchronous Dualport RAM Characteristics Asynchronous Dual-port RAM Configurations The Atmel Asynchronous Dual-port RAM has bi-directional or separate I/O ports, and can be configured in multi-bank form, with a maximum of four banks. The range of permitted Asynchronous Dual-port RAM Megacell configurations is as follows: Number of bits: 128,... 16K Number of words(1): 64,... 2K Word Size(1): 2,... 36 bits Note: 1. Must be the same for both ports. Asynchronous Dual-port RAM Example Characteristics Configuration Density (Kbits/mm ) Frequency (MHz) Dynamic Power (mW/MHz) 2 The following table shows the range of performances for particular Asynchronous Dualport RAM configurations under typical conditions. 128 x 8 (1K bits) 22 245 0.09 256 x 16 (4K bits) 32 220 0.31 512 x 32 (16K bits) 36 200 0.41 Compiled Two-port RAM Megacells General Two-port RAM Characteristics Two-port RAM Configurations The Atmel Asynchronous Two-port RAM can be configured in multi-bank form, with a maximum of four banks, and can be used to achieve FIFO functions. The range of permitted Asynchronous Two-port RAM Megacell configurations is as follows: Number of bits: 128,... 36K Number of words(1): 64,... 2K Word Size(1): 2,... 36 bits Note: 1. Must be the same for both ports. Two-port RAM Example Characteristics Configuration Density (Kbits/mm ) Frequency (MHz) Dynamic Power (mW/MHz) 2 The following table shows the range of performances for particular Asynchronous Twoport RAM configurations under typical conditions. 256 x 8 (2K bits) 20 315 0.06 512 x 16 (8K bits) 24 290 0.10 1K x 32 (32K bits) 27 235 0.18 10 MH2RT 4142B-AERO-06/02 MH2RT Compiled Synchronous ROM Megacells General Synchronous ROM Characteristics Synchronous ROM Configurations The Atmel Synchronous ROM is diffusion programmable and is applicable in low power solutions. It can be configured in multi-bank form, with a maximum of four banks. The range of permitted Synchronous ROM Megacell configurations is as follows: Number of bits: 256,... 512K Number of words: 64,... 8K Word Size: 4,... 64 bits Synchronous ROM Example Characteristics Configuration Density (Kbits/mm2) Frequency (MHz) Dynamic Power (mW/MHz) The following table shows the range of performances for particular Synchronous ROM configurations under typical conditions. 2K x 8 (16K bits) 400 240 0.13 4K x 16 (64K bits) 568 230 0.26 8K x 32 (256K bits) 669 165 0.54 11 4142B-AERO-06/02 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland TEL (44) 1355-803-000 FAX (44) 1355-242-743 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 literature@atmel.com Web Site http://www.atmel.com (c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R), is a registered trademark of Atmel. Verilog is a registered trademark Gateway Design Automation Corporation. Cadence is a trademark of Cadence Design Systems. Synopsis is a registered trademark of Synopsis Inc.. Other terms and product names may be the trademarks of others. Printed on recycled paper. 4142B-AERO-06/02 /xM |
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