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CP3UB17 Connectivity Processor with USB Interface
PRELIMINARY
Sept. 2003
CP3UB17 Reprogrammable Connectivity Processor with USB Interface
1.0 General Description
The CP3UB17 is backed up by the software resources designers need for rapid time-to-market, including an operating system, peripheral drivers, reference designs, and an integrated development environment. National Semiconductor offers a complete and industryproven application development environment for CP3UB17 applications, including the IAR Embedded Workbench, iSYSTEM winIDEA and iC3000 Active Emulator, Development Board, and Application Software. The CP3UB17 connectivity processor combines a powerful RISC core with on-chip SRAM and Flash memory for high computing bandwidth, hardware communications peripherals for high I/O bandwidth, and an external bus for system expandability. On-chip communications peripherals include: USB controller, ACCESS.bus, Microwire/Plus, SPI, UART, and Advanced Audio Interface (AAI). Additional on-chip peripherals include DMA controller, PCM/CSVD conversion module, Timing and Watchdog Unit, Versatile Timer Unit, MultiFunction Timer, and Multi-Input Wakeup.
Block Diagram
Clock Generator
12 MHz and 32 kHz Oscillator
PLL and Clock Generator
Power-on-Reset
CR16C CPU Core
256K Bytes Flash Program Memory
8K Bytes Flash Data
10K Bytes Static RAM
Serial Debug Interface
CPU Core Bus
Bus Interface Unit
DMA Controller
Peripheral Bus Controller
Interrupt Control Unit
CVSD/PCM
Power Management
Timing and Watchdog Unit
Peripheral Bus
USB
GPIO
Audio Interface
Microwire/ SPI
UART
ACCESS .bus
Versatile Timer Unit
Muti-Function Timer
Multi-Input Wake-Up
DS131
TRI-STATE is a registered trademark of National Semiconductor Corporation.
(c)2003 National Semiconductor Corporation
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CP3UB17
Table of Contents
1.0 2.0 3.0 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . 1 CPU Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 3.20 CR16C CPU Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Control Unit (ICU) . . . . . . . . . . . . . . . . . . . . . . . USB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multi-Input Wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . Triple Clock and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multi-Function Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . Versatile Timer Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing and Watchdog Module . . . . . . . . . . . . . . . . . . . . UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microwire/SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ACCESS.bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . DMA CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . Advanced Audio interface . . . . . . . . . . . . . . . . . . . . . . . . CVSD/PCM Conversion Module . . . . . . . . . . . . . . . . . . . Serial Debug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 4 4 4 4 4 5 5 5 5 5 5 5 5 6 6 6 6 6
15.0
USB Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
15.1 15.2 15.3 15.4 Functional States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Endpoint Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB Controller Registers. . . . . . . . . . . . . . . . . . . . . . . . Transceiver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . Audio Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . Audio Interface Modes . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . Frame Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . Audio Interface Operation . . . . . . . . . . . . . . . . . . . . . . . Communication Options. . . . . . . . . . . . . . . . . . . . . . . . . Audio Interface Registers. . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCM Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . CVSD Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCM to CVSD Conversion. . . . . . . . . . . . . . . . . . . . . . CVSD to PCM Conversion. . . . . . . . . . . . . . . . . . . . . . Interrupt Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Freeze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CVSD/PCM Converter Registers . . . . . . . . . . . . . . . . . Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . UART Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baud Rate Calculations . . . . . . . . . . . . . . . . . . . . . . . . Microwire Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . Microwire Interface Registers . . . . . . . . . . . . . . . . . . . ACB Protocol Overview . . . . . . . . . . . . . . . . . . . . . . . . ACB Functional Description . . . . . . . . . . . . . . . . . . . . . ACCESS.bus Interface Registers . . . . . . . . . . . . . . . . Usage Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TWM Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer T0 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Operation . . . . . . . . . . . . . . . . . . . . . . . . . . TWM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Programming Procedure. . . . . . . . . . . . . . . Timer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 68 70 85 86 86 89 89 89 91 94
16.0
Advanced Audio Interface . . . . . . . . . . . . . . . . . . . . . 86
16.1 16.2 16.3 16.4 16.5 16.6 16.7
17.0
CVSD/PCM Conversion Module . . . . . . . . . . . . . . . 101
17.1 17.2 17.3 17.4 17.5 17.6 17.7 17.8 17.9 101 101 102 102 102 102 102 103 103 106 106 110 114 116 118 119 119 119 122 124 126 130 131 131 132 132 134 135 136 140 140 141
4.0 5.0
Device Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 5.1 5.2 5.3 5.4 5.5 5.6 5.7 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 General-Purpose Registers . . . . . . . . . . . . . . . . . . . . . Dedicated Address Registers . . . . . . . . . . . . . . . . . . . . Processor Status Register (PSR) . . . . . . . . . . . . . . . . . Configuration Register (CFG) . . . . . . . . . . . . . . . . . . . . Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Environment . . . . . . . . . . . . . . . . . . . . . . . . . Bus Interface Unit (BIU) . . . . . . . . . . . . . . . . . . . . . . . . Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BIU Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . Wait and Hold States . . . . . . . . . . . . . . . . . . . . . . . . . . 16 16 17 18 19 20 20 25 25 26 26 28
18.0
UART Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
18.1 18.2 18.3 18.4
CPU Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 19.0
Microwire/SPI Interface . . . . . . . . . . . . . . . . . . . . . . 116
19.1 19.2 19.3 19.4 19.5
6.0
Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1 6.2 6.3 6.4 6.5
20.0
ACCESS.bus Interface . . . . . . . . . . . . . . . . . . . . . . . 122
20.1 20.2 20.3 20.4
7.0 8.0
System Configuration Registers . . . . . . . . . . . . . . . 29
7.1 7.2 8.1 8.2 8.3 8.4 8.5 Module Configuration Register (MCFG) . . . . . . . . . . . . 29 Module Status Register (MSTAT) . . . . . . . . . . . . . . . . . 29 Flash Memory Protection . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Organization . . . . . . . . . . . . . . . . . . . . . Flash Memory Operations. . . . . . . . . . . . . . . . . . . . . . . Information Block Words. . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Interface Registers . . . . . . . . . . . . . . . . Channel Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software DMA Request . . . . . . . . . . . . . . . . . . . . . . . . Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Controller Register Set. . . . . . . . . . . . . . . . . . . . . Non-Maskable Interrupts. . . . . . . . . . . . . . . . . . . . . . . . Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Controller Registers . . . . . . . . . . . . . . . . . . . . Maskable Interrupt Sources . . . . . . . . . . . . . . . . . . . . . Nested Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Crystal Network . . . . . . . . . . . . . . . . . . . . . . . Main Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slow Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auxiliary Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock and Reset Registers . . . . . . . . . . . . . . . . . . . . . . Active Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Save Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management Registers . . . . . . . . . . . . . . . . . . . Switching Between Power Modes. . . . . . . . . . . . . . . . . 30 30 31 32 34 40 40 41 42 42 42 46 46 46 48 49 51 51 52 52 52 52 52 52 53 55 55 55 55 56 56 57
21.0
Timing and Watchdog Module . . . . . . . . . . . . . . . . 131
21.1 21.2 21.3 21.4 21.5
Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 22.0
Multi-Function Timer . . . . . . . . . . . . . . . . . . . . . . . . 135
22.1 22.2 22.3 22.4 22.5
9.0
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.1 9.2 9.3 9.4 9.5 9.6
23.0 24.0 25.0 26.0
Versatile Timer Unit (VTU) . . . . . . . . . . . . . . . . . . . . 144
23.1 23.2 VTU Functional Description . . . . . . . . . . . . . . . . . . . . . 144 VTU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
10.0
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.1 10.2 10.3 10.4 10.5
Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . 172
26.1 26.2 26.3 26.4 26.5 26.6 26.7 26.8 26.9 26.10 26.11 26.12 26.13 26.14 26.15 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . USB Transceiver Electrical Characteristics . . . . . . . . . Flash Memory On-Chip Programming . . . . . . . . . . . . . Output Signal Levels . . . . . . . . . . . . . . . . . . . . . . . . . . Clock and Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Port Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Advanced Audio Interface (AAI) Timing. . . . . . . . . . . . Microwire/SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . ACCESS.bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . USB Port AC Characteristics . . . . . . . . . . . . . . . . . . . . Multi-Function Timer (MFT) Timing . . . . . . . . . . . . . . . Versatile Timing Unit (VTU) Timing . . . . . . . . . . . . . . . External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 172 172 173 174 175 175 177 178 179 181 186 189 189 190 191
11.0
Triple Clock and Reset . . . . . . . . . . . . . . . . . . . . . . . 50
11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9
12.0
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . 55
12.1 12.2 12.3 12.4 12.5 12.6 12.7
27.0 28.0 29.0
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Device Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 199
13.0 14.0
Multi-Input Wake-Up . . . . . . . . . . . . . . . . . . . . . . . . . 59
13.1 13.2 14.1 14.2 Multi-Input Wake-Up Registers . . . . . . . . . . . . . . . . . . . 59 Programming Procedures . . . . . . . . . . . . . . . . . . . . . . . 61 Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Open-Drain Operation. . . . . . . . . . . . . . . . . . . . . . . . . . 65
Input/Output Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . 62
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CP3UB17
2.0
CPU Features
Flexible I/O Up to 37 general-purpose I/O pins (shared with on-chip peripheral I/O pins) Programmable I/O pin characteristics: TRI-STATE output, push-pull output, weak pull-up input, high-impedance input Schmitt triggers on general purpose inputs Multi-Input Wakeup Extensive Power and Clock Management Support On-chip Phase Locked Loop Support for multiple clock options Dual clock and reset Power-down modes
CPU Features Fully static RISC processor core, capable of operating from 0 to 24 MHz with zero wait/hold states Minimum 41.7 ns instruction cycle time with a 24-MHz internal clock frequency, based on a 12-MHz external input 30 independently vectored peripheral interrupts On-Chip Memory 256K bytes reprogrammable Flash program memory 8K bytes Flash data memory 10K bytes of static RAM data memory Addresses up to 8 Mbytes of external memory Broad Range of Hardware Communications Peripherals
Full-speed USB node including seven Endpoint-FIFOs Power Supply conforming to USB 1.1 specification 2 ACCESS.bus serial bus (compatible with Philips I C bus) I/O port operation at 2.5V to 3.3V 8/16-bit SPI, Microwire/Plus serial interface Core logic operation at 2.5V Universal Asynchronous Receiver/Transmitter (UART) On-chip power-on reset Advanced Audio Interface (AAI) to connect to external 8/ Temperature Range 13-bit PCM Codecs as well as to ISDN-Controllers -40C to +85C (Industrial) through the IOM-2 interface (slave only) PCM/CVSD converter supporting one bidirectional audio Packages connection CSP-48, LQFP-100 General-Purpose Hardware Peripherals Complete Development Environment Dual 16-bit Multi-Function Timer Pre-integrated hardware and software support for rapid Versatile Timer Unit with four subsystems (VTU) prototyping and production Four channel DMA controller Integrated environment Timing and Watchdog Unit Project manager Multi-file C source editor
CP3UB17 Connectivity Processor Selection Guide NSID CP3UB17G38 CP3UB17K38 Speed (MHz) 24 24 Temp. Range -40 to +85C -40 to +85C Program Flash (kBytes) 256 256 Data Flash (kBytes) 8 8 SRAM (kBytes) 10 10 External Address Lines 22 0 I/Os 37 21 Package Type LQFP-100 CSP-48
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CP3UB17
3.0
Device Overview
The I/O pin characteristics are fully programmable. Each pin can be configured to operate as a TRI-STATE output, pushpull output, weak pull-up input, or high-impedance input.
The CP3UB17 connectivity processor is a complete microcomputers with all system timing, interrupt logic, program memory, data memory, I/O ports included on-chip, making them well-suited to a wide range of embedded applications. The block diagram on page 1 shows the major on-chip components of the CP3UB17.
3.4
BUS INTERFACE UNIT
The Bus Interface Unit (BIU) controls access to internal/external memory and I/O. It determines the configured param3.1 CR16C CPU CORE eters for bus access (such as the number of wait states for The CP3UB17 implements the CR16C CPU core module. memory access) and issues the appropriate bus signals for The high performance of the CPU core results from the im- each requested access. plementation of a pipelined architecture with a two-bytes- The BIU uses a set of control registers to determine how per-cycle pipelined system bus. As a result, the CPU can many wait states and hold states are used when accessing support a peak execution rate of one instruction per clock Flash program memory, and the I/O area (Port B and Port cycle. C). At start-up, the configuration registers are set for slowest For more information, please refer to the CR16C Programmer's Reference Manual (document number 424521772101, which may be downloaded from National's web site at http://www.national.com). possible memory access. To achieve fastest possible program execution, appropriate values must be programmed. These settings vary with the clock frequency and the type of off-chip device being accessed.
3.2
MEMORY
3.5
INTERRUPT CONTROL UNIT (ICU)
The CP3UB17 supports a uniform linear address space of up to 16 megabytes. Three types of on-chip memory occupy specific regions within this address space: 256K bytes of Flash program memory 8K bytes of Flash data memory 10K bytes of static RAM Up to 8M bytes of external memory (100-pin devices ) The 256K bytes of Flash program memory are used to store the application program and real-time operating system. The Flash memory has security features to prevent unintentional programming and to prevent unauthorized access to the program code. This memory can be programmed with an external programming unit or with the device installed in the application system (in-system programming).
The ICU receives interrupt requests from internal and external sources and generates interrupts to the CPU. An interrupt is an event that temporarily stops the normal flow of program execution and causes a separate interrupt handler to be executed. After the interrupt is serviced, CPU execution continues with the next instruction in the program following the point of interruption. Interrupts from the timers, UART, Microwire/SPI interface, and Multi-Input Wake-Up, are all maskable interrupts; they can be enabled or disabled by software. There are 32 of these maskable interrupts, assigned to 32 linear priority levels. The highest-priority interrupt is the Non-Maskable Interrupt (NMI), which is generated by a signal received on the NMI input pin.
The 8K bytes of Flash data memory are used for non-volatile storage of data entered by the end-user, such as config- 3.6 USB uration settings. The USB node is a Universal Serial Bus (USB) Node conThe 10K bytes of static RAM are used for temporary storage troller compatible with USB Specification, 1.0 and 1.1. It inof data and for the program stack and interrupt stack. Read tegrates the required USB transceiver, the Serial Interface and write operations can be byte-wide or word-wide, de- Engine (SIE), and USB endpoint FIFOs. A total of seven pending on the instruction executed by the CPU. endpoint pipes are supported: one bidirectional pipe for the Up to 8M bytes of external memory can be added on an ex- mandatory control EP0 and an additional six pipes for uniditernal bus. The external bus is only available on devices in rectional endpoints to support USB interrupt, bulk, and isochronous data transfers. 100-pin packages. For Flash program and data memory, the device internally generates the necessary voltages for programming. No additional power supply is required.
3.7
MULTI-INPUT WAKE-UP
3.3
INPUT/OUTPUT PORTS
The device has up to 37 software-configurable I/O pins, organized into five ports called Port B, Port C, Port G, Port H, and Port I. Each pin can be configured to operate as a general-purpose input or general-purpose output. In addition, many I/O pins can be configured to operate as inputs or outputs for on-chip peripheral modules such as the UART, timers, or Microwire/SPI interface.
The Multi-Input Wake-Up (MIWU) module can be used for either of two purposes: to provide inputs for waking up (exiting) from the Halt, Idle, or Power Save mode; or to provide general-purpose edge-triggered maskable interrupts from external sources. This 16-channel module generates four programmable interrupts to the CPU based on the signals received on its 16 input channels. Channels can be individually enabled or disabled, and programmed to respond to positive or negative edges.
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CP3UB17
3.8
TRIPLE CLOCK AND RESET
The Triple Clock and Reset module generates a high-speed main System Clock from an external crystal network. It also provides the main system reset signal and a power-on reset function. 3.11 VERSATILE TIMER UNIT This module generates a slow System Clock (32.768 kHz) The Versatile Timer Unit (VTU) module contains four indefrom an optional external crystal network. The Slow Clock is pendent timer subsystems, each operating in either dual 8used for operating the device in power-save mode. The bit PWM configuration, as a single 16-bit PWM timer, or a 32.768 kHz external crystal network is optional, because 16-bit counter with two input capture channels. Each of the the low speed System Clock can be derived from the high- four timer subsystems offer an 8-bit clock prescaler to acspeed clock by a prescaler. commodate a wide range of frequencies. Also, two independent clocks divided down from the high 3.12 TIMING AND WATCHDOG MODULE speed clock are available on output pins. The Timing and Watchdog Module (TWM) contains a RealThe Triple Clock and Reset module provides the clock sigTime timer and a Watchdog unit. The Real-Time Clock Timnals required for the operation of the various CP3UB17 oning function can be used to generate periodic real-time chip modules. From external crystal networks, it generates based system interrupts. The timer output is one of 16 inthe Main Clock, which can be scaled up to 24 MHz from an puts to the Multi-Input-Wake-Up module which can be used external 12 MHz input clock, and a 32.768 kHz secondary to exit from a power-saving mode. The Watchdog unit is deSystem Clock. The 12 MHz external clock is primarily used signed to detect the application program getting stuck in an as the reference frequency for the on-chip PLL. Also the infinite loop resulting in loss of program control or "runaway" clock for modules which require a fixed clock rate (e.g. the programs. When the watchdog triggers, it resets the device. PCM/CVSD transcoder) is generated through prescalers The TWM is clocked by the low-speed System Clock. from the 12 MHz clock. The PLL generates the input clock for the USB node and may be used to drive the high-speed 3.13 UART System Clock through a prescaler. Alternatively, the high The UART supports a wide range of programmable baud speed System Clock can be derived directly from the 12 rates and data formats, parity generation, and several error MHz Main Clock. detection schemes. The baud rate is generated on-chip, unIn addition, this module generates the device reset by using der software control. reset input signals coming from an external reset and variThe UART offers a wake-up condition from the power-save ous on-chip modules. mode using the Multi-Input Wake-Up module.
Dual Independent Timer mode--Generates system timing signals or counts occurrences of external events. Single Input Capture and Single Timer mode--Provides one external event counter and one system timer.
3.9
POWER MANAGEMENT
3.14
MICROWIRE/SPI
The Power Management Module (PMM) improves the efficiency of the device by changing the operating mode and power consumption to match the required level of activity. The device can operate in any of four power modes: Active--The device operates at full speed using the highfrequency clock. All device functions are fully operational. Power Save--The device operates at reduced speed using the Slow Clock. The CPU and some modules can continue to operate at this low speed. Idle--The device is inactive except for the Power Management Module and Timing and Watchdog Module, which continue to operate using the Slow Clock. Halt--The device is inactive but still retains its internal state (RAM and register contents).
The Microwire/SPI (MWSPI) interface module supports synchronous serial communications with other devices that conform to Microwire or Serial Peripheral Interface (SPI) specifications. It supports 8-bit and 16-bit data transfers. The Microwire interface allows several devices to communicate over a single system consisting of four wires: serial in, serial out, shift clock, and slave enable. At any given time, the Microwire interface operates as the master or a slave. The Microwire interface supports the full set of slave select for multi-slave implementation. In master mode, the shift clock is generated on chip under software control. In slave mode, a wake-up out of powersave mode is triggered using the Multi-Input Wake-Up module.
3.10
MULTI-FUNCTION TIMER
3.15
ACCESS.BUS INTERFACE
The ACCESS.bus interface module (ACB) is a two-wire seThe Multi-Function Timer (MFT) module contains a pair of rial interface with the ACCESS.bus physical layer. It is also 16-bit timer/counter registers. Each timer/counter unit can compatible with Intel's System Management Bus (SMBus) be configured to operate in any of the following modes: and Philips' I2C bus. The ACB module can be configured as Processor-Independent Pulse Width Modulation (PWM) a bus master or slave, and can maintain bidirectional commode--Generates pulses of a specified width and duty munications with both multiple master and slave devices. cycle and provides a general-purpose timer/counter. The ACCESS.bus receiver can trigger a wake-up condition Dual Input Capture mode--Measures the elapsed time out of the low-power modes using the Multi-Input Wake-Up between occurrences of external event and provides a module. general-purpose timer/counter.
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CP3UB17
3.16
DMA CONTROLLER
3.18
CVSD/PCM CONVERSION MODULE
The Direct Memory Access Controller (DMAC) can speed up data transfer between memory and I/O devices or between two memories, relative to data transfers performed directly by the CPU. A method called cycle-stealing allows the CPU and the DMAC to use the core bus in parallel. The DMAC implements four independent DMA channels. DMA requests from a primary and a secondary source are recognized for each DMA channel, as well as a software DMA request issued directly by the CPU. Table 1 shows the DMA channel assignment on the CP3UB17 architecture. The following on-chip modules can assert a DMA request to the DMAC: CR16C (Software DMA request) USB UART Advanced Audio Interface PCM/CVSD Converter
The CVSD/PCM module performs conversion between CVSD data and PCM data, in which the PCM data can be 8-bit -Law, 8-bit A-Law, or 13-bit to 16-bit Linear.
3.19
SERIAL DEBUG INTERFACE
The Serial Debug Interface module (SDI module)provides a JTAG-based serial link to an external debugger, for example running on a PC. In addition, the SDI module integrates an on-chip debug module, which allows the user to set up to four hardware breakpoints on instruction execution and data transfer. The SDI module can act as a CPU bus master to access all memory mapped resources, such as RAM and peripherals. Therefore it also allows for fast program code download into the on-chip Flash program memory using the JTAG interface.
3.20
DEVELOPMENT SUPPORT
The CP3UB17 is backed up by the software resources designers need for rapid time-to-market, including an operatTable 1 shows how the four DMA channels are assigned ing system, peripheral drivers, reference designs, and an integrated development environment. to the modules listed above. National Semiconductor offers a complete and industryTable 1 DMA Channel Assignment proven application development environment for CP3UB17 applications, including the IAR Embedded Workbench, Primary/ Channel Peripheral Transaction iSYSTEM winIDEA and iC3000 Active Emulator, DevelopSecondary ment Board, and Application Software. See your National Semiconductor sales representative for current information Primary USB Read/Write on availability and features of emulation equipment and 0 Secondary UART Read evaluation boards. Primary 1 Secondary Primary 2 Secondary Primary 3 Secondary CVSD/PCM Write CVSD/PCM AAI Read Write Unused AAI N/A Read UART Write
3.17
ADVANCED AUDIO INTERFACE
The audio interface provides a serial synchronous, full-duplex interface to CODECs and similar serial devices. Transmit and receive paths operate asynchronously with respect to each other. Each path uses three signals for communication: shift clock, frame synchronization, and data. In case receive and transmit use separate shift clocks and frame sync signals, the interface operates in its asynchronous mode. Alternatively, the transmit and receive path can share the same shift clock and frame sync signals for synchronous mode operation. The interface can handle data words of either 8- or 16-bit length and data frames can consist of up to four slots. In the normal mode of operation, the interface only transfers one word at a periodic rate. In the network mode, the interface transfers multiple words at a periodic rate. The periodic rate is also called a data frame and each word within one frame is called a slot. The beginning of each new data frame is marked by the frame sync signal. www.national.com 6
CP3UB17
4.0
Device Pinouts
X1CKI X1CKO X2CKI X2CKO PB[7:0] PC[7:0] A[21:0] SEL0 SEL1 SEL2 SELIO WR0 WR1 RD
8 8 22
12 MHz Crystal or Ext. Clock 32.768 kHz Crystal
12 MHz Crystal or Ext. Clock
X1CKI X1CKO
D+ DUVCC UGND USB
External Bus Interface 32.768 kHz Crystal/
X2CKI X2CKO AVCC AGND PI0 PI1 PI3 PI4 PI5 MIWU MFT GPIO
Power Supply
2 4 6
AVCC AGND VCC IOVCC GND
CP3UB17 (LQFP-100)
PI0 PI1 PI3 PI4 PI5 GPIO
Power Supply
2 2 4
VCC IOVCC GND
CP3UB17 (CSP-48) PI6/WUI9
PI7/TA PG0/RXD/WUI10 PG1/TXD/WUI11 PG2/RTS/WUI12 PG3/CTS/WUI13 PH0/MSK/TIO1 PH1/MDIDO/TIO2
Chip Reset
RESET
Chip Reset
RESET
UART/ MIWU
JTAG I/F to Debugger/ Programmer
TMS TDI TDO TCK RDY
PI6/WUI9 PI7/TA PG0/RXD/WUI10 PG1/TXD/WUI11 PG2/RTS/WUI12 PG3/CTS/WUI13
MIWU MFT JTAG I/F to Debugger/ Programmer
TMS TDI TDO TCK RDY
PH2/MDODI/TIO3 PH3/MWCS/TIO4 PH4/SCK/TIO5 PH5/SFS/TIO6 PH6/STD/TIO7 PH7/SRD/TIO8
MICROWIRE/ SPI/ VTU
UART/ MIWU Mode Selection
AAI/ VTU
ACCESS.bus
SDA SCL
ENV0 ENV1
PG5/SRFS/NMI PI2/SRCLK
AAI/NMI AAI
USB
D+ DUVCC UGND
PH0/MSK/TIO1 PH1/MDIDO/TIO2 PH2/MDODI/TIO3 PH3/MWCS/TIO4 PH4/SCK/TIO5 PH5/SFS/TIO6 PH6/STD/TIO7 PH7/SRD/TIO8 PG5/SRFS/NMI PI2/SRCLK
MICROWIRE/ SPI/ VTU
AAI/ VTU
Mode Selection
ENV0 ENV1 ENV2
AAI/NMI AAI DS139
Table 2 Pin Assignments for 100-Pin Package Pin Name A14 A13 A12 A11 A10 PH6 PH7 ENV1 A9 A8 A7 A6 A5 STD/TIO7 SRD/TIO8 Alternate Function(s) Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 Type O O O O O GPIO GPIO I/O O O O O O
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CP3UB17
Table 2 Pin Assignments for 100-Pin Package Pin Name A4 VCC X2CKI X2CKO GND AVCC AGND IOVCC X1CKO X1CKI GND A3 A2 A1 A0 PI0 PI1 PI2 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 GND IOVCC PI3 PI4 PI5 PI6 PI7 PG0 PG1 PC0 PG2 PG3 PC1 PC2 PC3 PC4 PC5 www.national.com WUI9 TA RXD/WUI10 TXD/WUI11 D8 RTS/WUI12 CTS/WUI13 D9 D10 D11 D12 D13 8 SRCLK D0 D1 D2 D3 D4 D5 D6 D7 Alternate Function(s) Pin Number 14 15 16 17 18 19 20 21 22 23 24 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 Type O PWR I O PWR PWR PWR PWR O I PWR O O O O GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO PWR PWR GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO
CP3UB17
Table 2 Pin Assignments for 100-Pin Package Pin Name PC6 PC7 PG5 TMS TCK TDI GND IOVCC ENV2 SEL0 SCL SDA TDO DD+ UVCC UGND RDY SEL1 SEL2 SELIO A21 A20 PH0 PH1 PH2 PH3 ENV0 IOVCC GND VCC GND RESET RD WR0 WR1 A19 A18 A17 A16 A15 MSK/TIO1 MDIDO/TIO2 MDODI/TIO3 MWCS/TIO4 Alternate Function(s) D14 D15 SRFS/NMI Pin Number 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 Type GPIO GPIO GPIO I I I PWR PWR I/O O I/O I/O O I/O I/O PWR PWR O O O O O O GPIO GPIO GPIO GPIO I/O PWR PWR PWR PWR I O O O O O O O O
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CP3UB17
Table 2 Pin Assignments for 100-Pin Package Pin Name PH4 PH5 Alternate Function(s) SCK/TIO5 SFS/TIO6 Pin Number 99 100 Type GPIO GPIO
Note 1: The ENV0, ENV1, ENV2, TCK, TDI, and TMS pins each have a weak pull-up to keep the input from floating. Note 2: The RESET input has a weak pulldown. Note 3: These functions are always enabled, due to the direct low-impedance path to these pins.
Table 3 Pin Assignments for 48-Pin Package Pin Name PH6 PH7 ENV1 VCC X2CKI X2CKO GND AVCC AGND IOVCC X1CKO X1CKI GND PI0 PI1 PI2 PI3 PI4 PI5 PI6 PI7 PG0 PG1 PG2 PG3 PG5 TMS TCK TDI GND IOVCC TDO DD+ UVCC UGND www.national.com 10 WUI9 TA RXD/WUI10 TXD/WUI11 RTS/WUI12 CTS/WUI13 SRFS/NMI SRCLK Alternate Function(s) STD/TIO7 SRD/TIO8 Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Type GPIO GPIO I/O PWR I O PWR PWR PWR PWR O I PWR GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO I I I PWR PWR O, GPIO O, GPIO I/O PWR, I/O PWR, O
CP3UB17
Pin Name RDY PH0 PH1 PH2 PH3 ENV0 VCC GND RESET PH4 PH5
Alternate Function(s)
Pin Number 38
Type O GPIO GPIO GPIO GPIO I/O PWR PWR I GPIO GPIO
MSK/TIO1 MDIDO/TIO2 MDODI/TIO3 MWCS/TIO4
39 40 41 42 43 44 45 46
SCK/TIO5 SFS/TIO6
47 48
Note 1: The ENV0 and ENV1, TCK, TDI and TMS pins each have a weak pull-up to keep the input from floating. Note 2: The RESET input has a weak pulldown. Note 3: These functions are always enabled, due to the direct low-impedance path to these pins.
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CP3UB17
4.1
PIN DESCRIPTION
figured as port pins, even when the associated peripheral or interface is enabled. Table 4 lists the device pins.
Some pins may be enabled as general-purpose I/O-port pins or as alternate functions associated with specific peripherals or interfaces. These pins may be individually con-
Table 4 CP3UB17 Pin Description for the 100-Pin LQFP Package Name X1CKI X1CKO X2CKI X2CKO AVCC IOVCC VCC GND AGND RESET TMS TDI TDO TCK RDY PG0 Pins 1 1 1 1 1 4 2 6 1 1 1 1 1 1 1 1 I/O Input Output Input Output Input Input Input Input Input Input Input Input Output Input Output I/O Primary Function 12 MHz Oscillator Input 12 MHz Oscillator Output 32 kHz Oscillator Input 32 kHz Oscillator Output PLL Analog Power Supply 2.5V - 3.3V I/O Power Supply 2.5V Core Logic Power Supply Reference Ground PLL Analog Ground Chip general reset JTAG Test Mode Select (with internal weak pull-up) JTAG Test Data Input (with internal weak pull-up) JTAG Test Data Output JTAG Test Clock Input (with internal weak pull-up) NEXUS Ready Output Generic I/O WUI10 TXD PG1 1 I/O Generic I/O WUI11 RTS PG2 1 I/O Generic I/O WUI12 CTS PG3 1 I/O Generic I/O WUI13 SRFS PG5 1 I/O Generic I/O NMI MSK PH0 1 I/O Generic I/O TIO1 MDIDO PH1 1 I/O Generic I/O TIO2 MDODI PH2 1 I/O Generic I/O TIO3 Versatile Timer Channel 3 Versatile Timer Channel 2 SPI Master Out Slave In Versatile Timer Channel 1 SPI Master In Slave Out Non-Maskable Interrupt Input SPI Shift Clock Multi-Input Wake-Up Channel 13 AAI Receive Frame Sync Multi-Input Wake-Up Channel 12 UART Clear-To-Send Input Multi-Input Wake-Up Channel 11 UART Ready-To-Send Output Multi-Input Wake-Up Channel 10 UART Transmit Data Output Alternate Name None None None None None None None None None None None None None None None RXD None None None None None None None None None None None None None None None UART Receive Data Input Alternate Function
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CP3UB17
Name
Pins
I/O
Primary Function
Alternate Name MWCS
Alternate Function SPI Slave Select Input Versatile Timer Channel 4 AAI Clock Versatile Timer Channel 5 AAI Frame Synchronization Versatile Timer Channel 6 AAI Transmit Data Output Versatile Timer Channel 7 AAI Receive Data Input Versatile Timer Channel 8 None None AAI Receive Clock None None None Multi-Input Wake-Up Channel 9 Multi Function Timer Port A None None None None None None External Data Bus Bit 0 to 7 External Data Bus Bit 8 to 15 None None None None None None None None PLL Clock Output
PH3
1
I/O
Generic I/O TIO4 SCK
PH4
1
I/O
Generic I/O TIO5 SFS
PH5
1
I/O
Generic I/O TIO6 STD
PH6
1
I/O
Generic I/O TIO7 SRD
PH7 PI0 PI1 PI2 PI3 PI4 PI5 PI6 PI7 SDA SCL D+ DUVCC UGND PB[7:0] PC[7:0] A[21:0] SEL0 SEL1 SEL2 SELIO WR0 WR1 RD ENV0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 8 22 1 1 1 1 1 1 1 1
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input Input I/O I/O Output Output Output Output Output Output Output Output I/O
Generic I/O TIO8 Generic I/O Generic I/O Generic I/O Generic I/O Generic I/O Generic I/O Generic I/O Generic I/O ACCESS.bus Serial Data ACCESS.bus Clock USB D+ Upstream Port USB D- Upstream Port 3.3V USB Transceiver Supply USB Transceiver Ground Generic I/O Generic I/O External Address Bus Bit 0 to 21 Chip Select for Zone 0 Chip Select for Zone 1 Chip Select for Zone 2 Chip Select for Zone I/O Zone External Memory Write Low Byte External Memory Write High Byte External Memory Read Special mode select input with internal pull-up during reset None None SRCLK None None None WUI9 TA None None None None None None D[7:0] D[15:8] None None None None None None None None PLLCLK
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CP3UB17
Name ENV1 ENV2
Pins 1 1
I/O I/O I/O
Primary Function Special mode select input with internal pull-up during reset Special mode select input with internal pull-up during reset
Alternate Name CPUCLK SLOWCLK
Alternate Function CPU Clock Output Slow Clock Output
Table 5 CP3UB17 Pin Description for the 48-Pin CSP Name X1CKI X1CKO X2CKI X2CKO AVCC IOVCC VCC GND AGND RESET TMS TDI TDO TCK RDY PG0 Pins 1 1 1 1 1 2 2 4 1 1 1 1 1 1 1 1 I/O Input Output Input Output Input Input Input Input Input Input Input Input Output Input Output I/O Primary Function 12 MHz Oscillator Input 12 MHz Oscillator Output 32 kHz Oscillator Input 32 kHz Oscillator Output PLL Analog Power Supply 2.5V - 3.3V I/O Power Supply 2.5V Core Logic Power Supply Reference Ground PLL Analog Ground Chip general reset JTAG Test Mode Select (with internal weak pull-up) JTAG Test Data Input (with internal weak pull-up) JTAG Test Data Output JTAG Test Clock Input (with internal weak pull-up) NEXUS Ready Output Generic I/O WUI10 TXD PG1 1 I/O Generic I/O WUI11 RTS PG2 1 I/O Generic I/O WUI12 CTS PG3 1 I/O Generic I/O WUI13 SRFS PG5 1 I/O Generic I/O NMI MSK PH0 1 I/O Generic I/O TIO1 MDIDO PH1 1 I/O Generic I/O TIO2 www.national.com 14 Versatile Timer Channel 2 Versatile Timer Channel 1 SPI Master In Slave Out Non-Maskable Interrupt Input SPI Shift Clock Multi-Input Wake-Up Channel 13 AAI Receive Frame Sync Multi-Input Wake-Up Channel 12 UART Clear-To-Send Input Multi-Input Wake-Up Channel 11 UART Ready-To-Send Output Multi-Input Wake-Up Channel 10 UART Transmit Data Output Alternate Name None None None None None None None None None None None None None None None RXD None None None None None None None None None None None None None None None UART Receive Data Input Alternate Function
CP3UB17
Name
Pins
I/O
Primary Function
Alternate Name MDODI
Alternate Function SPI Master Out Slave In Versatile Timer Channel 3 SPI Slave Select Input Versatile Timer Channel 4 AAI Clock Versatile Timer Channel 5 AAI Frame Synchronization Versatile Timer Channel 6 AAI Transmit Data Output Versatile Timer Channel 7 AAI Receive Data Input Versatile Timer Channel 8 None None AAI Receive Clock None None None Multi-Input Wake-Up Channel 9 Multi Function Timer Port A None None None None None None PLL Clock Output CPU Clock Output
PH2
1
I/O
Generic I/O TIO3 MWCS
PH3
1
I/O
Generic I/O TIO4 SCK
PH4
1
I/O
Generic I/O TIO5 SFS
PH5
1
I/O
Generic I/O TIO6 STD
PH6
1
I/O
Generic I/O TIO7 SRD
PH7 PI0 PI1 PI2 PI3 PI4 PI5 PI6 PI7 D+ DUVCC UGND SDA SCL ENV0 ENV1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input Input I/O I/O I/O I/O
Generic I/O TIO8 Generic I/O Generic I/O Generic I/O Generic I/O Generic I/O Generic I/O Generic I/O Generic I/O USB D+ Upstream Port USB D- Upstream Port 3.3V USB Transceiver Supply USB Transceiver Ground ACCESS.bus Serial Data ACCESS.bus Clock Special mode select input with internal pull-up during reset Special mode select input with internal pull-up during reset None None SRCLK None None None WUI9 TA None None None None None None PLLCLK CPUCLK
15
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CP3UB17
5.0
CPU Architecture
The CP3UB17 uses the CR16C third-generation 16-bit When the CFG.SR bit is clear, register pairs are grouped CompactRISC processor core. The CPU implements a Rein the manner used by native CR16C software: (R1,R0), duced Instruction Set Computer (RISC) architecture that al(R2,R1) ... (R11,R10), (R12_L, R11), R12, R13, RA, SP. lows an effective execution rate of up to one instruction per R12, R13, RA, and SP are 32-bit registers for holding adclock cycle. For a detailed description of the CPU16C archidresses greater than 16 bits. tecture, see the CompactRISC CR16C Programmer's Ref- With the recommended calling convention for the architecerence Manual which is available on the National ture, some of these registers are assigned special hardware Semiconductor web site (http://www.nsc.com). and software functions. Registers R0 to R13 are for generalThe CR16C CPU core includes these internal registers: purpose use, such as holding variables, addresses, or index values. The SP register holds a pointer to the program runGeneral-purpose registers (R0-R13, RA, and SP) Dedicated address registers (PC, ISP, USP, and INT- time stack. The RA register holds a subroutine return address. The R12 and R13 registers are available to hold base BASE) addresses used in the index addressing mode. Processor Status Register (PSR) Configuration Register (CFG) The R0-R11, PSR, and CFG registers are 16 bits wide. The R12, R13, RA, SP, ISP and USP registers are 32 bits wide. The PC register is 24 bits wide. Figure 1 shows the CPU registers.
Dedicated Address Registers 15 0 23 31 PC ISPH ISPL USPH USPL INTBASEH INTBASEL General-Purpose Registers 15 0 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 RA SP DS004
If a general-purpose register is specified by an operation that is 8 bits long, only the lower byte of the register is used; the upper part is not referenced or modified. Similarly, for word operations on register pairs, only the lower word is used. The upper word is not referenced or modified.
5.2
DEDICATED ADDRESS REGISTERS
The CR16C has four dedicated address registers to implement specific functions: the PC, ISP, USP, and INTBASE registers. 5.2.1 Program Counter (PC) Register
Processor Status Register 15 0 PSR Configuration Register 15 0 CFG
31
The 24-bit value in the PC register points to the first byte of the instruction currently being executed. CR16C instructions are aligned to even addresses, therefore the least significant bit of the PC is always 0. At reset, the PC is initialized to 0 or an optional predetermined value. When a warm reset occurs, value of the PC prior to reset is saved in the (R1,R0) general-purpose register pair. 5.2.2 Interrupt Stack Pointer (ISP)
The 32-bit ISP register points to the top of the interrupt stack. This stack is used by hardware to service exceptions (interrupts and traps). The stack pointer may be accessed Figure 1. CPU Registers as the ISP register for initialization. The interrupt stack can Some register bits are designated as "reserved." Software be located anywhere in the CPU address space. The ISP must write a zero to these bit locations when it writes to the cannot be used for any purpose other than the interrupt register. Read operations from reserved bit locations return stack, which is used for automatic storage of the CPU registers when an exception occurs and restoration of these undefined values. registers when the exception handler returns. The interrupt 5.1 GENERAL-PURPOSE REGISTERS stack grows downward in memory. The least significant bit The CompactRISC CPU features 16 general-purpose regis- and the 8 most significant bits of the ISP register are always ters. These registers are used individually as 16-bit oper- 0. ands or as register pairs for operations on addresses 5.2.3 User Stack Pointer (USP) greater than 16 bits. The USP register points to the top of the user-mode proGeneral-purpose registers are defined as R0 through gram stack. Separate stacks are available for user and suR13, RA, and SP. pervisor modes, to support protection mechanisms for Registers are grouped into pairs based on the setting of multitasking software. The processor mode is controlled by the Short Register bit in the Configuration Register the U bit in the PSR register (which is called PSR.U in the (CFG.SR). When the CFG.SR bit is set, the grouping of shorthand convention). Stack grow downward in memory. If register pairs is upward-compatible with the architecture the USP register points to an illegal address (any address of the earlier CR16A/B CPU cores: (R1,R0), (R2,R1) ... greater than 0x00FF_FFFF) and the USP is used for stack (R11,R10), (R12_L, R11), (R13_L, R12_L), (R14_L, access, an IAD trap is taken. R13_L) and SP. (R14_L, R13_L) is the same as (RA,ERA).
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CP3UB17
5.2.4
Interrupt Base Register (INTBASE)
N
The INTBASE register holds the address of the dispatch table for exceptions. The dispatch table can be located anywhere in the CPU address space. When loading the INTBASE register, bits 31 to 24 and bit 0 must written with 0.
5.3
PROCESSOR STATUS REGISTER (PSR)
E
The PSR provides state information and controls operating modes for the CPU. The format of the PSR is shown below. 15 12 11 10 9 I PE 8 7 6 5 F 4 3 2 1 0
Reserved
0NZ
0UL
TC
C
T
L
U
F
Z
The Carry bit indicates whether a carry or borrow occurred after addition or subtraction. 0 - No carry or borrow occurred. 1 - Carry or borrow occurred. The Trace bit enables execution tracing, in which a Trace trap (TRC) is taken after every instruction. Tracing is automatically disabled during the execution of an exception handler. 0 - Tracing disabled. 1 - Tracing enabled. The Low bit indicates the result of the last comparison operation, with the operands interpreted as unsigned integers. 0 - Second operand greater than or equal to first operand. 1 - Second operand less than first operand. The User Mode bit controls whether the CPU is in user or supervisor mode. In supervisor mode, the SP register is used for stack operations. In user mode, the USP register is used instead. User mode is entered by executing the Jump USR instruction. When an exception is taken, the exception handler automatically begins execution in supervisor mode. The USP register is accessible using the Load Processor Register (LPR/LPRD) instruction in supervisor mode. In user mode, an attempt to access the USP register generates a UND trap. 0 - CPU is executing in supervisor mode. 1 - CPU is executing in user mode. The Flag bit is a general condition flag for signalling exception conditions or distinguishing the results of an instruction, among other thing uses. For example, integer arithmetic instructions use the F bit to indicate an overflow condition after an addition or subtraction operation. The Zero bit is used by comparison operations. In a comparison of integers, the Z bit is set if the two operands are equal. If the operands are unequal, the Z bit is cleared. 0 - Source and destination operands unequal. 1 - Source and destination operands equal.
P
I
The Negative bit indicates the result of the last comparison operation, with the operands interpreted as signed integers. 0 - Second operand greater than or equal to first operand. 1 - Second operand less than first operand. The Local Maskable Interrupt Enable bit enables or disables maskable interrupts. If this bit and the Global Maskable Interrupt Enable (I) bit are both set, all interrupts are enabled. If either of these bits is clear, only the nonmaskable interrupt is enabled. The E bit is set by the Enable Interrupts (EI) instruction and cleared by the Disable Interrupts (DI) instruction. 0 - Maskable interrupts disabled. 1 - Maskable interrupts enabled. The Trace Trap Pending bit is used together with the Trace (T) bit to prevent a Trace (TRC) trap from occurring more than once for one instruction. At the beginning of the execution of an instruction, the state of the T bit is copied into the P bit. If the P bit remains set at the end of the instruction execution, the TRC trap is taken. 0 - No trace trap pending. 1 - Trace trap pending. The Global Maskable Interrupt Enable bit is used to enable or disable maskable interrupts. If this bit and the Local Maskable Interrupt Enable (E) bit are both set, all maskable interrupts are taken. If either bit is clear, only the non-maskable interrupt is taken. Unlike the E bit, the I bit is automatically cleared when an interrupt occurs and automatically set upon completion of an interrupt handler. 0 - Maskable interrupts disabled. 1 - Maskable interrupts enabled.
Bits Z, C, L, N, and F of the PSR are referenced from assembly language by the condition code in conditional branch instructions. A conditional branch instruction may cause a branch in program execution, based on the value of one or more of these PSR bits. For example, one of the Bcond instructions, BEQ (Branch EQual), causes a branch if the PSR.Z bit is set. On reset, bits 0 through 11 of the PSR are cleared, except for the PSR.E bit, which is set. On warm reset, the values of each bit before reset are copied into the R2 general-purpose register. Bits 4 and 8 of the PSR have a constant value of 0. Bits 12 through 15 are reserved. In general, status bits are modified only by specific instructions. Otherwise, status bits maintain their values throughout instructions which do not implicitly affect them.
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5.4
CONFIGURATION REGISTER (CFG)
The CFG register is used to enable or disable various operating modes and to control optional on-chip caches. Because the CP3UB17 does not have cache memory, the cache control bits in the CFG register are reserved. All CFG bits are cleared on reset. 15 Reserved 10 9 8 7 6 0 5 Reserved 2 1 0 0 0
SR ED 0
ED
SR
The Extended Dispatch bit selects whether the size of an entry in the interrupt dispatch table (IDT) is 16 or 32 bits. Each entry holds the address of the appropriate exception handler. When the IDT has 16-bit entries, and all exception handlers must reside in the first 128K of the address space. The location of the IDT is held in the INTBASE register, which is not affected by the state of the ED bit. 0 - Interrupt dispatch table has 16-bit entries. 1 - Interrupt dispatch table has 32-bit entries. The Short Register bit enables a compatibility mode for the CR16B large model. In the CR16C core, registers R12, R13, and RA are extended to 32 bits. In the CR16B large model, only the lower 16 bits of these registers are used, and these "short registers" are paired together for 32-bit operations. In this mode, the (RA, R13) register pair is used as the extended RA register, and address displacements relative to a single register are supported with offsets of 0 and 14 bits in place of the index addressing with these displacements. 0 - 32-bit registers are used. 1 - 16-bit registers are used (CR16B mode).
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5.5
ADDRESSING MODES
The CR16C CPU core implements a load/store architecture, in which arithmetic and logical instructions operate on register operands. Memory operands are made accessible in registers using load and store instructions. For efficient implementation of I/O-intensive embedded applications, the architecture also provides a set of bit operations that operate on memory operands. The load and store instructions support these addressing modes: register/pair, immediate, relative, absolute, and index addressing. When register pairs are used, the lower bits are in the lower index register and the upper bits are in the higher index register. When the CFG.SR bit is clear, the 32bit registers R12, R13, RA, and SP are also treated as register pairs. References to register pairs in assembly language use parentheses. With a register pair, the lower numbered register pair must be on the right. For example, jump (r5, r4) load $4(r4,r3), (r6,r5) load $5(r12), (r13) The instruction set supports the following addressing modes: Register/Pair Mode In register/pair mode, the operand is held in a general-purpose register, or in a general-purpose register pair. For example, the following instruction adds the contents of the low byte of register r1 to the contents of the low byte of r2, and places the result in the low byte register r2. The high byte of register r2 is not modified. ADDB R1, R2 Immediate In immediate mode, the operand is a conMode stant value which is encoded in the instruction. For example, the following instruction multiplies the value of r4 by 4 and places the result in r4. MULW $4, R4 Relative Mode In relative mode, the operand is addressed using a relative value (displacement) encoded in the instruction. This displacement is relative to the current Program Counter (PC), a general-purpose register, or a register pair. In branch instructions, the displacement is always relative to the current value of the PC Register. For example, the following instruction causes an unconditional branch to an address 10 ahead of the current PC. BR *+10 Index Mode
In another example, the operand resides in memory. Its address is obtained by adding a displacement encoded in the instruction to the contents of register r5. The address calculation does not modify the contents of register r5. LOADW 12(R5), R6 The following example calculates the address of a source operand by adding a displacement of 4 to the contents of a register pair (r5, r4) and loads this operand into the register pair (r7, r6). r7 receives the high word of the operand, and r6 receives the low word. LOADD 4(r5, r4), (r7, r6) In index mode, the operand address is calculated with a base address held in either R12 or R13. The CFG.SR bit must be clear to use this mode. For relative mode operands, the memory address is calculated by adding the value of a register pair and a displacement to the base address. The displacement can be a 14 or 20-bit unsigned value, which is encoded in the instruction. For absolute mode operands, the memory address is calculated by adding a 20-bit absolute address encoded in the instruction to the base address.
In the following example, the operand address is the sum of the displacement 4, the contents of the register pair (r5,r4), and the base address held in register r12. The word at this address is loaded into register r6. LOADW [r12]4(r5, r4), r6 Absolute Mode In absolute mode, the operand is located in memory, and its address is encoded in the instruction (normally 20 or 24 bits). For example, the following instruction loads the byte at address 4000 into the lower 8 bits of register r6. LOADB 4000, r6 For additional information on the addressing modes, see the CompactRISC CR16C Programmer's Reference Manual.
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5.6
STACKS
5.7
INSTRUCTION SET
A stack is a last-in, first-out data structure for dynamic storage of data and addresses. A stack consists of a block of memory used to hold the data and a pointer to the top of the stack. As more data is pushed onto a stack, the stack grows downward in memory. The CR16C supports two types of stacks: the interrupt stack and program stacks.
Table 6 lists the operand specifiers for the instruction set, and Table 7 is a summary of all instructions. For each instruction, the table shows the mnemonic and a brief description of the operation performed.
In the mnemonic column, the lower-case letter "i" is used to indicate the type of integer that the instruction operates on, either "B" for byte or "W" for word. For example, the notation 5.6.1 Interrupt Stack ADDi for the "add" instruction means that there are two The processor uses the interrupt stack to save and restore forms of this instruction, ADDB and ADDW, which operate the program state during the exception handling. Hardware on bytes and words, respectively. automatically pushes this data onto the interrupt stack before entering an exception handler. When the exception Similarly, the lower-case string "cond" is used to indicate the handler returns, hardware restores the processor state with type of condition tested by the instruction. For example, the data popped from the interrupt stack. The interrupt stack notation Jcond represents a class of conditional jump instructions: JEQ for Jump on Equal, JNE for Jump on Not pointer is held in the ISP register. Equal, etc. For detailed information on all instructions, see 5.6.2 Program Stack the CompactRISC CR16C Programmer's Reference ManuThe program stack is normally used by software to save and al. restore register values on subroutine entry and exit, hold loTable 6 Key to Operand Specifiers cal and temporary variables, and hold parameters passed between the calling routine and the subroutine. The only Operand Specifier Description hardware mechanisms which operate on the program stack are the PUSH, POP, and POPRET instructions. abs Absolute address 5.6.3 User and Supervisor Stack Pointers disp imm Iposition Rbase Rdest Rindex RPbase, RPbasex RPdest RPlink Rposition Rproc Rprocd RPsrc RPtarget Rsrc, Rsrc1, Rsrc2 To support multitasking operating systems, support is provided for two program stack pointers: a user stack pointer and a supervisor stack pointer. When the PSR.U bit is clear, the SP register is used for all program stack operations. This is the default mode when the user/supervisor protection mechanism is not used, and it is the supervisor mode when protection is used. When the PSR.U bit is set, the processor is in user mode, and the USP register is used as the program stack pointer. User mode can only be entered using the JUSR instruction, which performs a jump and sets the PSR.U bit. User mode is exited when an exception is taken and re-entered when the exception handler returns. In user mode, the LPRD instruction cannot be used to change the state of processor registers (such as the PSR). Displacement (numeric suffix indicates number of bits) Immediate operand (numeric suffix indicates number of bits) Bit position in memory Base register (relative mode) Destination register Index register Base register pair (relative mode) Destination register pair Link register pair Bit position in register 16-bit processor register 32-bit processor register Source register pair Target register pair Source register
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Table 7 Instruction Set Summary Mnemonic MOVi MOVXB MOVZB MOVXW MOVZW MOVD Operands Rsrc/imm, Rdest Rsrc, Rdest Rsrc, Rdest Rsrc, RPdest Rsrc, RPdest imm, RPdest RPsrc, RPdest ADD[U]i ADDCi ADDD MACQWa MACSWa MACUWa MULi MULSB MULSW MULUW SUBi SUBD SUBCi CMPi CMPD BEQ0i BNE0i ANDi ANDD ORi ORD Scond XORi XORD ASHUi Rsrc/imm, Rdest Rsrc/imm, Rdest RPsrc/imm, RPdest Rsrc1, Rsrc2, RPdest Rsrc1, Rsrc2, RPdest Rsrc1, Rsrc2, RPdest Rsrc/imm, Rdest Rsrc, Rdest Rsrc, RPdest Rsrc, RPdest Rsrc/imm, Rdest RPsrc/imm, RPdest Rsrc/imm, Rdest Rsrc/imm, Rdest RPsrc/imm, RPdest Rsrc, disp Rsrc, disp Rsrc/imm, Rdest RPsrc/imm, RPdest Rsrc/imm, Rdest RPsrc/imm, RPdest Rdest Rsrc/imm, Rdest RPsrc/imm, RPdest Rsrc/imm, Rdest Move Move with sign extension Move with zero extension Move with sign extension Move with zero extension Move immediate to register-pair Move between register-pairs Add Add with carry Add with RP or immediate. Multiply signed Q15: RPdest := RPdest + (Rsrc1 x Rsrc2) Multiply signed and add result: RPdest := RPdest + (Rsrc1 x Rsrc2) Multiply unsigned and add result: RPdest := RPdest + (Rsrc1 x Rsrc2) Multiply: Rdest(8) := Rdest(8) x Rsrc(8)/imm Rdest(16) := Rdest(16) x Rsrc(16)/imm Multiply: Rdest(16) := Rdest(8) x Rsrc(8) Multiply: RPdest := RPdest(16) x Rsrc(16) Multiply: RPdest := RPdest(16) x Rsrc(16); Subtract: (Rdest := Rdest - Rsrc/imm) Subtract: (RPdest := RPdest - RPsrc/imm) Subtract with carry: (Rdest := Rdest - Rsrc/imm) Compare Rdest - Rsrc/imm Compare RPdest - RPsrc/imm Compare Rsrc to 0 and branch if EQUAL Compare Rsrc to 0 and branch if NOT EQUAL Logical AND: Rdest := Rdest & Rsrc/imm Logical AND: RPdest := RPsrc & RPsrc/imm Logical OR: Rdest := Rdest | Rsrc/imm Logical OR: Rdest := RPdest | RPsrc/imm Save condition code as boolean Logical exclusive OR: Rdest := Rdest ^ Rsrc/imm Logical exclusive OR: Rdest := RPdest ^ RPsrc/imm Arithmetic left/right shift Description
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Table 7 Instruction Set Summary Mnemonic ASHUD LSHi LSHD SBITi Operands Rsrc/imm, RPdest Rsrc/imm, Rdest Rsrc/imm, RPdest Iposition, disp(Rbase) Iposition, disp(RPbase) Iposition, (Rindex)disp(RPbasex) Iposition, abs Iposition, (Rindex)abs CBITi Iposition, disp(Rbase) Iposition, disp(RPbase) Iposition, (Rindex)disp(RPbasex) Iposition, abs Iposition, (Rindex)abs TBIT TBITi Rposition/imm, Rsrc Iposition, disp(Rbase) Iposition, disp(RPbase) Iposition, (Rindex)disp(RPbasex) Iposition, abs Iposition, (Rindex)abs LPR LPRD SPR SPRD Bcond Rsrc, Rproc RPsrc, Rprocd Rproc, Rdest Rprocd, RPdest disp9 disp17 disp24 BAL BR RPlink, disp24 disp9 disp17 disp24 EXCP Jcond JAL vector RPtarget RA, RPtarget, RPlink, RPtarget JUMP JUSR www.national.com RPtarget RPtarget 22 Jump Jump and set PSR.U Trap (vector) Conditional Jump to a large address Jump and link to a large address Branch and link Branch Load processor register Load double processor register Store processor register Store 32-bit processor register Conditional branch Test a bit in a register Test a bit in memory Clear a bit in memory Description Arithmetic left/right shift Logical left/right shift Logical left/right shift Set a bit in memory (Because this instruction treats the destination as a readmodify-write operand, it not be used to set bits in writeonly registers.)
CP3UB17
Table 7 Instruction Set Summary Mnemonic RETX PUSH POP POPRET LOADi imm, Rsrc, RA imm, Rdest, RA imm, Rdest, RA disp(Rbase), Rdest abs, Rdest (Rindex)abs, Rdest (Rindex)disp(RPbasex), Rdest disp(RPbase), Rdest LOADD disp(Rbase), Rdest abs, Rdest (Rindex)abs, Rdest (Rindex)disp(RPbasex), Rdest disp(RPbase), Rdest STORi Rsrc, disp(Rbase) Rsrc, disp(RPbase) Rsrc, abs Rsrc, (Rindex)disp(RPbasex) Rsrc, (Rindex)abs STORD RPsrc, disp(Rbase) RPsrc, disp(RPbase) RPsrc, abs RPsrc, (Rindex)disp(RPbasex) RPsrc, (Rindex)abs STOR IMM imm4, disp(Rbase) imm4, disp(RPbase) imm4, (Rindex)disp(RPbasex) imm4, abs imm4, (Rindex)abs LOADM LOADMP STORM imm3 imm3 STORM imm3 Load 1 to 8 registers (R2-R5, R8-R11) from memory starting at (R0) Load 1 to 8 registers (R2-R5, R8-R11) from memory starting at (R1, R0) Store 1 to 8 registers (R2-R5, R8-R11) to memory starting at (R2) Operands Return from exception Push "imm" number of registers on user stack, starting with Rsrc and possibly including RA Restore "imm" number of registers from user stack, starting with Rdest and possibly including RA Restore registers (similar to POP) and JUMP RA Load (register relative) Load (absolute) Load (absolute index relative) Load (register relative index) Load (register pair relative) Load (register relative) Load (absolute) Load (absolute index relative) Load (register pair relative index) Load (register pair relative) Store (register relative) Store (register pair relative) Store (absolute) Store (register pair relative index) Store (absolute index) Store (register relative) Store (register pair relative) Store (absolute) Store (register pair index relative) Store (absolute index relative) Store unsigned 4-bit immediate value extended to operand length in memory Description
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Table 7 Instruction Set Summary Mnemonic STORMP DI EI EIWAIT NOP WAIT imm3 Operands Description Store 1 to 8 registers (R2-R5, R8-R11) to memory starting at (R7,R6) Disable maskable interrupts Enable maskable interrupts Enable maskable interrupts and wait for interrupt No operation Wait for interrupt
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6.0
Memory
The CP3UB17 supports a uniform 16M-byte linear address are reserved and must not be read or written. The BIU space. Table 8 lists the types of memory and peripherals zones are regions of the address space that share the same that occupy this memory space. Unlisted address ranges control bits in the Bus Interface Unit (BIU). Table 8 CP3UB17 Memory Map Start Address 00 0000h 04 0000h 0E 0000h 0E 2000h 0E 8000h 0E 9200h 0E C000h 0E E800h 0E EC00h 0E F000h 0E F140h 0E F180h 0E F200h 10 0000h 40 0000h 80 0000h FF 0000h FF FB00h FF FC00h End Address 03 FFFFh 0D FFFFh 0E 1FFFh 0E 7FFFh 0E 91FFh 0E BFFFh 0E E7FFh 0E EBFFh 0E EFFFh 0E F13Fh 0E F17Fh 0E F1FFh 0F FFFFh 3F FFFFh 7F FFFFh FE FFFFh FF FAFFh FF FBFFh FF FFFFh Size in Bytes 256K 640K 8K 24K 4.5K 11.5K 10K 1K 1K 320 64 128 67.5K 3072K 4096K 8128K 64256 256 1K Description On-chip Flash Program Memory, including Boot Memory Reserved On-chip Flash Data Memory Reserved Reserved Reserved System RAM Reserved Reserved Reserved Reserved Reserved Reserved Reserved External Memory Zone 1 External Memory Zone 2 BIU Peripherals I/O Expansion Peripherals and Other I/O Ports I/O Zone N/A Static Zone 1 Static Zone 2 N/A BIU Zone Static Zone 0 (mapped internally in IRE and ERE mode; mapped to the external bus in DEV mode)
6.1
OPERATING ENVIRONMENT
The operating environment controls whether external memory is supported and whether the reset vector jumps to a code space intended to support In-System Programming (ISP). Up to 8M of external memory space is available. The operating mode of the device is controlled by the states on the ENV2:0 pins at reset, as shown in Table 9. Table 9 Operating Environment Selection ENV2:0 x10 111 011 000 Operating Environment In-System-Programming (ISP) mode Internal ROM enabled (IRE) or ISP mode External ROM enabled (ERE) mode Development (DEV) mode
When ENV2:0 = 111, IRE mode is selected unless the EMPTY bits in the Protection word indicate that the program flash memory is empty (unprogrammed), in which case ISP mode is selected. See Section 8.4.2 for more details. The ENV2 pin is only available on the 100-pin packages, therefore it is not possible to enter the ERE or DEV environments on the 48-pin versions of the CP3UB17. In the DEV environment, the on-chip flash memory is disabled, and the corresponding region of the address space is mapped to external memory.
6.2
BUS INTERFACE UNIT (BIU)
Internal pullups on the ENV2:0 pins select IRE mode or ISP mode if these pins are allowed to float.
The BIU controls the interface between the CPU core bus and those on-chip modules which are mapped into BIU zones. These on-chip modules are the flash program memory and the I/O zone. The BIU controls the configured parameters for bus access (such as the number of wait states for memory access) and issues the appropriate bus signals for the requested access. www.national.com
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6.3
BUS CYCLES
6.4.1
BIU Configuration Register (BCFG)
There are four types of data transfer bus cycles: Normal read Fast read Early write Late write
The BCFG register is a byte-wide, read/write register that selects early-write or late-write bus cycles. At reset, the register is initialized to 07h. The register format is shown below. 7 Reserved 3 2 1 1 1 0 EWR
The type of data cycle used in a particular transaction depends on the type of CPU operation (a write or a read), the type of memory or I/O being accessed, and the access type programmed into the BIU control registers (early/late write EWR or normal/fast read). For read operations, a basic normal read takes two clock cycles, and a fast-read bus cycle takes one clock cycle. Normal read bus cycles are enabled by default after reset.
The Early Write bit controls write cycle timing. 0 - Late-write operation (2 clock cycles to write). 1 - Early-write operation.
At reset, the BCFG register is initialized to 07h, which seFor write operations, a basic late-write bus cycle takes two lects early-write operation. However, late-write operation is clock cycles, and a basic early-write bus cycle takes three required for normal device operation, so software must clock cycles. Early-write bus cycles are enabled by default change the register value to 06h. Bits 1 and 2 of this register after reset. However, late-write bus cycles are needed for must always be set when writing to this register. ordinary write operations, so this configuration must be 6.4.2 I/O Zone Configuration Register (IOCFG) changed by software (see Section 6.4.1). The IOCFG register is a word-wide, read/write register that In certain cases, one or more additional clock cycles are controls the timing and bus characteristics of accesses to added to a bus access cycle. There are two types of addi- the 256-byte I/O Zone memory space (FF FB00h to FF tional clock cycles for ordinary memory accesses, called in- FBFFh). The registers associated with Port B and Port C reternal wait cycles (TIW) and hold (Thold) cycles. side in the I/O memory array. At reset, the register is initialA wait cycle is inserted in a bus cycle just after the memory ized to 069Fh. The register format is shown below. address has been placed on the address bus. This gives the accessed memory more time to respond to the transaction 7 6 5 4 3 2 0 request. BW Reserved HOLD WAIT A hold cycle is inserted at the end of a bus cycle. This holds the data on the data bus for an extended number of clock cycles. 15 10 9 8
6.4
BIU CONTROL REGISTERS
Reserved
IPST
Res.
The BIU has a set of control registers that determine how many wait cycles and hold cycles are to be used for accessing memory. During initialization of the system, these regis- WAIT ters should be programmed with appropriate values so that the minimum allowable number of cycles is used. This number varies with the clock frequency. There are five BIU control registers, as listed in Table 10. These registers control the bus cycle configuration used for HOLD accessing the various on-chip memory types. Table 10 Bus Control Registers Name BCFG IOCFG SZCFG0 SZCFG1 SZCFG2 Address FF F900h FF F902h FF F904h FF F906h FF F908h Description BW BIU Configuration Register I/O Zone Configuration Register Static Zone 0 Configuration Register Static Zone 1 Configuration Register Static Zone 2 Configuration Register
IPST
The Memory Wait Cycles field specifies the number of TIW (internal wait state) clock cycles added for each memory access, ranging from 000 binary for no additional TIW wait cycles to 111 binary for seven additional TIW wait cycles. The Memory Hold Cycles field specifies the number of Thold clock cycles used for each memory access, ranging from 00b for no Thold cycles to 11b for three Thold clock cycles. The Bus Width bit defines the bus width of the IO Zone. 0 - 8-bit bus width. 1 - 16-bit bus width (default) The Post Idle bit controls whether an idle cycle follows the current bus cycle, when the next bus cycle accesses a different zone. No idle cycles are required for on-chip accesses. 0 - No idle cycle (recommended). 1 - Idle cycle.
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6.4.3
Static Zone 0 Configuration Register (SZCFG0) IPRE
The SZCFG0 register is a word-wide, read/write register that controls the timing and bus characteristics of Zone 0 memory accesses. Zone 0 is used for the on-chip flash memory (including the boot area, program memory, and data memory). At reset, the register is initialized to 069Fh. The register format is shown below. 7 BW 6 WBR 5 RBE 4 3 2 WAIT 0 6.4.4
The Preliminary Idle bit controls whether an idle cycle is inserted prior to the current bus cycle, when the new bus cycle accesses a different zone. No idle cycles are required for onchip accesses. 0 - No idle cycle (recommended). 1 - Idle cycle inserted. Static Zone 1 Configuration Register (SZCFG1)
HOLD
The SZCFG1 register is a word-wide, read/write register that controls the timing and bus characteristics for off-chip accesses selected with the SEL1 output signal. At reset, the register is initialized to 069Fh. The register format is shown below.
15 Reserved
12
11 FRE
10
9
8 Res. 7 BW 6 WBR 5 RBE 4 3 2 WAIT 0 HOLD
IPRE IPST
WAIT
HOLD
RBE
WBR
BW
FRE
IPST
The Memory Wait field specifies the number of TIW (internal wait state) clock cycles added for each memory access, ranging from 000b for no additional TIW wait cycles to 111b for seven additional TIW wait cycles. These bits are ignored if the SZCFG0.FRE bit is set. The Memory Hold field specifies the number of Thold clock cycles used for each memory access, ranging from 00b for no Thold cycles to 11b for three Thold clock cycles. These bits are ignored if the SZCFG0.FRE bit is set. The Read Burst Enable enables burst cycles on 16-bit reads from 8-bit bus width regions of the address space. Because the flash program memory is required to be 16-bit bus width, the RBE bit is a don't care bit. This bit is ignored when the SZCFG0.FRE bit is set. 0 - Burst read disabled. 1 - Burst read enabled. The Wait on Burst Read bit controls if a wait state is added on burst read transaction. This bit is ignored, when SZCFG0.FRE bit is set or when SZCFG0.RBE is clear. 0 - No TBW on burst read cycles. 1 - One TBW on burst read cycles. The Bus Width bit controls the bus width of the zone. The flash program memory must be configured for 16-bit bus width. 0 - 8-bit bus width. 1 - 16-bit bus width (required). The Fast Read Enable bit controls whether fast read bus cycles are used. A fast read operation takes one clock cycle. A normal read operation takes at least two clock cycles. 0 - Normal read cycles. 1 - Fast read cycles. The Post Idle bit controls whether an idle cycle follows the current bus cycle, when the next bus cycle accesses a different zone. No idle cycles are required for on-chip accesses. 0 - No idle cycle (recommended). 1 - Idle cycle inserted.
15 Reserved
12
11 FRE
10
9
8 Res.
IPRE IPST
WAIT
HOLD
RBE
WBR
BW
FRE
The Memory Wait field specifies the number of TIW (internal wait state) clock cycles added for each memory access, ranging from 000b for no additional TIW wait cycles to 111b for seven additional TIW wait cycles. These bits are ignored if the SZCFG1.FRE bit is set. The Memory Hold field specifies the number of Thold clock cycles used for each memory access, ranging from 00b for no Thold cycles to 11b for three Thold clock cycles. These bits are ignored if the SZCFG1.FRE bit is set. The Read Burst Enable enables burst cycles on 16-bit reads from 8-bit bus width regions of the address space. This bit is ignored when the SZCFG1.FRE bit is set or the SZCFG1.BW is clear. 0 - Burst read disabled. 1 - Burst read enabled. The Wait on Burst Read bit controls if a wait state is added on burst read transaction. This bit is ignored, when SZCFG1.FRE bit is set or when SZCFG1.RBE is clear. 0 - No TBW on burst read cycles. 1 - One TBW on burst read cycles. The Bus Width bit controls the bus width of the zone. 0 - 8-bit bus width. 1 - 16-bit bus width. The Fast Read Enable bit controls whether fast read bus cycles are used. A fast read operation takes one clock cycle. A normal read operation takes at least two clock cycles. 0 - Normal read cycles. 1 - Fast read cycles.
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IPST
IPRE
6.4.5
The Post Idle bit controls whether an idle cycle FRE follows the current bus cycle, when the next bus cycle accesses a different zone. 0 - No idle cycle. 1 - Idle cycle inserted. The Preliminary Idle bit controls whether an idle cycle is inserted prior to the current bus IPST cycle, when the new bus cycle accesses a different zone. 0 - No idle cycle. 1 - Idle cycle inserted. IPRE Static Zone 2 Configuration Register (SZCFG2)
The SZCFG2 register is a word-wide, read/write register that controls the timing and bus characteristics for off-chip accesses selected with the SEL2 output signal. At reset, the register is initialized to 069Fh. The register format is shown below. 7 BW 6 WBR 5 RBE 4 3 2 WAIT 0
The Fast Read Enable bit controls whether fast read bus cycles are used. A fast read operation takes one clock cycle. A normal read operation takes at least two clock cycles. 0 - Normal read cycles. 1 - Fast read cycles. The Post Idle bit controls whether an idle cycle follows the current bus cycle, when the next bus cycle accesses a different zone. 0 - No idle cycle. 1 - Idle cycle inserted. The Preliminary Idle bit controls whether an idle cycle is inserted prior to the current bus cycle, when the new bus cycle accesses a different zone. 0 - No idle cycle. 1 - Idle cycle inserted.
6.5
WAIT AND HOLD STATES
HOLD
The number of wait cycles and hold cycles inserted into a bus cycle depends on whether it is a read or write operation, the type of memory or I/O being accessed, and the control register settings. 6.5.1 Flash Program/Data Memory
15 Reserved
12
11 FRE
10 IPRE
9 IPST
8 Res.
WAIT
HOLD
RBE
WBR
BW
The Memory Wait field specifies the number of TIW (internal wait state) clock cycles added for each memory access, ranging from 000b for no additional TIW wait cycles to 111b for seven additional TIW wait cycles. These bits are ignored if the SZCFG2.FRE bit is set. The Memory Hold field specifies the number of Thold clock cycles used for each memory access, ranging from 00b for no Thold cycles to 11b for three Thold clock cycles. These bits are ignored if the SZCFG2.FRE bit is set. The Read Burst Enable enables burst cycles on 16-bit reads from 8-bit bus width regions of the address space. This bit is ignored when the SZCFG2.FRE bit is set or the SZCFG2.BW is clear. 0 - Burst read disabled. 1 - Burst read enabled. The Wait on Burst Read bit controls if a wait state is added on burst read transaction. This bit is ignored, when SZCFG2.FRE bit is set or when SZCFG2.RBE is clear. 0 - No TBW on burst read cycles. 1 - One TBW on burst read cycles. The Bus Width bit controls the bus width of the zone. 0 - 8-bit bus width. 1 - 16-bit bus width.
When the CPU accesses the Flash program and data memory (address ranges 000000h-03FFFFh and 0E0000h- 0E1FFFh), the number of added wait and hold cycles depends on the type of access and the BIU register settings. In fast-read mode (SZCFG0.FRE=1), a read operation is a single cycle access. This limits the maximum CPU operating frequency to 24 MHz. For a read operation in normal-read mode (SZCFG0.FRE=0), the number of inserted wait cycles is specified in the SZCFG0.WAIT field. The total number of wait cycles is the value in the WAIT field plus 1, so it can range from 1 to 8. The number of inserted hold cycles is specified in the SCCFG0.HOLD field, which can range from 0 to 3. For a write operation in fast read mode (SZCFG0.FRE=1), the number of inserted wait cycles is 1. No hold cycles are used. For a write operation normal read mode (SZCFG0.FRE=0), the number of wait cycles is equal to the value written to the SZCFG0.WAIT field plus 1 (in the late write mode) or 2 (in the early write mode). The number of inserted hold cycles is equal to the value written to the SCCFG0.HOLD field, which can range from 0 to 3. 6.5.2 RAM Memory
Read and write accesses to on-chip RAM is performed within a single cycle, without regard to the BIU settings. The RAM address is in the range of 0E 8000h-0E 91FFh and 0E C000h-0E EBFFh. 6.5.3 Access to Peripherals
When the CPU accesses on-chip peripherals in the range of 0E F000h-0E F1FFh and FF 0000h-FF FBFFh, one wait cycle and one preliminary idle cycle is used. No hold cycles are used. The IOCFG register determines the access timing for the address range FF FB00h-FF FBFFh. www.national.com 28
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7.0
System Configuration Registers
MISC_IO_SPEED The MISC_IO_SPEED bit controls the slew rate of the output drivers for the ENV[2:0], RDY, RFDATA, and TDO pins. To minimize noise, the slow slew rate is recommended. 0 - Fast slew rate. 1 - Slow slew rate. MEM_IO_SPEED The MEM_IO_SPEED bit controls the slew rate of the output drivers for the A[21:0], RD, SEL[2:1], and WR[1:0] pins. Memory speeds for the CP3UB17 are characterized with fast slew rate. Slow slew rate reduces the available memory access time by 5 ns. 0 - Fast slew rate. 1 - Slow slew rate.
The system configuration registers control and provide status for certain aspects of device setup and operation, such as indicating the states sampled from the ENV[2:0] inputs. The system configuration registers are listed in Table 11. Table 11 System Configuration Registers Name MCFG MSTAT Address FF F910h FF F914h Description Module Configuration Register Module Status Register
7.1
MODULE CONFIGURATION REGISTER (MCFG)
7.2
MODULE STATUS REGISTER (MSTAT)
The MCFG register is a byte-wide, read/write register that selects the clock output features of the device. The register must be written in active mode only, not in power save, HALT, or IDLE mode. However, the register contents are preserved during all power modes. The MCFG register format is shown below. 7 6 5 4 3 2 1 0
The MSTAT register is a byte-wide, read-only register that indicates the general status of the device. The MSTAT register format is shown below. 7 5 4 3 2 1 0
Reserved DPGMBUSY PGMBUSY OENV2 OENV1 OENV0
The Operating Environment bits hold the states sampled from the ENV[2:0] input pins MEM_IO MISC_IO USB SCLK MCLK PLLCLK EXI Res. at reset. These states are controlled by exter_SPEED _SPEED _ENABLE OE OE OE OE nal hardware at reset and are held constant in the register until the next reset. PGMBUSY The Flash Programming Busy bit is automatiEXIOE The EXIOE bit controls whether the external cally set when either the program memory or bus is enabled in the IRE environment for imthe data memory is being programmed or plementing the I/O Zone (FF FB00h-FF erased. It is clear when neither of the memoFBFFh). ries is busy. When this bit is set, software must 0 - External bus disabled. not attempt to program or erase either of 1 - External bus enabled. these two memories. This bit is a copy of the PLLCLKOE The PLLCLKOE bit controls whether the PLL FMBUSY bit in the FMSTAT register. clock is driven on the ENV0/PLLCLK pin. 0 - Flash memory is not busy. 0 - ENV0/PLLCLK pin is high impedance. 1 - Flash memory is busy. 1 - PLL clock driven on ENV0/PLLCLK. DPGMBUSY The Data Flash Programming Busy indicates MCLKOE The MCLKOE bit controls whether the Main that the flash data memory is being erased or Clock is driven on the ENV1/CPUCLK pin. a pipelined programming sequence is current0 - ENV1/CPUCLK pin is high impedance. ly ongoing. Software must not attempt to per1 - Main Clock is driven on ENV1/CPUCLK. form any write access to the flash program SCLKOE The SCLKOE bit controls whether the Slow memory at this time, without also polling the Clock is driven on the ENV2/SLOWCLK pin. FSMSTAT.FMFULL bit in the flash memory in0 - ENV2/SLOWCLK pin is high impedance. terface. The DPGMBUSY bit is a copy of the 1 - Slow Clock driven on ENV2/SLOWCLK. FMBUSY bit in the FSMSTAT register. USB_ENABLE The USB_ENABLE bit can be used to force 0 - Flash data memory is not busy. an external USB transceiver into its low-power 1 - Flash data memory is busy. mode. The power mode is dependent on the USB controller status, the USB_ENABLE bit in the Function Word (see Section 8.4.1), and the USB_ENABLE bit in the MCFG register. 0 - External USB transceiver forced into lowpower mode. 1 - Transceiver power mode dependent on USB controller status and programming of the Function Word. (This is the state of the USB_ENABLE bit after reset.)
OENV[2:0]
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8.0
Flash Memory
The flash memory consists of the flash program memory and the flash data memory. The flash program memory is further divided into the Boot Area and the Code Area.
default (after reset) all bits in the FM0WER, FM1WER, and FSM0WER registers are cleared, which disables write access by the CPU to all sections. Write access to a section is A special protection scheme is applied to the lower portion enabled by setting the corresponding write enable bit. After of the flash program memory, called the Boot Area. The completing a programming or erase operation, software Boot Area always starts at address 0 and ranges up to a should clear all write enable bits to protect the flash program programmable end address. The maximum boot area ad- memory against any unintended writes. dress which can be selected is 00 1BFFh. The intended use 8.1.2 Global Protection of this area is to hold In-System-Programming (ISP) rouThe WRPROT field in the Protection Word controls global tines or essential application routines. The Boot Area is alwrite protection. The Protection Word is located in a special ways protected against CPU write access, to avoid flash memory outside of the CPU address space. If a majorunintended modifications. ity of the bits in the 3-bit WRPROT field are clear, write proThe Code Area is intended to hold the application code and tection is enabled. Enabling this mode prevents the CPU constant data. The Code Area begins with the next byte af- from writing to flash memory. ter the Boot Area. Table 12 summarizes the properties of The RDPROT field in the Protection Word controls global the regions of flash memory mapped into the CPU address read protection. If a majority of the bits in the 3-bit RDPROT space. field are clear, read protection is enabled. Enabling this Table 12 Flash Memory Areas mode prevents reading by an external debugger through the serial debug interface or by an external flash programmer. Read Area Address Range Write Access CPU read access is not affected by the RDPROT bits. Access
8.2
FLASH MEMORY ORGANIZATION
Boot Area
0-BOOTAREA - 1
Yes
No Write access only if section write enable bit is set and global write protection is disabled. Write access only if section write enable bit is set and global write protection is disabled.
Code Area
BOOTAREA-03 FFFFh
Yes
Each of the flash memories are divided into main blocks and information blocks. The main blocks hold the code or data used by application software. The information blocks hold factory parameters, protection settings, and other devicespecific data. The main blocks are mapped into the CPU address space. The information blocks are accessed indirectly through a register-based interface. Separate sets of registers are provided for accessing flash program memory (FM registers) and flash data memory (FSM registers). The flash program memory consists of two main blocks and two data blocks, as shown in Table 13. The flash data memory consists of one main block and one information block. Table 13 Flash Memory Blocks Name Main Block 0 Address Range 00 0000h-01 FFFFh (CPU address space) 000h-07Fh (address register) 02 0000h-03 FFFFh (CPU address space) 080h-0FFh (address register) 0E 0000h-0E 1FFFh (CPU address space) Function Flash Program Memory Function Word, Factory Parameters Flash Program Memory Protection Word, User Data Flash Data Memory
Data Area
0E 0000h-0E 1FFFh
Yes
8.1
FLASH MEMORY PROTECTION
Information Block 0 Main Block 1 Information Block 1 Main Block 2
The memory protection mechanisms provide both global and section-level protection. Section-level protection against CPU writes is applied to individual 8K-byte sections of the flash program memory and 512-byte sections of the flash data memory. Section-level protection is controlled through read/write registers mapped into the CPU address space. Global write protection is applied at the device level, to disable flash memory writes by the CPU. Global write protection is controlled by the encoding of bits stored in the flash memory array. 8.1.1 Section-Level Protection
Information 000h-07Fh User Data (address register) Block 2 Each bit in the Flash Memory Write Enable (FM0WER and FM1WER) registers enables or disables write access to a corresponding section of flash program memory. Write ac- 8.2.1 Main Block 0 and 1 cess to the flash data memory is controlled by the bits in the Main Block 0 and Main Block 1 hold the 256K-byte program Flash Slave Memory Write Enable (FSM0WER) register. By space, which consists of the Boot Area and Code Area. www.national.com 30
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Each block consists of sixteen 8K-byte sections. Write access by the CPU to Main Block 0 and Main Block 1 is controlled by the corresponding bits in the FM0WER and FM1WER registers, respectively. The least significant bit in each register controls the section at the lowest address. 8.2.2 Information Block 0
8.2.5
Information Block 2
Information Block 2 contains 128 bytes, which can be used to store user data. The CPU can always read Information Block 2. The CPU can write Information Block 2 only when global write protection is disabled. Erasing Information Block 2 also erases Main Block 2.
Information Block 0 contains 128 bytes, of which one 16-bit word has a dedicated function, called the Function Word. The Function Word resides at address 07Eh. It controls the power mode of an external USB transceiver. The remaining Information Block 0 locations are used to hold factory parameters.
8.3
FLASH MEMORY OPERATIONS
Flash memory programming (erasing and writing) can be performed on the flash data memory while the CPU is executing out of flash program memory. Although the CPU can execute out of flash data memory, it cannot erase or write the flash program memory while executing from flash data Software only has read access to Information Block 0 memory. To erase or write the flash program memory, the through a register-based interface. The Function Word and CPU must be executing from the on-chip static RAM or offthe factory parameters are protected against CPU writes. chip memory. Table 14 shows the structure of Information Block 0. An erase operation is required before programming. An Table 14 Information Block 0 erase operation sets all of the bits in the erased region. A programming operation clears selected bits. Address Read The programming mechanism is pipelined, so that a new Name Write Access Range Access write request can be loaded while a previous request is in Function Word Other (Used for Factory Parameters) 8.2.3 07Eh-07Fh Yes 000h-07Dh No progress. When the FMFULL bit in the FMSTAT or FSMSTAT register is clear, the pipeline is ready to receive a new request. New requests may be loaded after checking only the FMFULL bit. 8.3.1 Main Block Read
Information Block 1
Information Block 1 contains 128 bytes, of which one 16-bit word has a dedicated function, called the Protection Word. The Protection Word resides at address 0FEh. It controls the global protection mechanisms and the size of the Boot Area. The Protection Word can be written by the CPU, however the changes only become valid after the next device reset. The remaining Information Block 1 locations can be used to store other user data. Erasing Information Block 1 also erases Main Block 1. Table 15 shows the structure of the Information Block 1. Table 15 Information Block 1 Name Protection Word Other (User Data) Address Range 0FEh-0FFh Yes 080h-0FDh Read Access Write Access Write access only if section write enable bit is set and global write protection is disabled.
Read accesses from flash program memory can only occur when the flash program memory is not busy from a previous write or erase operation. Read accesses from the flash data memory can only occur when both the flash program memory and the flash data memory are not busy. Both byte and word read operations are supported. 8.3.2 Information Block Read
Information block data is read through the register-based interface. Only word read operations are supported and the read address must be word-aligned (LSB = 0). The following steps are used to read from an information block: 1. Load the word address in the Flash Memory Information Block Address (FMIBAR) or Flash Slave Memory Information Block Address (FSMIBAR) register. 2. Read the data word by reading out the Flash Memory Information Block Data (FMIBDR) or Flash Slave Memory Information Block Data (FSMIBDR) register. 8.3.3 Main Block Page Erase
8.2.4
Main Block 2
Main Block 2 holds the 8K-byte data area, which consists of sixteen 512-byte sections. Write access by the CPU to Main Block 2 is controlled by the corresponding bits in the FSM0WER register. The least significant bit in the register controls the section at the lowest address. 3. Set the Page Erase (PER) bit. The PER bit is in the FM-
A flash erase operation sets all of the bits in the erased region. Pages of a main block can be individually erased if their write enable bits are set. This method cannot be used to erase the boot area, if defined. Each page in Main Block 0 and 1 consists of 1024 bytes (512 words). Each page in Main Block 2 consists of 512 bytes (256 words). To erase a page, the following steps are performed: 1. Verify that the Flash Memory Busy (FMBUSY) bit is clear. The FMBUSY bit is in the FMSTAT or FSMSTAT register. 2. Prevent accesses to the flash memory while erasing is in progress. CTRL or FSMCTRL register. www.national.com
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4. Write to an address within the desired page. 5. Wait until the FMBUSY bit becomes clear again. 6. Check the Erase Error (EERR) bit to confirm successful erase of the page. The EERR bit is in the FMSTAT or FSMSTAT register. 7. Repeat steps 4 through 6 to erase additional pages. 8. Clear the PER bit. 8.3.4 Main Block Module Erase
A module erase operation can be used to erase an entire main block. All sections within the block must be enabled for writing. If a boot area is defined in the block, it cannot be erased. The following steps are performed to erase a main block: 1. Verify that the Flash Memory Busy (FMBUSY) bit is clear. The FMBUSY bit is in the FMSTAT or FSMSTAT register. 2. Prevent accesses to the flash memory while erasing is in progress. 3. Set the Module Erase (MER) bit. The MER bit is in the FMCTRL or FSMCTRL register. 4. Write to any address within the desired main block. 5. Wait until the FMBUSY bit becomes clear again. 6. Check the Erase Error (EERR) bit to confirm successful erase of the block. The EERR bit is in the FMSTAT or FSMSTAT register. 7. Clear the MER bit.
2. Prevent accesses to the flash memory while the write is in progress. 3. Set the Program Enable (PE) bit. The PE bit is in the FMCTRL or FSMCTRL register. 4. Write a word to the desired word-aligned address. This starts a new pipelined programming sequence. The FMBUSY bit becomes set while the write operation is in progress. The FMFULL bit in the FMSTAT or FSMSTAT register becomes set if a previous write operation is still in progress. 5. Wait until the FMFULL bit becomes clear. 6. Repeat steps 4 and 5 for additional words. 7. Wait until the FMBUSY bit becomes clear again. 8. Check the programming error (PERR) bit to confirm successful programming. The PERR bit is in the FMSTAT or FSMSTAT register. 9. Clear the Program Enable (PE) bit. 8.3.7 Information Block Write
Writing is only allowed when global write protection is disabled. Writing by the CPU is only allowed when the write enable bit is set for the sector which contains the word to be written. The CPU cannot write Information Block 0. Only word-wide write access to word-aligned addresses is supported. The following steps are performed to write a word:
1. Verify that the Flash Memory Busy (FMBUSY) bit is clear. The FMBUSY bit is in the FMSTAT or FSMSTAT register. 8.3.5 Information Block Module Erase 2. Prevent accesses to the flash memory while the write Erasing an information block also erases the corresponding is in progress. main block. If a boot area is defined in the main block, nei- 3. Set the Program Enable (PE) bit. The PE bit is in the ther block can be erased. Page erase is not supported for FMCTRL or FSMCTRL register. information blocks. The following steps are performed to 4. Write the desired target address into the FMIBAR or erase an information block: FSMIBAR register. 1. Verify that the Flash Memory Busy (FMBUSY) bit is 5. Write the data word into the FMIBDR or FSMIBDR register. This starts a new pipelined programming seclear. The FMBUSY bit is in the FMSTAT or FSMSTAT quence. The FMBUSY bit becomes set while the write register. operation is in progress. The FMFULL bit in the FM2. Prevent accesses to the flash memory while erasing is STAT or FSMSTAT register becomes set if a previous in progress. write operation is still in progress. 3. Set the Module Erase (MER) bit. The MER bit is in the 6. Wait until the FMFULL bit becomes clear. FMCTRL or FSMCTRL register. 4. Load the FMIBAR or FSMIBAR register with any ad- 7. Repeat steps 4 through 6 for additional words. dress within the block, then write any data to the FMIB- 8. Wait until the FMBUSY bit becomes clear again. 9. Check the programming error (PERR) bit to confirm DR or FSMIBDR register. successful programming. The PERR bit is in the FM5. Wait until the FMBUSY bit becomes clear again. STAT or FSMSTAT register. 6. Check the Erase Error (EERR) bit to confirm successful erase of the block. The EERR bit is in the FMSTAT or 10. Clear the Program Enable (PE) bit. FSMSTAT register. 8.4 INFORMATION BLOCK WORDS 7. Clear the MER bit. Two words in the information blocks are dedicated to hold 8.3.6 Main Block Write settings that affect the operation of the system: the Function Writing is only allowed when global write protection is dis- Word in Information Block 0 and the Protection Word in Inabled. Writing by the CPU is only allowed when the write en- formation Block 1. able bit is set for the sector which contains the word to be 8.4.1 Function Word written. The CPU cannot write the Boot Area. Only wordwide write access to word-aligned addresses is supported. The Function Word resides in the Information Block 0 at address 07Eh. At reset, the Function Word is copied into the The following steps are performed to write a word: FMAR0 register. 1. Verify that the Flash Memory Busy (FMBUSY) bit is clear. The FMBUSY bit is in the FMSTAT or FSMSTAT 15 1 0 register. Reserved USB_ENABLE www.national.com 32
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USB_ENABLE The USB_ENABLE bit can be used to force an external USB transceiver into its low-power mode. The power mode is dependent on the USB controller status, the USB_ENABLE bit in the MCFG register (see Section 7.1), and the USB_ENABLE bit in the Function Word. 0 - External USB transceiver forced into lowpower mode. ISPE 1 - Transceiver power mode dependent on USB controller status and programming of the Function Word. 8.4.2 Protection Word
The Protection Word resides in Information Block 1 at address 0FEh. At reset, the Protection Word is copied into the FMAR1 register. 15 13 12 10 9 7 6 4 3 1 0
WRPROT RDPROT ISPE
EMPTY BOOTAREA 1
ENV[1:0] inputs (see Section 6.1) are sampled high at reset and the EMPTY bits indicate the flash program memory is empty, the device will begin execution in mode. The device enters ISP mode without regard to the EMPTY status if ENV0 is driven low and ENV1 is driven high. The ISPE field indicates whether the Boot Area is used to hold In-System-Programming routines or user application routines. If a majority of the three ISPE bits are set, the Boot Area holds ISP routines. If majority of the ISPE bits are clear, the Boot Area holds user application routines. Table 17 summarizes all possible EMPTY, ISPE, and Boot Area settings and the corresponding start-up operation for each combination. In DEV mode, the EMPTY bit settings are ignored and the CPU always starts executing from address 0. Table 17 CPU Reset Behavior
BOOTAREA The BOOTAREA field specifies the size of the Boot Area. The Boot Area starts at address 0 and ends at the address specified by this field. The inverted bits of the BOOTAREA field count the number of 1024-byte blocks to be reserved as the Boot Area. The maximum Boot Area size is 7K bytes (address range 0 to 1BFFh). The end of the Boot Area defines the start of the Code Area. If the device starts in ISP mode and there is no Boot Area defined (encoding 111b), the device is kept in reset. Table 16 lists all possible boot area encodings. Table 16 Boot Area Encodings BOOT AREA 111 110 101 100 011 010 001 000 EMPTY Size of the Boot Area No Boot Area defined 1024 bytes 2048 bytes 3072 bytes 4096 bytes 5120 bytes 6144 bytes 7168 bytes Code Area Start Address 00 0000h 00 0400h
EMPTY
ISPE
Boot Area
Start-Up Operation Device starts in IRE/ ERE mode from Code Area start address Device starts in IRE/ ERE mode from Code Area start address Device starts in IRE/ ERE mode from address 0 Device starts in ISP mode from Code Area start address Device starts in ISP mode and is kept in its reset state
Not Empty
ISP
Defined
Not Empty
ISP
Not Defined
Not Empty
No ISP
Don't Care
Empty
ISP
Defined Not Defined Don't Care
Empty Empty
ISP No ISP
00 0800h 00 0C00h 00 1000h 00 1400h 00 1800h 00 1C00h WRPROT RDPROT The RDPROT field controls the global read protection mechanism for the on-chip flash program memory. If a majority of the three RDPROT bits are clear, the flash program memory is protected against read access from the serial debug interface or an external flash programmer. CPU read access is not affected by the RDPROT bits. If a majority of the RDPROT bits are set, read access is allowed. The WRPROT field controls the global write protection mechanism for the on-chip flash program memory. If a majority of the three WRPROT bits are clear, the flash program memory is protected against write access from any source and read access from the se-
The EMPTY field indicates whether the flash program memory has been programmed or should be treated as blank. If a majority of the three EMPTY bits are clear, the flash program memory is treated as programmed. If a majority of the EMPTY bits are set, the flash program memory is treated as empty. If the
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rial debug interface. If a majority of the WRPROT bits are set, write access is allowed.
Table 18 Flash Memory Interface Registers Program Memory FMRCV FF F962h FMAR0 FF F964h FMAR1 FF F966h FMAR2 FF F968h 8.5.1 Data Memory FSMRCV FF F762h FSMAR0 FF F764h FSMAR1 FF F766h FSMAR2 FF F768h Description Flash Memory Recovery Time Reload Register Flash Memory Auto-Read Register 0 Flash Memory Auto-Read Register 1 Flash Memory Auto-Read Register 2
8.5
FLASH MEMORY INTERFACE REGISTERS
There is a separate interface for the program flash and data flash memories. The same set of registers exist in both interfaces. In most cases they are independent of each other, but in some cases the program flash interface controls the interface for both memories, as indicated in the following sections. Table 18 lists the registers. Table 18 Flash Memory Interface Registers Program Memory FMIBAR FF F940h FMIBDR FF F942h FM0WER FF F944h FM1WER FF F946h FMCTRL FF F94Ch FMSTAT FF F94Eh FMPSR FF F950h FMSTART FF F952h FMTRAN FF F954h FMPROG FF F956h FMPERASE FF F958h FMMERASE0 FF F95Ah FMEND FF F95Eh FMMEND FF F960h Data Memory FSMIBAR FF F740h FSMIBDR FF F742h FSM0WER FF F744h N/A FSMCTRL FF F74Ch FSMSTAT FF F74Eh FSMPSR FF F750h FSMSTART FF F752h FSMTRAN FF F754h FSMPROG FF F756h FSMPERASE FF F758h FSMMERASE0 FF F75Ah FSMEND FF F75Eh FSMMEND FF F760h Description Flash Memory Information Block Address Register Flash Memory Information Block Address Register Flash Memory 0 Write Enable Register Flash Memory 1 Write Enable Register Flash Memory Control Register Flash Memory Status Register Flash Memory Prescaler Register Flash Memory Start Time Reload Register Flash Memory Transition Time Reload Register Flash Memory Programming Time Reload Register Flash Memory Page Erase Time Reload Register Flash Memory Module Erase Time Reload Register 0 Flash Memory End Time Reload Register Flash Memory Module Erase End Time Reload Register IBA
Flash Memory Information Block Address Register (FMIBAR/FSMIBAR)
The FMIBAR register specifies the 8-bit address for read or write access to an information block. Because only word access to the information blocks is supported, the least significant bit (LSB) of the FMIBAR must be 0 (word-aligned). The hardware automatically clears the LSB, without regard to the value written to the bit. The FMIBAR register is cleared after device reset. The CPU bus master has read/write access to this register. 15 Reserved 8 7 IBA 0
The Information Block Address field holds the word-aligned address of an information block location accessed during a read or write transaction. The LSB of the IBA field is always clear.
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8.5.2
Flash Memory Information Block Data Register (FMIBDR/FSMIBDR)
8.5.4
Flash Memory 1 Write Enable Register (FM1WER)
The FMIBDR register holds the 16-bit data for read or write access to an information block. The FMIBDR register is cleared after device reset. The CPU bus master has read/ write access to this register. 15 IBD 0
The FM1WER register controls write protection for the second half of the program flash memory. The data block is divided into 16 8K-byte sections. Each bit in the FM1WER register controls write protection for one of these sections. The FM1WER register is cleared after device reset, so the flash memory is write protected after reset. The CPU bus master has read/write access to this registers. 15 0 FM1WE
IBD
The Information Block Data field holds the data word for access to an information block. For write operations the IBD field holds the data word to be programmed into the informa- FM1WEn tion block location specified by the IBA address. During a read operation from an information block, the IBD field receives the data word read from the location specified by the IBA address. Flash Memory 0 Write Enable Register (FM0WER/FSM0WER)
The Flash Memory 1 Write Enable n bits control write protection for a section of a flash memory data block. The address mapping of the register bits is shown below. Bit 0 1-14 15 Logical Address Range 02 0000h-02 1FFFh ... 03 E000h-03 FFFFh
8.5.3
The FM0WER register controls section-level write protection for the first half of the flash program memory. The FMS0WER registers controls section-level write protection for the flash data memory. Each data block is divided into 16 8K-byte sections. Each bit in the FM0WER and FSM0WER registers controls write protection for one of these sections. The FM0WER and FSM0WER registers are cleared after device reset, so the flash memory is write protected after reset. The CPU bus master has read/write access to this registers. 15 FM0WE 0
8.5.5
Flash Data Memory 0 Write Enable Register (FSM0WER)
The FSM0WER register controls write protection for the flash data memory. The data block is divided into 16 512byte sections. Each bit in the FSM0WER register controls write protection for one of these sections. The FSM0WER register is cleared after device reset, so the flash memory is write protected after reset. The CPU bus master has read/ write access to this registers. 15 0 FSM0WE
FM0WEn
The Flash Memory 0 Write Enable n bits control write protection for a section of a flash memory data block. The address mapping of FSM0WEn the register bits is shown below. Bit 0 1-14 15 Logical Address Range 00 0000h-00 1FFFh ... 01 E000h-01 FFFFh
The Flash Data Memory 0 Write Enable n bits control write protection for a section of a flash memory data block. The address mapping of the register bits is shown below. Bit 0 1-14 15 Logical Address Range 0E 0000h-0E 01FFh ... 0E 1E00h-0E 1FFFh
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8.5.6
Flash Memory Control Register (FMCTRL/ FSMCTRL)
This register controls the basic functions of the Flash program memory. The register is clear after device reset. The CPU bus master has read/write access to this register. 7 6 5 4 3 2 1 0
MER PER PE IENPROG DISVRF Res. CWD LOWPRW
LOWPRW
CWD
DISVRF
IENPROG
PE
PER
The Low Power Mode controls whether flash program memory is operated in low-power mode, which draws less current when data is read. This is accomplished be only accessing the flash program memory during the first half of the clock period. The low-power mode must not be used at System Clock frequencies above 25 MHz, otherwise a read access may return undefined data. This bit must not be changed while the flash program memory is busy being programmed or erased. 0 - Normal mode. 1 - Low-power mode. The CPU Write Disable bit controls whether the CPU has write access to flash memory. This bit must not be changed while FMBUSY is set. 0 - The CPU has write access to the flash memory 1 - An external debugging tool is the current "owner" of the flash memory interface, so write accesses by the CPU are inhibited. The Disable Verify bit controls the automatic verification feature. This bit must not be changed while the flash program memory is busy being programmed or erased. 0 - New flash program memory contents are automatically verified after programming. 1 - Automatic verification is disabled. The Interrupt Enable for Program bit is clear after reset. The flash program and data memories share a single interrupt channel but have independent interrupt enable control bits. 0 - No interrupt request is asserted to the ICU when the FMFULL bit is cleared. 1 - An interrupt request is made when the FMFULL bit is cleared and new data can be written into the write buffer. The Program Enable bit controls write access of the CPU to the flash program memory. This bit must not be altered while the flash program memory is busy being programmed or erased. The PER and MER bits must be clear when this bit is set. 0 - Programming the flash program memory by the CPU is disabled. 1 - Programming the flash program memory is enabled. The Page Erase Enable bit controls whether a a valid write operation triggers an erase operation on a 1024-byte page of flash memory. 36
MER
Page erase operations are only supported for the main blocks, not the information blocks. A page erase operation on an information block is ignored and does not alter the information block. When the PER bit is set, the PE and MER bits must be clear. This bit must not be changed while the flash program memory is busy being programmed or erased. 0 - Page erase mode disabled. Write operations are performed normally. 1 - A valid write operation to a word location in program memory erases the page that contains the word. The Module Erase Enable bit controls whether a valid write operation triggers an erase operation on an entire block of flash memory. If an information block is written in this mode, both the information block and its corresponding main block are erased. When the MER bit is set, the PE and PER bits must be clear. This bit must not be changed while the flash program memory is busy being programmed or erased. 0 - Module erase mode disabled. Write operations are performed normally. 1 - A valid write operation to a word location in a main block erases the block that contains the word. A valid write operation to a word location in an information block erases the block that contains the word and its associated main block. Flash Memory Status Register (FMSTAT/ FSMSTAT)
8.5.7
This register reports the currents status of the on-chip Flash memory. The FLSR register is clear after device reset. The CPU bus master has read/write access to this register. 7 5 4 3 2 1 0
Reserved
DERR FMFULL FMBUSY PERR EERR
EERR
PERR
The Erase Error bit indicates whether an error has occurred during a page erase or module (block) erase. After an erase error occurs, software can clear the EERR bit by writing a 1 to it. Writing a 0 to the EERR bit has no effect. Software must not change this bit while the flash program memory is busy being programmed or erased. 0 - The erase operation was successful. 1 - An erase error occurred. The Program Error bit indicates whether an error has occurred during programming. After a programming error occurs, software can clear the PERR bit by writing a 1 to it. Writing a 0 to the PERR bit has no effect. Software must not change this bit while the flash program memory is busy being programmed or erased.
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FMBUSY
FMFULL
0 - The programming operation was successful. 1 - A programming error occurred. The Flash Memory Busy bit indicates whether the flash memory (either main block or information block) is busy being programmed or erased. During that time, software must not request any further flash memory operations. If such an attempt is made, the CPU is stopped as long as the FMBUSY bit is active. The CPU must not attempt to read from program memory (including instruction fetches) while it is busy. 0 - Flash memory is ready to receive a new erase or programming request. 1 - Flash memory busy with previous erase or programming operation. The Flash Memory Buffer Full bit indicates whether the write buffer for programming is full or not. When the buffer is full, new erase and write requests may not be made. The IENPROG bit can be enabled to trigger an interrupt when the buffer is ready to receive a new request. 0 - Buffer is ready to receive new erase or write requests. 1 - Buffer is full. No new erase or write requests can be accepted.
DERR
The Data Loss Error bit indicates that a buffer overrun has occurred during a programming sequence. After a data loss error occurs, software can clear the DERR bit by writing a 1 to it. Writing a 0 to the DERR bit has no effect. Software must not change this bit while the flash program memory is busy being programmed or erased. 0 - No data loss error occurred. 1 - Data loss error occurred. Flash Memory Prescaler Register (FMPSR/ FSMPSR)
8.5.8
The FMPSR register is a byte-wide read/write register that selects the prescaler divider ratio. The CPU must not modify this register while an erase or programming operation is in progress (FMBUSY is set). At reset, this register is initialized to 04h if the flash memory is idle. The CPU bus master has read/write access to this register. 7 Reserved 5 4 FTDIV 0
FTDIV 8.5.9
The prescaler divisor scales the frequency of the System Clock by a factor of (FTDIV + 1). Flash Memory Start Time Reload Register (FMSTART/FSMSTART)
The FMSTART/FSMSTART register is a byte-wide read/ write register that controls the program/erase start delay time. Software must not modify this register while a program/erase operation is in progress (FMBUSY set). At reset, this register is initialized to 18h if the flash memory is idle. The CPU bus master has read/write access to this register. 7 FTSTART 0
FTSTART
The Flash Timing Start Delay Count field generates a delay of (FTSTART + 1) prescaler output clocks.
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8.5.10
Flash Memory Transition Time Reload Register (FMTRAN/FSMTRAN)
8.5.13
Flash Memory Module Erase Time Reload Register 0 (FMMERASE0/FSMMERASE0)
The FMTRAN/FMSTRAN register is a byte-wide read/write register that controls some program/erase transition times. Software must not modify this register while program/erase operation is in progress (FMBUSY set). At reset, this register is initialized to 30h if the flash memory is idle. The CPU bus master has read/write access to this register. 7 FTTRAN 0
The FMMERASE0/FSMMERASE0 register is a byte-wide read/write register that controls the module erase pulse width. Software must not modify this register while a program/erase operation is in progress (FMBUSY set). At reset, this register is initialized to EAh if the flash memory is idle. The CPU bus master has read/write access to this register. 7 FTMER 0
FTTRAN
The Flash TIming Transition Count field specifies a delay of (FTTRAN + 1) prescaler output clocks. Flash Memory Programming Time Reload Register (FMPROG/FSMPROG)
FTMER
8.5.11
The Flash Timing Module Erase Pulse Width field specifies a module erase pulse width of 4096 x (FTMER + 1) prescaler output clocks. Flash Memory End Time Reload Register (FMEND/FSMEND)
8.5.14
The FMPROG/FSMPROG register is a byte-wide read/write register that controls the programming pulse width. Software must not modify this register while a program/erase operation is in progress (FMBUSY set). At reset, this register is initialized to 16h if the flash memory is idle. The CPU bus master has read/write access to this register. 7 FTPROG 0
The FMEND/FSMEND register is a byte-wide read/write register that controls the delay time after a program/erase operation. Software must not modify this register while a program/erase operation is in progress (FMBUSY set). At reset, this register is initialized to 18h when the flash memory on the chip is idle. The CPU bus master has read/write access to this register. 7 FTEND 0
FTPROG
The Flash Timing Programming Pulse Width field specifies a programming pulse width of 8 x (FTPROG + 1) prescaler output clocks.
FTEND
8.5.12
Flash Memory Page Erase Time Reload Register (FMPERASE/FSMPERASE) 8.5.15
The Flash Timing End Delay Count field specifies a delay of (FTEND + 1) prescaler output clocks. Flash Memory Module Erase End Time Reload Register (FMMEND/FSMMEND)
The FMPERASE/FSMPERASE register is a byte-wide read/write register that controls the page erase pulse width. Software must not modify this register while a program/ erase operation is in progress (FMBUSY set). At reset, this register is initialized to 04h if the flash memory is idle. The CPU bus master has read/write access to this register. 7 FTPER 0
The FMMEND/FSMMEND register is a byte-wide read/write register that controls the delay time after a module erase operation. Software must not modify this register while a program/erase operation is in progress (FMBUSY set). At reset, this register is initialized to 3Ch if the flash memory is idle. The CPU bus master has read/write access to this register. 7 0 FTMEND
FTPER
The Flash Timing Page Erase Pulse Width field specifies a page erase pulse width of 4096 x (FTPER + 1) prescaler output clocks. FTMEND
The Flash Timing Module Erase End Delay Count field specifies a delay of 8 x (FTMEND + 1) prescaler output clocks.
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8.5.16
Flash Memory Recovery Time Reload Register (FMRCV/FSMRCV)
8.5.18
Flash Memory Auto-Read Register 1 (FMAR1/ FSMAR1)
The FMRCV/FSMRCV register is a byte-wide read/write register that controls the recovery delay time between two flash memory accesses. Software must not modify this register while a program/erase operation is in progress (FMBUSY set). At reset, this register is initialized to 04h if the flash memory is idle. The CPU bus master has read/write access to this register. 7 FTRCV 0
The FMAR1 register contains a copy of the Protection Word from Information Block 1. The Protection Word is sampled at reset. The contents of the FMAR1 register define the current Flash memory protection settings. The CPU bus master has read-only access to this register. The FSMAR1 register has the same value as the FMAR1 register. The format is the same as the format of the Protection Word (see Section 8.4.2). 15 13 12 10 9 7 6 4 3 1 0
WRPROT RDPROT ISPE EMPTY BOOTAREA 1 FTRCV The Flash Timing Recovery Delay Count field specifies a delay of (FTRCV + 1) prescaler output clocks. Flash Memory Auto-Read Register 0 (FMAR0/ FSMAR0)
8.5.19
Flash Memory Auto-Read Register 2 (FMAR2/ FSMAR2)
8.5.17
The FMAR0/FSMAR0 register contains a copy of the Function Word from Information Block 0. The Function Word is sampled at reset. The contents of the FMAR0 register are used to enable or disable special device functions. The CPU The FSMAR2 register has the same value as the FMAR2 bus master has read-only access to this register. The register. FSMAR0 register has the same value as the FMAR0 register 7 0 CADR7:0 15 Reserved 1 0 USB_ENABLE 15 USB_ENABLE The USB_ENABLE bit can be used to force an external USB transceiver into its low-power mode. The USB power mode is dependent on CADR8:0 the USB controller status, the USB_ENABLE bit in the MCFG register (see Section 7.1), and the USB_ENABLE bit in the Function Word. CADR12:9 0 - External USB transceiver forced into lowpower mode. 1 - Transceiver power mode dependent on CADR15:13 USB controller status and programming of the Function Word. CADR15:13 13 12 CADR12:8 9 8 CADR8
The FMAR2 register is a word-wide read-only register, which is loaded during reset. It is used to build the Code Area start address. At reset, the CPU executes a branch, using the contents of the FMAR2 register as displacement. The CPU bus master has read-only access to this register.
The Code Area Start Address (bits 8:0) contains the lower 9 bits of the Code Area start address. The CADR8:0 field has a fixed value of 0. The Code Area Start Address (bits 12:9) are loaded during reset with the inverted value of BOOTAREA3:0. The Code Area Start Address (bits 15:13) contains the upper 3 bits of the Code Area start address. The CADR15:13 field has a fixed value of 0.
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9.0
DMA Controller
Table 19 DMA Channel Assignment Channel 0 (Primary) 0 (Secondary) 1 (Primary) 1 (Secondary) 2 (Primary) 2 (Secondary) 3 (Primary) 3 (Secondary) Peripheral USB UART UART unused Audio Interface CVSD/PCM Transcoder Audio Interface CVSD/PCM Transcoder Transaction R/W R W N/A R R W W Register RX/TX FIFO RXBUF TXBUF N/A ARDR0 PCMOUT ATDR0 PCMIN
The DMA Controller (DMAC) has a register-based programming interface, as opposed to an interface based on I/O control blocks. After loading the registers with source and destination addresses, as well as block size and type of operation, a DMAC channel is ready to respond to DMA transfer requests. A request can only come from on-chip peripherals or software, not external peripherals. On receiving a DMA transfer request, if the channel is enabled, the DMAC performs the following operations: 1. Arbitrates to become master of the CPU bus. 2. Determines priority among the DMAC channels, one clock cycle before T1 of the DMAC transfer cycle. (T1 is the first clock cycle of the bus cycle.) Priority among the DMAC channels is fixed in descending order, with Channel 0 having the highest priority. 3. Executes data transfer bus cycle(s) selected by the values held in the control registers of the channel being serviced, and according to the accessed memory address. The DMAC acknowledges the request during the bus cycle that accesses the requesting device. 4. If the transfer of a block is terminated, the DMAC does the following: Updates the termination bits. Generates an interrupt (if enabled). Goes to step 6. 5. If DMRQn is still active, and the Bus Policy is "continuous", returns to step 3. 6. Returns mastership of the CPU bus to the CPU.
9.2
TRANSFER TYPES
The DMAC uses two data transfer modes, Direct (Flyby) and Indirect (Memory-to-Memory). The choice of mode depends on the required bus performance and whether direct mode is available for the transfer. Indirect mode must be used when the source and desitnation have differing bus Each DMAC channel can be programmed for direct (flyby) widths, when both the source and destination are in memoor indirect (memory-to-memory) data transfers. Once a ry, and when the destination does not support direct mode. DMAC transfer cycle is in progress, the next transfer request Direct (Flyby) Transfers is sampled when the DMAC acknowledge is de-asserted, 9.2.1 then on the rising edge of every clock cycle. In direct mode each data item is transferred using a single The configuration of either address freeze or address update (increment or decrement) is independent of the number of transferred bytes, transfer direction, or number of bytes in each DMAC transfer cycle. All these can be configured for each channel by programming the appropriate control registers. Each DMAC channel has eight control registers. DMAC channels are described hereafter with the suffix n, where n = 0 to 3, representing the channel number in the registernames. bus cycle, without reading the data into the DMAC. It provides the fastest transfer rate, but it requires identical source and destination bus widths. The DMAC cannot use Direct cycles between two memory devices. One of the devices must be an I/O device that supports the Direct (Flyby) mechanism, as shown in Figure 2.
Bus State T1 CLK T2 Tidle T1
9.1
CHANNEL ASSIGNMENT
DMRQ[3:0]
Table 19 shows the assignment of the DMA channels to different tasks. Four channels can be shared by a primary and an secondary function. However, only one source at a time can be enabled. If a channel is used for memory block transfers, other resources must be disabled.
ADDR
ADCA
DMACK[3:0]
DS005
Figure 2. Direct DMA Cycle Followed by a CPU Cycle Direct mode supports two bus policies: intermittent and continuous. In intermittent mode, the DMAC gives bus mastership back to the CPU after every cycle. In continuous mode, the DMAC remains bus master until the transfer is completwww.national.com 40
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ed. The maximum bus throughput in intermittent mode is 9.3 OPERATION MODES one transfer for every three System Clock cycles. The maxThe DMAC operates in three different block transfer modes: imum bus throughput in continuous mode is one transfer for single transfer, double buffer, and auto-initialize. every clock cycle. Single Transfer Operation The I/O device which made the DMA request is called the 9.3.1 implied I/O device. The other device can be either memory or another I/O device, and is called the addressed device. Because only one address is required in direct mode, this address is taken from the corresponding ADCAn counter. The DMAC channel generates either a read or a write bus cycle, as controlled by the DMACNTLn.DIR bit. When the DMACNTLn.DIR bit is clear, a read bus cycle from the addressed device is performed, and the data is written to the implied I/O device. When the DMACNTLn.DIR bit is set, a write bus cycle to the addressed device is performed, and the data is read from the implied I/O device. The configuration of either address freeze or address update (increment or decrement) is independent of the number of transferred bytes, transfer direction, or number of bytes in each DMAC transfer cycle. All these can be configured for each channel by programming the appropriate control register. Whether 8 or 16 bits are transferred in each cycle is selected by the DMACNTLn.TCS register bit. After the data item has been transferred, the BLTCn counter is decremented by one. The ADCAn counter is updated according to the INCA and ADA fields in the DMACNTLn register. 9.2.2 Indirect (Memory-To-Memory) Transfers This mode provides the simplest way to accomplish a single block data transfer. Initialization 1. Write the block transfer addresses and byte count into the corresponding ADCAn, ADCBn, and BLTCn counters. 2. Clear the DMACNTLn.OT bit to select non-auto-initialize mode. Clear the DMASTAT.VLD bit by writing a 1 to it. 3. Set the DMACNTLn.CHEN bit to activate the channel and enable it to respond to DMA transfer requests. Termination When the BLTCn counter reaches 0: 1. The transfer operation terminates. 2. The DMASTAT.TC and DMASTAT.OVR bits are set, and the DMASTAT.CHAC bit is cleared. 3. An interrupt is generated if enabled by the DMACNTLn.ETC or DMACNTLn.EOVR bits. The DMACNTLn.CHEN bit must be cleared before loading the DMACNTLn register to avoid prematurely starting a new DMA transfer. 9.3.2 Double Buffer Operation
In indirect (memory-to-memory) mode, data transfers use This mode allows software to set up the next block transfer two consecutive bus cycles. The data is first read into a tem- while the current block transfer proceeds. porary register, and then written to the destination in the fol- Initialization lowing cycle. This mode is slower than the direct (flyby) 1. Write the block transfer addresses and byte count into mode, but it provides support for different source and destithe ADCAn, ADCBn, and BLTCn counters. nation bus widths. Indirect mode must be used for transfers 2. Clear the DMACNTLn.OT bit to select non-auto-initialbetween memory devices. ize mode. Clear the DMASTAT.VLD bit by writing a 1 to it. If an intermittent bus policy is used, the maximum throughput is one transfer for every five clock cycles. If a continuous 3. Set the DMACNTLn.CHEN bit. This activates the channel and enables it to respond to DMA transfer requests. bus policy is used, maximum throughput is one transfer for 4. While the current block transfer proceeds, write the adevery two clock cycles. dresses and byte count for the next block into the When the DMACNTLn.DIR bit is 0, the first bus cycle reads ADRAn, ADRBn, and BLTRn registers. The BLTRn regdata from the source using the ADCAn counter, while the ister must be written last, because it sets the DMASsecond bus cycle writes the data into the destination using TAT.VLD bit which indicates that all the parameters for the ADCBn counter. When the DMACNTLn.DIR bit is set, the next transfer have been updated. the first bus cycle reads data from the source using the ADCBn counter, while the second bus cycle writes the data into Continuation/Termination the destination addressed by the ADCAn counter. When the BLTCn counter reaches 0: The number of bytes transferred in each cycle is taken from 1. The DMASTAT.TC bit is set. the DMACNTLn.TCS register bit. After the data item has 2. An interrupt is generated if enabled by the been transferred, the BLTCn counter is decremented by DMACNTLn.ETC bit. one. The ADCAn and ADCBn counters are updated accord3. The DMAC channel checks the value of the VLD bit. ing to the INCA, INCB, ADA, and ADB fields in the If the DMASTAT.VLD bit is set: DMACNTLn register. 1. The channel copies the ADRAn, ADRBn, and BLTRn values into the ADCAn, ADCBn, and BLTCn registers. 2. The DMASTAT.VLD bit is cleared. 3. The next block transfer is started.
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If the DMASTAT.VLD bit is clear: 1. 2. 3. 4. The transfer operation terminates. The channel sets the DMASTAT.OVR bit. The DMASTAT.CHAC bit is cleared. An interrupt is generated if enabled DMACNTLn.EOVR bit.
by
the
The DMACNTLn.CHEN bit must be cleared before loading the DMACNTLn register to avoid prematurely starting a new DMA transfer.
Note: The ADCBn and ADRBn registers are used only in indirect (memory-to-memory) transfer. In direct (flyby) 9.5 DEBUG MODE mode, the DMAC does not use them and therefore does not When the FREEZE signal is active, all DMA operations are copy ADRBn into ADCBn. stopped. They will start again when the FREEZE signal 9.3.3 Auto-Initialize Operation goes inactive. This allows breakpoints to be used in debug This mode allows the DMAC to continuously fill the same systems. memory area without software intervention.
For each channel, use the software DMA transfer request only when the corresponding hardware DMA request is inactive and no terminal count interrupt is pending . Software can poll the DMASTAT.CHAC bit to determine whether the DMA channel is already active. After verifying the DMASTATn.CHAC bit is clear (channel inactive), check the DMASTATn.TC (terminal count) bit. If the TC bit is clear, then no terminal count condition exists and therefore no terminal count interrupt is pending. If the channel is not active and no terminal count interrupt is pending, software may request a DMA transfer.
9.6
DMA CONTROLLER REGISTER SET
Initialization There are four identical sets of DMA controller registers, as 1. Write the block addresses and byte count into the ADlisted in Table 20. CAn, ADCBn, and BLTCn counters, as well as the Table 20 DMA Controller Registers ADRAn, ADRBn, and BLTRn registers. 2. Set the DMACNTLn.OT bit to select auto-initialize Name Address Description mode. 3. Set the DMACNTLn.CHEN bit to activate the channel Device A Address and enable it to respond to DMA transfer requests. ADCA0 FF F800h Counter Register Continuation Device A Address ADRA0 FF F804h When the BLTCn counter reaches 0: Register 1. The contents of the ADRAn, ADRBn, and BLTRn regisDevice B Address ters are copied to the ADCAn, ADCBn, and BLTCn ADCB0 FF F808h Counter Register counters. 2. The DMAC channel checks the value of the DMASDevice B Address ADRB0 FF F80Ch TAT.TC bit. Register If the DMASTAT.TC bit is set: Block Length BLTC0 FF F810h 1. The DMASTAT.OVR bit is set. Counter Register 2. A level interrupt is generated if enabled by the BLTR0 FF F814h Block Length Register DMACNTLn.EOVR bit. 3. The operation is repeated. DMACNTL0 FF F81Ch DMA Control Register If the DMASTAT.TC bit is clear: DMASTAT0 FF F81Eh DMA Status Register 1. The DMASTAT.TC bit is set. 2. A level interrupt is generated if enabled by the Device A Address ADCA1 FF F820h DMACNTLn.ETC bit. Counter Register 3. The DMAC operation is repeated. Device A Address ADRA1 FF F824h Termination Register The DMA transfer is terminated when the Device B Address ADCB1 FF F828h DMACNTLn.CHEN bit is cleared. Counter Register
9.4
SOFTWARE DMA REQUEST
ADRB1 BLTC1 BLTR1 DMACNTL1 DMASTAT1 FF F82Ch FF F830h FF F834h FF F83Ch FF F83Eh
In addition to the hardware requests from I/O devices, a DMA transfer request can also be initiated by software. A software DMA transfer request must be used for block copying between memory devices. When the DMACNTLn.SWRQ bit is set, the corresponding DMA channel receives a DMA transfer request. When the DMACNTLn.SWRQ bit is clear, the software DMA transfer request of the corresponding channel is inactive.
Device B Address Register Block Length Counter Register Block Length Register DMA Control Register DMA Status Register
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Table 20 DMA Controller Registers Name ADCA2 ADRA2 ADCB2 ADRB2 BLTC2 BLTR2 DMACNTL2 DMASTAT2 ADCA3 ADRA3 ADCB3 ADRB3 BLTC3 BLTR3 DMACNTL3 DMASTAT3 9.6.1 Address FF F840h FF F844h FF F848h FF F84Ch FF F850h FF F854h FF F85Ch FF F85Eh FF F860h FF F864h FF F868h FF F86Ch FF F870h FF F874h FF F87Ch FF F87Eh Description Device A Address Counter Register Device A Address Register Device B Address Counter Register Device B Address Register Block Length Counter Register Block Length Register DMA Control Register DMA Status Register Device A Address Counter Register Device A Address Register Device B Address Counter Register Device B Address Register Block Length Counter Register Block Length Register DMA Control Register DMA Status Register
9.6.2
Device A Address Register (ADRAn)
The Device A Address register is a 32-bit, read/write register. It holds the 24-bit starting address of either the next source data block, or the next destination data area, according to the DIR bit in the DMACNTLn register. The upper 8 bits of the ADRAn register are reserved and always clear. 31 24 23 Device A Address 0
Reserved
9.6.3
Device B Address Counter Register (ADCBn)
The Device B Address Counter register is a 32-bit, read/ write register. It holds the current 24-bit address of either the source data item, or the destination location, according to the DIR bit in the CNTLn register. The ADCBn register is updated after each transfer cycle by INCB field of the DMACNTLn register according to ADB bit of the DMACNTLn register. In direct (flyby) mode, this register is not used. The upper 8 bits of the ADCBn register are reserved and always clear. 31 24 23 Device B Address Counter 0
Reserved
9.6.4
Device B Address Register (ADRBn)
The Device B Address register is a 32-bit, read/write register. It holds the 24-bit starting address of either the next source data block or the next destination data area, according to the DIR bit in the CNTLn register. In direct (flyby) mode, this register is not used. The upper 8 bits of the ADCRBn register are reserved and always clear. 31 24 23 Device B Address 0
Reserved
Device A Address Counter Register (ADCAn) 9.6.5 Block Length Counter Register (BLTCn) The Block Length Counter register is a 16-bit, read/write register. It holds the current number of DMA transfers to be executed in the current block. BLTCn is decremented by one after each transfer cycle. A DMA transfer may consist of 1 or 2 bytes, as selected by the DMACNTLn.TCS bit. 15 Block Length Counter Note: 0000h is interpreted as 216-1 transfer cycles. 0
The Device A Address Counter register is a 32-bit, read/ write register. It holds the current 24-bit address of either the source data item or the destination location, depending on the state of the DIR bit in the CNTLn register. The ADA bit of DMACNTLn register controls whether to adjust the pointer in the ADCAn register by the step size specified in the INCA field of DMACNTLn register. The upper 8 bits of the ADCAn register are reserved and always clear. 31 24 23 Device A Address Counter 0
Reserved
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9.6.6
Block Length Register (BLTRn)
DIR
The Block Length register is a 16-bit, read/write register. It holds the number of DMA transfers to be performed for the next block. Writing this register automatically sets the DMASTAT.VLD bit. 15 Block Length Note: 0000h is interpreted as 216-1 transfer cycles. 9.6.7 DMA Control Register (DMACNTLn) BPC 0 OT
The DMA Control register n is a word-wide, read/write register that controls the operation of DMA channel n. This register is cleared at reset. Reserved bits must be written with 0. 7 BPC 6 OT 5 DIR 4 IND 3 2 1 0
TCS EOVR ETC CHEN
15 Res.
14
13
12 ADB
11
10
9
8 SWRQ
INCB
INCA
ADA SWRQ
CHEN
ETC
EOVR
TCS
IND
The Channel Enable bit must be set to enable any DMA operation on this channel. Writing a 1 to this bit starts a new DMA transfer even if it is currently a 1. If all DMACNTLn.CHEN bits are clear, the DMA clock is disabled to reduce power. 0 - Channel disabled. 1 - Channel enabled. If the Enable Interrupt on Terminal Count bit is set, it enables an interrupt when the DMASTAT.TC bit is set. 0 - Interrupt disabled. 1 - Interrupt enabled. If the Enable Interrupt on OVR bit is set, it enables an interrupt when the DMASTAT.OVR bit is set. 0 - Interrupt disabled. 1 - Interrupt enabled. The Transfer Cycle Size bit specifies the number of bytes transferred in each DMA transfer cycle. In direct (fly-by) mode, undefined results occur if the TCS bit is not equal to the addressed memory bus width. 0 - Byte transfers (8 bits per cycle). 1 - Word transfers (16 bits per cycle). The Direct/Indirect Transfer bit specifies the transfer type. 0 - Direct transfer (flyby). 1 - Indirect transfer (memory-to-memory).
ADA
INCA
ADB
INCB
The Transfer Direction bit specifies the direction of the transfer relative to Device A. 0 - Device A (pointed to by the ADCAn register) is the source. In Fly-By mode a read transaction is initialized. 1 - Device A (pointed to by the ADCAn register) is the destination. In Fly-By mode a write transaction is initialized. The Operation Type bit specifies the operation mode of the DMA controller. 0 - Single-buffer mode or double-buffer mode enabled. 1 - Auto-Initialize mode enabled. The Bus Policy Control bit specifies the bus policy applied by the DMA controller. The operation mode can be either intermittent (cycle stealing) or continuous (burst). 0 - Intermittent operation. The DMAC channel relinquishes the bus after each transaction, even if the request is still asserted. 1 - Continuous operation. The DMAC channel n uses the bus continuously as long as the request is asserted. This mode can only be used for software DMA requests. For hardware DMA requests, the BPC bit must be clear. The Software DMA Request bit is written with a 1 to initiate a software DMA request. Writing a 0 to this bit deactivates the software DMA request. The SWRQ bit must only be written when the DMRQ signal for this channel is inactive (DMASTAT.CHAC = 0). 0 - Software DMA request is inactive. 1 - Software DMA request is active. If the Device A Address Control bit is set, it enables updating the Device A address. 0 - ADCAn address unchanged. 1 - ADCAn address incremented or decremented, according to INCA field of DMACNTLn register. The Increment/Decrement ADCAn field specifies the step size for the Device A address increment/decrement. 00 - Increment ADCAn register by 1. 01 - Increment ADCAn register by 2. 10 - Decrement ADCAn register by 1. 11 - Decrement ADCAn register by 2. If the Device B Address Control bit is set, it enables updating the Device B Address. 0 - ADCBn address unchanged. 1 - ADCBn address incremented or decremented, according to INCB field of DMACNTLn register. The Increment/Decrement ADCBn field specifies the step size for the Device B address increment/decrement. 00 - Increment ADCBn register by 1. 01 - Increment ADCBn register by 2. 10 - Decrement ADCBn register by 1. 11 - Decrement ADCBn register by 2.
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9.6.8
DMA Status Register (DMASTAT)
The DMA status register is a byte-wide, read register that holds the status information for the DMA channel n. This register is cleared at reset. The reserved bits always return zero when read. The VLD, OVR and TC bits are sticky (once set by the occurrence of the specific condition, they remain set until explicitly cleared by software). These bits can be individually cleared by writing 1 to the bit positions in the DMASTAT register to be cleared. Writing 0 to these bits has no effect 7 Reserved 4 3 2 1 0 TC
VLD CHAC OVR
TC
OVR
CHAC
VLD
The Terminal Count bit indicates whether the transfer was completed by a terminal count condition (BLTCn Register reached 0). 0 - Terminal count condition did not occur. 1 - Terminal count condition occurred. The behavior of the Channel Overrun bit depends on the operation mode (single buffer, double buffer, or auto-initialize) of the DMA channel. In double-buffered mode (DMACNTLn.OT = 0): The OVR bit is set when the present transfer is completed (BLTCn = 0), but the parameters for the next transfer (address and block length) are not valid (DMASTAT.VLD = 0). In auto-initialize mode (DMACNTLn.OT = 1): The OVR bit is set when the present transfer is completed (BLTCn = 0), and the DMASTAT.TC bit is still set. In single-buffer mode: Operates in the same way as double-buffer mode. In single-buffered mode, the DMASTAT.VLD bit should always be clear, so it will also be set when the DMASTAT.TC bit is set. Therefore, the OVR bit can be ignored in this mode. The Channel Active bit continuously indicates the active or inactive status of the channel, and therefore, it is read only. Data written to the CHAC bit is ignored. 0 - Channel inactive. 1 - Indicates that the channel is active (CHEN bit in the CNTLn register is 1 and BLTCn > 0) The Transfer Parameters Valid bit specifies whether the transfer parameters for the next block to be transferred are valid. Writing the BLTRn register automatically sets this bit. The bit is cleared in the following cases: * The present transfer is completed and the ADRAn, ADRBn (indirect mode only), and BLTR registers are copied to the ADCAn, ADCBn (indirect mode only), and BLTCn registers. * Writing 1 to the VLD bit.
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10.0 Interrupts
The Interrupt Control Unit (ICU) receives interrupt requests from internal and external sources and generates interrupts to the CPU. Interrupts from the timers, UARTs, Microwire/ SPI interface, and Multi-Input Wake-Up are all maskable interrupts. The highest-priority interrupt is the Non-Maskable Interrupt (NMI), which is triggered by a falling edge received on the NMI input pin. The priorities of the maskable interrupts are hardwired and therefore fixed. The interrupts are named IRQ0 through IRQ31, in which IRQ0 has the lowest priority and IRQ31 has the highest priority. knowledge bus cycle on receiving a maskable interrupt request from the ICU. During the interrupt acknowledge cycle, a byte is read from address FF FE00h (IVCT register). The byte is used as an index into the Dispatch Table to determine the address of the interrupt handler. Because IRQ0 is not connected to any interrupt source, it would seem that the interrupt vector would never return the value 10h. If it does return a value of 10h, the entry in the dispatch table should point to a default interrupt handler that handles this error condition. One possible condition for this to occur is deassertion of the interrupt before the interrupt acknowledge cycle.
10.1
NON-MASKABLE INTERRUPTS
The Interrupt Control Unit (ICU) receives the external NMI input and generates the NMI signal driven to the CPU. The NMI input is an asynchronous input with Schmitt trigger characteristics and an internal synchronization circuit, therefore no external synchronizing circuit is needed. The NMI pin triggers an exception on its falling edge. 10.1.1 Non-Maskable Interrupt Processing
10.3
INTERRUPT CONTROLLER REGISTERS
Table 21 Interrupt Controller Registers Name Address FF FE02h Description Non-Maskable Interrupt Status Register External NMI Trap Control and Status Register Interrupt Vector Register Interrupt Enable and Mask Register 0 Interrupt Enable and Mask Register 1 Interrupt Status Register 0 Interrupt Status Register 1
Table 21 lists the ICU registers.
NMISTAT
The CPU performs an interrupt acknowledge bus cycle when beginning to process a non-maskable interrupt. The address associated with this core bus cycle is within the internal core address space and may be monitored as a Core Bus Monitoring (CBM) clock cycle. At reset, NMI interrupts are disabled and must remain disabled until software initializes the interrupt table, interrupt base register (INTBASE), and the interrupt mode. The external NMI interrupt is enabled by setting the EXNMI.ENLCK bit and will remain enabled until a reset occurs. Alternatively, the external NMI interrupt can be enabled by setting the EXNMI.EN bit and will remain enabled until an interrupt event or a reset occurs.
EXNMI
FF FE04h
IVCT IENAM0 IENAM1 ISTAT0 ISTAT1 10.3.1
FF FE00h FF FE0Eh FF FE10h FF FE0Ah FF FE0Ch
10.2
MASKABLE INTERRUPTS
The ICU receives level-triggered interrupt request signals from 31 internal sources and generates a vectored interrupt to the CPU when required. Priority among the interrupt sources (named IRQ1 through IRQ31) is fixed. The maskable interrupts are globally enabled and disabled by the E bit in the PSR register. The EI and DI instructions are used to set (enable) and clear (disable) this bit. The global maskable interrupt enable bit (I bit in the PSR) must also be set before any maskable interrupts are taken. Each interrupt source can be individually enabled or disabled under software control through the ICU interrupt enable registers and also through interrupt enable bits in the peripherals that request the interrupts. The CR16C core supports IRQ0, but in the CP3UB17 it is not connected to any interrupt source. 10.2.1
Non-Maskable Interrupt Status Register (NMISTAT)
The NMISTAT register is a byte-wide read-only register. It holds the status of the current pending Non-Maskable Interrupt (NMI) requests. On the CP3UB17, the external NMI input is the only source of NMI interrupts. The NMISTAT register is cleared on reset and each time its contents are read. 7 Reserved 1 0 EXT
Maskable Interrupt Processing Interrupt vector numbers are always positive, in the range EXT 10h to 2Fh. The IVCT register contains the interrupt vector of the enabled and pending interrupt with the highest priority. The interrupt vector 10h corresponds to IRQ0 and the lowest priority, while the vector 2Fh corresponds to IRQ31 and the highest priority. The CPU performs an interrupt acwww.national.com 46
The External NMI request bit indicates whether an external non-maskable interrupt request has occurred. Refer to the description of the EXNMI register below for additional details. 0 - No external NMI request. 1 - External NMI request has occurred.
CP3UB17
10.3.2
External NMI Trap Control and Status Register (EXNMI)
10.3.3
Interrupt Vector Register (IVCT)
The EXNMI register is a byte-wide read/write register. It indicates the current value of the NMI pin and controls the NMI interrupt trap generation based on a falling edge of the NMI pin. TST, EN and ENLCK are cleared on reset. When writing to this register, all reserved bits must be written with 0 for the device to function properly 7 Reserved 3 2 ENLCK 1 PIN 0 EN
The IVCT register is a byte-wide read-only register which reports the encoded value of the highest priority maskable interrupt that is both asserted and enabled. The valid range is from 10h to 2Fh. The register is read by the CPU during an interrupt acknowledge bus cycle, and INTVECT is valid during that time. It may contain invalid data while INTVECT is updated. 7 0 6 0 5 INTVECT 0
EN
PIN
ENLCK
The EXNMI trap enable bit is one of two bits that can be used to enable NMI interrupts. The bit is cleared by hardware at reset and whenever the NMI interrupt occurs (EXNMI.EXT set). It is intended for applications where the NMI input toggles frequently but nested NMI traps are not desired. For these applications, the EN bit needs to be re-enabled before exiting the trap handler. When used this way, the ENLCK bit should never be set. The EN bit can be set and cleared by software (software can set this bit only if EXNMI.EXT is cleared), and should only be set after the interrupt base register and the interrupt stack pointer have been set up. 0 - NMI interrupts not enabled by this bit (but may be enabled by the ENLCK bit). 1 - NMI interrupts enabled. The PIN bit indicates the state (non-inverted) on the NMI input pin. This bit is read-only, data written into it is ignored. 0 - NMI pin not asserted. 1 - NMI pin asserted. The EXNMI trap enable lock bit is used to permanently enable NMI interrupts. Only a device reset can clear the ENLCK bit. This allows the external NMI feature to be enabled after the interrupt base register and the interrupt stack pointer have been set up. When the ENLCK bit is set, the EN bit is ignored. 0 - NMI interrupts not enabled by this bit (but may be enabled by the EN bit). 1 - NMI interrupts enabled.
INTVECT
The Interrupt Vector field indicates the highest priority interrupt which is both asserted and enabled.
10.3.4
Interrupt Enable and Mask Register 0 (IENAM0)
The IENAM0 register is a word-wide read/write register which holds bits that individually enable and disable the maskable interrupt sources IRQ1 through IRQ15. The register is initialized to FFFFh upon reset. 15 IENA 1 0 Res.
IENA
Each Interrupt Enable bit enables or disables the corresponding interrupt request IRQ1 through IRQ15, for example IENA15 controls IRQ15. Because IRQ0 is not used, IENA0 is ignored. 0 - Interrupt is disabled. 1 - Interrupt is enabled. Interrupt Enable and Mask Register 1 (IENAM1)
10.3.5
The IENAM1 register is a word-wide read/write register which holds bits that individually enable and disable the maskable interrupt sources IRQ16 through IRQ31. The register is initialized to FFFFh at reset. 15 IENA 0
IENA
Each Interrupt Enable bit enables or disables the corresponding interrupt request IRQ16 through IRQ31, for example IENA15 controls IRQ31. 0 - Interrupt is disabled. 1 - Interrupt is enabled.
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10.3.6
Interrupt Status Register 0 (ISTAT0)
10.4
MASKABLE INTERRUPT SOURCES
The ISTAT0 register is a word-wide read-only register. It in- Table 22 shows the interrupts assigned to various on-chip dicates which maskable interrupt inputs to the ICU are ac- maskable interrupts. The priority of simultaneous maskable tive. These bits are not affected by the state of the interrupts is linear, with IRQ31 having the highest priority. corresponding IENA bits. Table 22 Maskable Interrupts Assignment 15 IST 1 0 Res. IRQ Number IRQ31 IRQ30 IST The Interrupt Status bits indicate if a maskable interrupt source is signalling an interrupt request. IST[15:1] correspond to IRQ15 to IRQ1 respectively. Because the IRQ0 interrupt is not used, bit 0 always reads back 0. 0 - Interrupt is not active. 1 - Interrupt is active. Interrupt Status Register 1 (ISTAT1) IRQ29 IRQ28 IRQ27 IRQ26 IRQ25 IRQ24 IRQ23 IRQ22 IRQ21 IRQ20 IRQ19 IRQ18 IST The Interrupt Status bits indicate if a maskable interrupt source is signalling an interrupt request. IST[31:16] correspond to IRQ31 to IRQ16, respectively. 0 - Interrupt is not active. 1 - Interrupt is active. IRQ17 IRQ16 IRQ15 IRQ14 IRQ13 IRQ12 IRQ11 IRQ10 IRQ9 IRQ8 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0 TWM (Timer 0) Reserved Reserved Reserved Reserved Reserved Reserved USB Interface DMA Channel 0 DMA Channel 1 DMA Channel 2 DMA Channel 3 Reserved Advanced Audio Interface UART Rx PCM/CVSD Converter ACCESS.bus Interface TA (Timer input A) TB (Timer input B) VTUA (VTU Interrupt Request 1) VTUB (VTU Interrupt Request 2) VTUC (VTU Interrupt Request 3) VTUD (VTU Interrupt Request 4) Microwire/SPI Rx/Tx UART Tx UART CTS MIWU Interrupt 0 MIWU Interrupt 1 MIWU Interrupt 2 MIWU Interrupt 3 Flash Program/Data Memory Reserved Details
10.3.7
The ISTAT1 register is a word-wide read-only register. It indicates which maskable interrupt inputs into the ICU are active. These bits are not affected by the state of the corresponding IENA bits. 15 IST 0
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All reserved or unused interrupt vectors should point to a default or error interrupt handlers.
10.5
NESTED INTERRUPTS
Nested NMI interrupts are always enabled. Nested maskable interrupts are disabled by default, however an interrupt handler can allow nested maskable interrupts by setting the I bit in the PSR. The LPR instruction is used to set the I bit. Nesting of specific maskable interrupts can be allowed by disabling interrupts from sources for which nesting is not allowed, before setting the I bit. Individual maskable interrupt sources can be disabled using the IENAM0 and IENAM1 registers. Any number of levels of nested interrupts are allowed, limited only by the available memory for the interrupt stack.
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CP3UB17
11.0 Triple Clock and Reset
The Triple Clock and Reset module generates a 12 MHz Main Clock and a 32.768 kHz Slow Clock from external crystal networks or external clock sources. It provides various clock signals for the rest of the chip. It also provides the main system reset signal, a power-on reset function, Main Clock prescalers to generate two additional low-speed clocks, and a 32-kHz oscillator start-up delay. Figure 3 is block diagram of the Triple Clock and Reset module.
TWM (Invalid Watchdog Service) Flash Interface (Program/Erase Busy) External Reset
Reset
Device Reset Reset Module Stretched Reset
Power-On-Reset Module (POR)
Stop Main Osc. Preset X1CKI
Stop Main Osc
Start-Up-Delay 14-Bit Timer
X1CKO Main Osc.
Good Main Clock
4-Bit Aux1 Prescaler 4-Bit Aux2 Prescaler Main Clock Div. by 2 8-Bit Prescaler Mux
Auxiliary Clock 1
Auxiliary Clock 2
Slow Clock Prescaler
Slow Clock
X2CKI
32 kHz Osc.
Slow Clock Select Start-Up-Delay 8-Bit Timer Time-out Good Slow Clock
X2CKO
Preset Stop Slow Osc Bypass 32 kHz Osc Fast Clock Prescaler 4-Bit Prescaler Mux System Clock
Fast Clock Select Mux PLL Clock
PLL (x3, x4, or x5) Bypass PLL Good PLL Clock Stop PLL Stop PLL DS006
Figure 3. Triple Clock and Reset Module
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11.1
EXTERNAL CRYSTAL NETWORK
An external crystal network is connected to the X1CKI and X1CKO pins to generate the Main Clock, unless an external clock signal is driven on the X1CKI pin. A similar external crystal network may be used at pins X2CKI and X2CKO for the Slow Clock. If an external crystal network is not used for the Slow Clock, the Slow Clock is generated by dividing the fast Main Clock. The crystal network you choose may require external components different from the ones specified in this datasheet. In this case, consult with National's engineers for the component specifications The crystals and other oscillator components must be placed close to the X1CKI/X1CKO and X2CKI/X2CKO device input pins to keep the printed trace lengths to an absolute minimum. Figure 4 shows the required crystal network at X1CKI/ X1CKO and optional crystal network at X2CKI/X2CKO. Table 23 shows the component specifications for the main
crystal network and Table 24 shows the component specifications for the 32.768 kHz crystal network.
X1CKI/X2CKI
C1
12 MHz/32.768 kHz Crystal X1CKO/X2CKO
C2
GND DS007
Figure 4. External Crystal Network
Table 23 Component Values of the High Frequency Crystal Circuit Component Crystal Parameters Resonance Frequency Type Max. Serial Resistance Max. Shunt Capacitance Load Capacitance Capacitance Values 12 MHz 20 ppm AT-Cut 50 7 pF 22 pF 22 pF Tolerance
N/A
Capacitor C1, C2
20%
Table 24 Component Values of the Low Frequency Crystal Circuit Component Crystal Parameters Resonance Frequency Type Maximum Serial Resistance Maximum Shunt Capacitance Load Capacitance Min. Q factor Capacitor C1, C2 Capacitance Values 32.768 kHz Parallel N-Cut or XY-bar 40 k 2 pF 12.5 pF 40000 25 pF Tolerance
N/A
20%
Choose capacitor component values in the tables to obtain the specified load capacitance for the crystal when combined with the parasitic capacitance of the trace, socket, and package (which can vary from 0 to 8 pF). As a guideline, the load capacitance is: C1 x C2 CL = -------------------- + Cparasitic C1 + C2 C2 > C1 C1 can be trimmed to obtain the desired load capacitance. The start-up time of the 32.768 kHz oscillator can vary from one to six seconds. The long start-up time is due to the high
Q value and high serial resistance of the crystal necessary to minimize power consumption in Power Save mode.
11.2
MAIN CLOCK
The Main Clock is generated by the 12-MHz high-frequency oscillator or driven by an external signal. It can be stopped by the Power Management Module to reduce power consumption during periods of reduced activity. When the Main Clock is restarted, a 14-bit timer generates a Good Main Clock signal after a start-up delay of 32,768 clock cycles. This signal is an indicator that the high-frequency oscillator is stable.
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The Stop Main Osc signal from the Power Management Module stops and starts the high-frequency oscillator. When this signal is asserted, it presets the 14-bit timer to 3FFFh and stops the high-frequency oscillator. When the signal goes inactive, the high-frequency oscillator starts and the 14-bit timer counts down from its preset value. When the timer reaches zero, it stops counting and asserts the Good Main Clock signal.
The PRSFC register must not be modified while the System Clock is derived from the PLL Clock. The System Clock must be derived from the low-frequency oscillator clock while the MODE field is modified.
11.5
SYSTEM CLOCK
The System Clock drives most of the on-chip modules, including the CPU. Typically, it is driven by the Main Clock, but it can also be driven by the PLL. In either case, the clock sig11.3 SLOW CLOCK nal is passed through a programmable divider (scale factors The Slow Clock is necessary for operating the device in re- from /1 to /16). duced power modes and to provide a clock source for mod11.6 AUXILIARY CLOCKS ules such as the Timing and Watchdog Module. The Slow Clock operates in a manner similar to the Main Auxiliary Clock 1 and Auxiliary Clock 2 are generated from Clock. The Stop Slow Osc signal from the Power Manage- Main Clock for use by certain peripherals. Auxiliary Clock 1 ment Module stops and starts the low-frequency (32.768 is available for the Advanced Audio Interface. Auxiliary kHz) oscillator. When this signal is asserted, it presets a 6- Clock 2 is available for the CVSD/PCM transcoder. The Auxbit timer to 3Fh and disables the low-frequency oscillator. iliary clocks may be configured to keep these peripherals When the signal goes inactive, the low-frequency oscillator running when the System Clock is slowed down or suspendstarts, and the 6-bit timer counts down from its preset value. ed during low-power modes. When the timer reaches zero, it stops counting and asserts the Good Slow Clock signal, which indicates that the Slow Clock is stable.
11.7
POWER-ON RESET
The Power-On Reset circuit generates a system reset signal at power-up and holds the signal active for a period of time For systems that do not require a reduced power consump- to allow the crystal oscillator to stabilize. The circuit detects tion mode, the external crystal network may be omitted for a power turn-on condition, which presets a 14-bit timer drivthe Slow Clock. In that case, the Slow Clock can be synthe- en by Main Clock to a value of 3FFFh. This preset value is sized by dividing the Main Clock by a prescaler factor. The defined in hardware and not programmable. Once oscillaprescaler circuit consists of a fixed divide-by-2 counter and tion starts and the clock becomes active, the timer starts a programmable 8-bit prescaler register. This allows a counting down. When the count reaches zero, the 14-bit choice of clock divisors ranging from 2 to 512. The resulting timer stops counting and the internal reset signal is deactiSlow Clock frequency must not exceed 100 kHz. vated (unless the RESET pin is held low). A software-programmable multiplexer selects either the The circuit sets a power-on reset bit upon detection of a prescaled Main Clock or the 32.768 kHz oscillator as the power-on condition. The CPU can read this bit to determine Slow Clock. At reset, the prescaled Main Clock is selected, whether a reset was caused by a power-up or by the RESET ensuring that the Slow Clock is always present initially. Se- input. lection of the 32.768 kHz oscillator as the Slow Clock disables the clock prescaler, which allows the CLK1 oscillator Note: The Power-On Reset circuit cannot be used to detect to be turned off, which reduces power consumption and ra- a drop in the supply voltage. diated emissions. This can be done only if the module de- 11.8 EXTERNAL RESET tects a toggling low-speed oscillator. If the low-speed oscillator is not operating, the prescaler remains available An active-low reset input pin called RESET allows the device to be reset at any time. When the signal goes low, it as the Slow Clock source. generates an internal system reset signal that remains ac11.4 PLL CLOCK tive until the RESET signal goes high again. The PLL Clock is generated by the PLL from the 12 MHz Main Clock by applying a multiplication factor of x3, x4, or x5. The USB interface is clocked directly by the PLL Clock and requires a 48 MHz clock, so a x4 scaling factor must be used if the USB interface is active. To enable the PLL: 1. Set the PLL multiplication factor in PRFSC.MODE. 2. Clear the PLL power-down bit CRCTRL.PLLPWD. 3. Clear the high-frequency clock select bit CRCTRL.FCLK. 4. Read CRCTRL.FCLK, and go back to step 3 if not clear. The CRCTRL.FCLK bit will be clear only after the PLL has stabilized, so software must repeat step 3 until the bit is clear. The clock source can be switched back to the Main Clock by setting the CRCTRL.FCLK bit. www.national.com 52
C GND DS151 R CP3BT1x RESET
If the VCC power supply has slow rise-time. it may be necessary to use an external reset circuit to insure proper device initialization. Figure 5 shows an example of an external reset circuit.
VCC VCC
Figure 5. External Reset Circuit
CP3UB17
The value of R should be less than 50K ohms. The RC time PLLPWD constant of the circuit should be 5 times the power supply rise time. The time constant also should exceed the stabilization time for the high-frequency oscillator.
11.9
CLOCK AND RESET REGISTERS
Table 25 Clock and Reset Registers Name Address FF FC40h FF FC42h FF FC44h FF FC46h Description Clock and Reset Control Register High Frequency Clock Prescaler Register Low Frequency Clock Prescaler Register Auxiliary Clock Prescaler Register ACE1
Table 25 lists the clock and reset registers.
CRCTRL PRSFC PRSSC PRSAC 11.9.1
Clock and Reset Control Register (CRCTRL)
ACE2
The CRCTRL register is a byte-wide read/write register that controls the clock selection and contains the power-on reset status bit. At reset, the CRCTRL register is initialized as described below: 7 6 5 4 3 2 1 0
Reserved
POR ACE2 ACE1 PLLPWD FCLK SCLK
SCLK
FCLK
The Slow Clock Select bit controls the clock POR source used for the Slow Clock. 0 - Slow Clock driven by prescaled Main Clock. 1 - Slow Clock driven by 32.768 kHz oscillator. The Fast Clock Select bit selects between the 12 MHz Main Clock and the PLL as the source used for the System Clock. After reset, the Main Clock is selected. Attempting to switch to the PLL while the PLLPWD bit is set (PLL is turned off) is ignored. Attempting to switch to the PLL also has no effect if the PLL output clock has not stabilized. 0 - The System Clock prescaler is driven by the output of the PLL. 1 - The System Clock prescaler is driven by the 12-MHz Main Clock. This is the default after reset.
The PLL Power-Down bit controls whether the PLL is active or powered down (Stop PLL signal asserted). When this bit is set, the on-chip PLL stays powered-down. Otherwise it is powered-up or it can be controlled by the Power Management Module, respectively. Before software can power-down the PLL in Active mode by setting the PLLPWD bit, the FCLK bit must be set. Attempting to set the PLLPWD bit while the FCLK bit is clear is ignored. The FCLK bit cannot be cleared until the PLL clock has stabilized. After reset this bit is set. 0 - PLL is active. 1 - PLL is powered down. When the Auxiliary Clock Enable bit is set and a stable Main Clock is provided, the Auxiliary Clock 1 prescaler is enabled and generates the first Auxiliary Clock. When the ACE1 bit is clear or the Main Clock is not stable, Auxiliary Clock 1 is stopped. After reset this bit is clear. 0 - Auxiliary Clock 1 is stopped. 1 - Auxiliary Clock 1 is active if the Main Clock is stable. When the Auxiliary Clock Enable 2 bit is set and a stable Main Clock is provided, the Auxiliary Clock 2 prescaler is enabled and generates Auxiliary Clock 2. When the ACE2 bit is clear or the Main Clock is not stable, the Auxiliary Clock 2 is stopped. Auxiliary Clock 2 is used as the clock input for the PCM/CVSD transcoder. After reset this bit is clear. 0 - Auxiliary Clock 2 is stopped. 1 - Auxiliary Clock 2 is active if the Main Clock is stable. Power-On-Reset - The Power-On-Reset bit is set when a power-turn-on condition has been detected. This bit can only be cleared by software, not set. Writing a 1 to this bit will be ignored, and the previous value of the bit will be unchanged. 0 - Software cleared this bit. 1 - Software has not cleared his bit since the last reset.
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11.9.2
High Frequency Clock Prescaler Register (PRSFC)
11.9.3
Low Frequency Clock Prescaler Register (PRSSC)
The PRSFC register is a byte-wide read/write register that holds the 4-bit clock divisor used to generate the high-frequency clock. In addition, the upper three bits are used to control the operation of the PLL. The register is initialized to 4Fh at reset (except in PROG mode.) 7 Res 6 MODE 4 3 FCDIV 0
The PRSSC register is a byte-wide read/write register that holds the clock divisor used to generate the Slow Clock from the Main Clock. The register is initialized to B6h at reset. 7 SCDIV 0
SCDIV FCDIV The Fast Clock Divisor specifies the divisor used to obtain the high-frequency System Clock from the PLL or Main Clock. The divisor is (FCDIV + 1). The PLL MODE field specifies the operation mode of the on-chip PLL. After reset the MODE bits are initialized to 100b, so the PLL is configured to generate a 48-MHz clock. This register must not be modified when the System Clock is derived from the PLL Clock. The System Clock must be derived from the low-frequency oscillator clock while the MODE field is modified. Output Frequency (assumes 12 MHz input clock) Reserved Reserved Reserved 36 MHz 48 MHz 60 MHz Reserved Reserved
MODE
The Slow Clock Divisor field specifies a divisor to be used when generating the Slow Clock from the Main Clock. The Main Clock is divided by a value of (2 x (SCDIV + 1)) to obtain the Slow Clock. At reset, the SCDIV register is initialized to B6h, which generates a Slow Clock rate of 32768.88 Hz. Auxiliary Clock Prescaler Register (PRSAC)
11.9.4
The PRSAC register is a byte-wide read/write register that holds the clock divisor values for prescalers used to generate the two auxiliary clocks from the Main Clock. The register is initialized to FFh at reset. 7 ACDIV2 4 3 ACDIV2 0
MODE2:0
Description
ACDIV1
000 001 010 011 100 101 110 111
Reserved ACDIV2 Reserved Reserved 3x Mode 4x Mode 5x Mode Reserved Reserved
The Auxiliary Clock Divisor 1 field specifies the divisor to be used for generating Auxiliary Clock 1 from the Main Clock. The Main Clock is divided by a value of (ACDIV1 + 1). The Auxiliary Clock Divisor 2 field specifies the divisor to be used for generating Auxiliary Clock 2 from the Main Clock. The Main Clock is divided by a value of (ACDIV2 + 1).
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12.0 Power Management
The Power Management Module (PMM) improves the efficiency of the CP3UB17 by changing the operating mode (and therefore the power consumption) according to the required level of device activity. The device implements four power modes: Active Power Save Idle Halt Table 26 summarizes the differences between power modes: the state of the high-frequency oscillator (on or off), the System Clock source (clock used by most modules), and the clock source used by the Timing and Watchdog Module (TWM). The high-frequency oscillator generates the 12-MHz Main Clock, and the low-frequency oscillator generates a 32.768 kHz clock. The Slow Clock can be driven by the 32.768 kHz clock or a scaled version of the Main Clock. Table 26 Power Mode Operating Summary Mode Active High-Frequency Oscillator On System Clock TWM Clock turned off under software control before switching to a reduced power mode, or they may remain active as long as Main Clock is also active. If the system does not require the PLL output clock, the PLL can be disabled. Alternatively, the Main Clock and the PLL can also be controlled by the Hardware Clock Control function, if enabled. The clock architecture is described in Section 11.0. In Power Save mode, some modules are disabled or their operation is restricted. Other modules, including the CPU, continue to function normally, but operate at a reduced clock rate. Details of each module's activity in Power Save mode are described in each module's descriptions. It is recommended to keep CPU activity at a minimum by executing the WAIT instruction to guarantee low power consumption in the system.
12.3
IDLE MODE
Main Clock Slow Clock Slow Clock None None Slow Clock Slow Clock None
Power Save On or Off Idle Halt On or Off Off
The low-frequency oscillator continues to operate in all four modes and power must be provided continuously to the device power supply pins. In Halt mode, however, Slow Clock does not toggle, and as a result, the TWM timer and Watchdog Module do not operate. For the Power Save and Idle modes, the high-frequency oscillator can be turned on or off under software control, as long as the low-frequency oscillator is used to drive Slow Clock.
In Idle mode, the System Clock is disabled and therefore the clock is stopped to most modules of the device. The PLL and the high-frequency oscillator may be disabled as controlled by register bits. The low-frequency oscillator remains active. The Power Management Module (PMM) and the Timing and Watchdog Module (TWM) continue to operate off the Slow Clock. Auxiliary Clocks 1 and 2 can be turned off under software control before switching to a power saving mode, or they remain active as long as Main Clock is also active. Alternatively, the 12 MHz Main Clock and the PLL can also be controlled by the Hardware Clock Control function, if enabled.
12.4
HALT MODE
12.1
ACTIVE MODE
In Active mode, the high-frequency oscillator is active and generates the 12-MHz Main Clock. The 32.768 kHz oscillator is active and may be used to generate the Slow Clock. The PLL can be active or inactive, as required. Most on-chip modules are driven by the System Clock. The System Clock can be the PLL Clock after a programmable divider or the 12-MHz Main Clock. The activity of peripheral modules is controlled by their enable bits. Power consumption can be reduced in this mode by selectively disabling modules and by executing the WAIT instruction. When the WAIT instruction is executed, the CPU stops executing new instructions until it receives an interrupt signal. After reset, the CP3UB17 is in Active Mode.
In Halt mode, all the device clocks, including the System Clock, Main Clock, and Slow Clock, are disabled. The highfrequency oscillator and PLL are turned off. The low-frequency oscillator continues to operate, however its circuitry is optimized to guarantee lowest possible power consumption. This mode allows the device to reach the absolute minimum power consumption without losing its state (memory, registers, etc.).
12.2
POWER SAVE MODE
In Power Save mode, Slow Clock is used as the System Clock which drives the CPU and most on-chip modules. If Slow Clock is driven by the 32.768 kHz oscillator and no onchip module currently requires the 12-MHz Main Clock, software can disable the high-frequency oscillator to further reduce power consumption. Auxiliary Clocks 1 and 2 can be
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CP3UB17
12.5
CLOCK CONTROL
IDLE
Altogether, three mechanisms control whether the high-frequency oscillator is active, and four mechanisms control whether the PLL is active: Disable Bits: The DMC and DHC bits in the PMMCR register may be used to disable the high-frequency oscillator and PLL, respectively, in Power Save and Idle modes. When used to disable the high-frequency oscillator or PLL, the DMC and DHC bits override the HCC mechanism. Power Management Mode: Halt mode disables the HALT high-frequency oscillator and PLL. Active Mode enables them. The DMC and DHC bits and the HCC mechanism have no effect in Active or Halt mode. PLL Power Down Bit: The PLLPWD bit in the CRCTRL register can be used to disable the PLL in all modes. This bit does not affect the high-frequency oscillator.
12.6
POWER MANAGEMENT REGISTERS
Table 27 Power Management Registers Name Address FF FC60h FF FC62h Description Power Management Control Register Power Management Status Register WBPSM
Table 27 lists the power management registers.
PMMCR PMMSR 12.6.1
Power Management Control Register (PMMCR)
The Power Management Control/Status Register (PMMCR) is a byte-wide, read/write register that controls the operating power mode (Active, Power Save, Idle, or Halt) and enables or disables the high-frequency oscillator in the Power Save and Idle modes. At reset, the non-reserved bits of this register are cleared. The format of the register is shown below. 7 6 5 4 3 2 1 0 DMC PSM If the Power Save Mode bit is clear and the WBPSM bit is clear, writing 1 to the PSM bit causes the device to start the switch to Power Save mode. If the WBPSM bit is set when the PSM bit is written with 1, entry into Power Save mode is delayed until execution of a WAIT instruction. The PSM bit becomes set after the switch to Power Save mode is complete. The PSM bit can be cleared by software, and it can be cleared by hardware when a hardware wake-up event is detected. 0 - Device is not in Power Save mode. DHC 1 - Device is in Power Save mode.
Reserved
DHC DMC WBPSM HALT IDLE PSM
The Idle Mode bit indicates whether the device has entered Idle mode. The WBPSM bit must be set to enter Idle mode. When the IDLE bit is written with 1, the device enters IDLE mode at the execution of the next WAIT instruction. The IDLE bit can be set and cleared by software. It is also cleared by the hardware when a hardware wake-up event is detected. 0 - Device is not in Idle mode. 1 - Device is in Idle mode. The Halt Mode bit indicates whether the device is in Halt mode. Before entering Halt mode, the WBPSM bit must be set. When the HALT bit is written with 1, the device enters the Halt mode at the execution of the next WAIT instruction. When in HALT mode, the PMM stops the System Clock and then turns off the PLL and the high-frequency oscillator. The HALT bit can be set and cleared by software. The Halt mode is exited by a hardware wake-up event. When this signal is set high, the oscillator is started. After the oscillator has stabilized, the HALT bit is cleared by the hardware. 0 - Device is not in Halt mode. 1 - Device is in Halt mode. When the Wait Before Power Save Mode bit is clear, a switch from Active mode to Power Save mode only requires setting the PSM bit. When the WBPSM bit is set, a switch from Active mode to Power Save, Idle, or Halt mode is performed by setting the PSM, IDLE, or HALT bit, respectively, and then executing a WAIT instruction. Also, if the DMC or DHC bits are set, the high-frequency oscillator and PLL may be disabled only after a WAIT instruction is executed and the Power Save, Idle, or Halt mode is entered. 0 - Mode transitions may occur immediately. 1 - Mode transitions are delayed until the next WAIT instruction is executed. The Disable Main Clock bit may be used to disable the high-frequency oscillator in Power Save and Idle modes. In Active mode, the high-frequency oscillator is enabled without regard to the DMC value. In Halt mode, the high-frequency oscillator is disabled without regard to the DMC value. The DMC bit is cleared by hardware when a hardware wakeup event is detected. 0 - High-frequency oscillator is only disabled in Halt mode or when disabled by the HCC mechanism. 1 - High-frequency oscillator is also disabled in Power Save and Idle modes. The Disable High-Frequency (PLL) Clock bit and the CRCTRL.PLLPWD bit may be used to disable the PLL in Power Save and Idle modes. When the DHC bit is clear (and PLLPWD = 0), the PLL is enabled in these modes. If the DHC bit is set, the PLL is disabled in
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Power Save and Idle mode. In Active mode with the CRCTRL.PLLPWD bit set, the PLL is enabled without regard to the DHC value. In Halt mode, the PLL is disabled without regard to the DMC value. The DHC bit is cleared by hardware when a hardware wake-up event is detected. 0 - PLL is disabled only by entering Halt mode or setting the CRCTRL.PLLPWD bit. 1 - PLL is also disabled in Power Save or Idle mode. 12.6.2 Power Management Status Register (PMMSR)
12.7
SWITCHING BETWEEN POWER MODES
Switching from a higher to a lower power consumption mode is performed by writing an appropriate value to the Power Management Control/Status Register (PMCSR). Switching from a lower power consumption mode to the Active mode is usually triggered by a hardware interrupt. Figure 6 shows the four power consumption modes and the events that trigger a transition from one mode to another.
Reset HAL = 1 & "WAIT" T Active Mode PSM = 1 or WBPSM = 1 & PSM = 1 & "WAIT"
The Management Status Register (PMMR) is a byte-wide, read/write register that provides status signals for the various clocks. The reset value of PMSR register bits 0 to 2 depend on the status of the clock sources monitored by the PMM. The upper 5 bits are clear after reset. The format of the register is shown below. 7 Reserved 3 2 1 0 OLC
WBPSM = 1 & Idle = 1 & "WAIT"
Power Save Mode
HW Event
WBPSM =1 & Idle =1 & "WAIT"
Idle Mode IDLE = 1
HW Event
OHC OMC
Halt Mode Note: HW Event = MIWU wake-up or NMI
HW Event DS008
OLC
OMC
OHC
The Oscillating Low Frequency Clock bit indicates whether the low-frequency oscillator is producing a stable clock. When the low-frequency oscillator is unavailable, the PMM will not switch to Power Save, Idle, or Halt mode. 0 - Low-frequency oscillator is unstable, disabled, or not oscillating. 1 - Low-frequency oscillator is available. The Oscillating Main Clock bit indicates whether the high-frequency oscillator is producing a stable clock. When the high-frequency oscillator is unavailable, the PMM will not switch to Active mode. 0 - High-frequency oscillator is unstable, disabled, or not oscillating. 1 - High-frequency oscillator is available. The Oscillating High Frequency (PLL) Clock bit indicates whether the PLL is producing a stable clock. Because the PMM tests the stability of the PLL clock to qualify power mode state transitions, a stable clock is indicated when the PLL is disabled. This removes the stability of the PLL clock from the test when the PLL is disabled. When the PLL is enabled but unstable, the PMM will not switch to Active mode. 0 - PLL is enabled but unstable. 1 - PLL is stable or disabled (CRCTRL.PLLPWD = 0).
Figure 6. Power Mode State Diagram Some of the power-up transitions are based on the occurrence of a wake-up event. An event of this type can be either a maskable interrupt or a non-maskable interrupt (NMI). All of the maskable hardware wake-up events are monitored by the Multi-Input Wake-Up (MIWU) Module, which is active in all modes. Once a wake-up event is detected, it is latched until an interrupt acknowledge cycle occurs or a reset is applied. A wake-up event causes a transition to the Active mode and restores normal clock operation, but does not start execution of the program. It is the interrupt handler associated with the wake-up source (MIWU or NMI) that causes program execution to resume. 12.7.1 Active Mode to Power Save Mode
A transition from Active mode to Power Save mode is performed by writing a 1 to the PMMCR.PSM bit. The transition to Power Save mode is either initiated immediately or at execution of the next WAIT instruction, depending on the state of the PMMCR.WBPSM bit. For an immediate transition to Power Save mode (PMMCR.WBPSM = 0), the CPU continues to operate using the low-frequency clock. The PMCSR.PSM bit becomes set when the transition to the Power Save mode is completed. For a transition at the next WAIT instruction (PMMCR.WBPSM = 1), the CPU continues to operate in Active mode until it executes a WAIT instruction. At execution of the WAIT instruction, the device enters the Power Save mode, and the CPU waits for the next interrupt event. In this case, the PMMCR.PSM bit becomes set when it is written, even before the WAIT instruction is executed.
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12.7.2
Entering Idle Mode
12.7.6
Wake-Up Transition to Active Mode
Entry into Idle mode is performed by writing a 1 to the PMC- A hardware wake-up event switches the device directly from SR.IDLE bit and then executing a WAIT instruction. The Idle Power Save, Idle, or Halt mode to Active mode. Hardware mode can be entered only from the Active or Power Save wake-up events are: mode. For entry from Active mode, the PMMCR.WBPSM bit Non-Maskable Interrupt (NMI) must be set before the WAIT instruction is executed. Valid wake-up event on a Multi-Input Wake-Up channel 12.7.3 Disabling the High-Frequency Clock When a wake-up event occurs, the on-chip hardware perWhen the low-frequency oscillator is used to generate the forms the following steps: Slow Clock, power consumption can be reduced further in 1. Clears the PMCSR.DMC bit, which enables the highthe Power Save or Idle mode by disabling the high-frequenfrequency clock (if it was disabled). cy oscillator. This is accomplished by writing a 1 to the PMC- 2. Waits for the PMCSR.OMC bit to become set, which inSR.DHF bit before executing the WAIT instruction that puts dicates that the high-frequency clock is operating and the device in the Power Save or Idle mode. The high-freis stable. quency clock is turned off only after the device enters the 3. Clears the PMCSR.DHC bit, which enables the PLL. Power Save or Idle mode. 4. Waits for the PMCSR.OHC bit to become set. The CPU operates on the low-frequency clock in Power 5. Switches the device into Active mode. Save mode. It can turn off the high-frequency clock at any 12.7.7 Power Mode Switching Protection time by writing a 1 to the PMCSR.DHF bit. The high-frequency oscillator is always enabled in Active mode and al- The Power Management Module has several mechanisms ways disabled in Halt mode, without regard to the to protect the device from malfunctions caused by missing or unstable clock signals. PMCSR.DHF bit setting. Immediately after power-up and entry into Active mode, software must wait for the low-frequency clock to become stable before it can put the device in Power Save mode. It should monitor the PMCSR.OLC bit for this purpose. Once this bit is set, Slow Clock is stable and Power Save mode can be entered. 12.7.4 Entering Halt Mode The PMCSR.OHC, PMCSR.OMC, and PMCSR.OLC bits indicate the current status of the PLL, high-frequency oscillator, and low-frequency oscillator, respectively. Software can check the appropriate bit before switching to a power mode that requires the clock. A set status bit indicates an operating, stable clock. A clear status bit indicates a clock that is disabled, not available, or not yet stable. (Except in the case of the PLL, which has a set status bit when disabled.)
Entry into Halt mode is accomplished by writing a 1 to the PMCSR.HALT bit and then executing a WAIT instruction. During a power mode transition, if there is a request to Halt mode can be entered only from Active or Power Save switch to a mode with a clear status bit, the switch is delayed mode. For entry from Active mode, the PMCSR.WBPSM bit until that bit is set by the hardware. must be set before the WAIT instruction is executed. When the system is built without an external crystal network 12.7.5 Software-Controlled Transition to Active Mode for the low-frequency clock, Main Clock is divided by a presA transition from Power Save mode to Active mode can be caler factor to produce the low-frequency clock. In this situaccomplished by either a software command or a hardware ation, Main Clock is disabled only in the Halt mode, and wake-up event. The software method is to write a 0 to the cannot be disabled for the Power Save or Idle mode. PMCSR.PSM bit. The value of the register bit changes only after the transition to the Active mode is completed. Without an external crystal network for the low-frequency clock, the device comes out of Halt or Idle mode and enters If the high-frequency oscillator is disabled for Power Save Active mode with Main Clock driving Slow Clock. operation, the oscillator must be enabled and allowed to sta- Note: For correct operation in the absence of a low-frebilize before the transition to Active mode. To enable the quency crystal, the X2CKI pin must be tied low (not left floathigh-frequency oscillator, software writes a 0 to the PMC- ing) so that the hardware can detect the absence of the SR.DMC bit. Before writing a 0 to the PMCSR.PSM bit, soft- crystal. ware must first monitor the PMCSR.OMC bit to determine when the oscillator has stabilized.
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13.0 Multi-Input Wake-Up
The Multi-Input Wake-Up Unit (MIWU) monitors its 16 input channels for a software-selectable trigger condition. On detection of a trigger condition, the module generates an interrupt request and if enabled, a wake-up request. A wake-up request can be used by the power management unit to exit the Halt, Idle, or Power Save mode and return to the active mode. An interrupt request generates an interrupt to the CPU (interrupt IRQ2-IRQ5), which allows an interrupt handler to respond to MIWU events. The wake-up event only activates the clocks and CPU, but does not by itself initiate execution of any code. It is the interrupt request associated with the MIWU that gets the CPU to start executing code, by jumping to the corresponding interrupt handler. Therefore, setting up the MIWU interrupt handler is essential for any wake-up operation. There are four interrupt requests that can be routed to the ICU as shown in Figure 7. Each of the 16 MIWU channels can be programmed to activate one of these four interrupt requests. The MIWU channels are named WUI0 through WUI15, as shown in Table 28. Table 28 MIWU Sources MIWU Channel WUI0 WUI1 WUI2 WUI3 WUI4 WUI5 WUI6 WUI7 WUI8 WUI9 WUI10 WUI11 WUI12 WUI13 WUI14 WUI15 Source TWM-T0OUT ACCESS.bus Reserved MWCS CTS RXD Reserved AAI SFS USB Wake-Up PI6 PG0 PG1 PG2 PG3 PG6 PG7 WKED The Wake-Up Edge Detection bits control the edge sensitivity for MIWU channels. The WKED15:0 bits correspond to the WUI[15:0] channels, respectively. 0 - Triggered on rising edge (low-to-high transition). 1 - Triggered on falling edge (high-to-low transition). WKPCL 13.1.1 FF FC8Ah The MIWU is active at all times, including the Halt mode. All device clocks are stopped in this mode. Therefore, detecting an external trigger condition and the subsequent setting of the pending bit are not synchronous to the System Clock.
13.1
MULTI-INPUT WAKE-UP REGISTERS
Table 29 Multi-Input Wake-Up Registers Name Address FF FC80h FF FC82h FF FC8Ch FF FC84h FF FC86h FF FC88h Description Wake-Up Edge Detection Register Wake-Up Enable Register Wake-Up Interrupt Enable Register Wake-Up Interrupt Control Register 1 Wake-Up Interrupt Control Register 2 Wake-Up Pending Register Wake-Up Pending Clear Register
Table 29 lists the MIWU unit registers.
WKEDG WKENA WKIENA WKICTL1 WKICTL2 WKPND
Wake-Up Edge Detection Register (WKEDG)
The WKEDG register is a word-wide read/write register that controls the edge sensitivity of the MIWU channels. The WKEDG register is cleared upon reset, which configures all channels to be triggered on rising edges. The register format is shown below. 15 WKED 0
Each channel can be configured to trigger on rising or falling edges, as determined by the setting in the WKEDG register. Each trigger event is latched into the WKPND register. If a trigger event is enabled by its respective bit in the WKENA register, an active wake-up/interrupt signal is generated. Software can determine which channel has generated the active signal by reading the WKPND register.
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Peripheral BUS
15
........... WKIENA
0
WKICTL 1-2
WUI0
0 4 EXINT3:0 to ICU
Encoder
WUI15 WKEDG
15 WKPND
Wake-Up Signal To Power Mgt
WKENA 15 ........... 0 DS009
Figure 7. Multi-Input Wake-Up Module Block Diagram 13.1.2 Wake-Up Enable Register (WKENA) 13.1.4 Wake-Up Interrupt Control Register 1 (WKICTL1)
The Wake-Up Enable (WKENA) register is a word-wide read/write register that individually enables or disables wake-up events from the MIWU channels. The WKENA register is cleared upon reset, which disables all wake-up/interrupt channels. The register format is shown below. 15 WKEN 0
The WKICTL1 register is a word-wide read/write register that selects the interrupt request signal for the associated MIWU channels WUI7:0. At reset, the WKICTL1 register is cleared, which selects MIWU Interrupt Request 0 for all eight channels. The register format is shown below. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WKIN WKIN WKIN WKIN WKIN WKIN WKIN WKIN TR7 TR6 TR5 TR4 TR3 TR2 TR1 TR0 WKEN The Wake-Up Enable bits enable and disable the MIWU channels. The WKEN15:0 bits correspond to the WUI15:0 channels, respectively. 0 - MIWU channel wake-up events disabled. 1 - MIWU channel wake-up events enabled. Wake-Up Interrupt Enable Register (WKIENA)
WKINTR
13.1.3
The WKIENA register is a word-wide read/write register that enables and disables interrupts from the MIWU channels. The register format is shown below. 15 WKIEN 0
The Wake-Up Interrupt Request Select fields select which of the four MIWU interrupt requests are activated for the corresponding channel. 00 - Selects MIWU interrupt request 0. 01 - Selects MIWU interrupt request 1. 10 - Selects MIWU interrupt request 2. 11 - Selects MIWU interrupt request 3.
WKIEN
The Wake-Up Interrupt Enable bits control whether MIWU channels generate interrupts. 0 - Interrupt disabled. 1 - Interrupt enabled. 60
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13.1.5
Wake-Up Interrupt Control Register 2 (WKICTL2)
13.1.7
Wake-Up Pending Clear Register (WKPCL)
The WKICTL2 register is a word-wide read/write register that selects the interrupt request signal for the associated MIWU channels WUI15 to WUI8. At reset, the WKICTL2 register is cleared, which selects MIWU Interrupt Request 0 for all eight channels. The register format is shown below. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
The Wake-Up Pending Clear (WKPCL) register is a wordwide write-only register that lets the CPU clear bits in the WKPND register. Writing a 1 to a bit position in the WKPCL register clears the corresponding bit in the WKPND register. Writing a 0 has no effect. Do not modify this register with instructions that access the register as a read-modify-write operand, such as the bit manipulation instructions. Reading this register location returns undefined data. Therefore, do not use a read-modify-write sequence (such as the SBIT instruction) to set individual bits. Do not attempt to read the register, then perform a logical OR on the register value. Instead, write the mask directly to the register address. The register format is shown below. 0 WKCL
WKIN WKIN WKIN WKIN WKIN WKIN WKIN WKIN TR15 TR14 TR13 TR12 TR11 TR10 TR9 TR8
WKINTR
The Wake-Up Interrupt Request Select fields select which of the four MIWU interrupt re15 quests are activated for the corresponding channel. 00 - Selects MIWU interrupt request 0. 01 - Selects MIWU interrupt request 1. 10 - Selects MIWU interrupt request 2. WKCL 11 - Selects MIWU interrupt request 3. Wake-Up Pending Register (WKPND)
13.1.6
The WKPND register is a word-wide read/write register in which the Multi-Input Wake-Up module latches any detected trigger conditions. The CPU can only write a 1 to any bit position in this register. If the CPU attempts to write a 0, it has no effect on that bit. To clear a bit in this register, the CPU must use the WKPCL register. This implementation prevents a potential hardware-software conflict during a read-modify-write operation on the WKPND register. This register is cleared upon reset. The register format is shown below. 15 WKPD 0
Writing 1 to a bit clears it. 0 - Writing 0 has no effect. 1 - Writing 1 clears the corresponding bit in the WKPD register.
13.2
PROGRAMMING PROCEDURES
To set up and use the Multi-Input Wake-Up function, use the following procedure. Performing the steps in the order shown will prevent false triggering of a wake-up condition. This same procedure should be used following a reset because the wake-up inputs are left floating, resulting in unknown data on the input pins. 1. Clear the WKENA register to disable the MIWU channels. 2. For inputs that originate from an I/O port (the usual case), set the corresponding bit in the port direction register to configure the I/O pin as an input. 3. Write the WKEDG register to select the desired type of edge sensitivity (clear for rising edge, set for falling edge). 4. Set all bits in the WKPCL register to clear any pending bits in the WKPND register. 5. Set up the WKICTL1 and WKICTL2 registers to define the interrupt request signal used for each channel. 6. Set the bits in the WKENA register corresponding to the wake-up channels to be activated. To change the edge sensitivity of a wake-up channel, use the following procedure. Performing the steps in the order shown will prevent false triggering of a wake-up/interrupt condition. 1. Clear the WKENA bit associated with the input to be reprogrammed. 2. Write the new value to the corresponding bit position in the WKEDG register to reprogram the edge sensitivity of the input. 3. Set the corresponding bit in the WKPCL register to clear the pending bit in the WKPND register. 4. Set the same WKENA bit to re-enable the wake-up function.
WKPD
The Wake-Up Pending bits indicate which MIWU channels have been triggered. The WKPD[15:0] bits correspond to the WUI[15:0] channels. Writing 1 to a bit sets it. 0 - Trigger condition did not occur. 1 - Trigger condition occurred.
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14.0 Input/Output Ports
Each device has up to 40 software-configurable I/O pins, organized into five 8-bit ports. The ports are named Port B, Port C, Port G, Port H, and Port I. In addition to their general-purpose I/O capability, the I/O pins of Ports G, H, and I have alternate functions for use with on-chip peripheral modules such as the UART or the Multi-Input Wake-Up module. The alternate functions of all I/O pins are shown in Table 2. Ports B and C are used as the 16-bit data bus when an external bus is enabled (100-pin devices only). This alternate function is selected by enabling the DEV or ERE operating environments, not by programming the port registers. Different pins within the same port can be individually configured to operate in different modes. Figure 8 is a diagram showing the I/O port pin logic. The register bits, multiplexers, and buffers allow the port pin to be configured into the various operating modes.The output buffer is a TRI-STATE buffer with weak pull-up capability. The weak pull-up, if used, prevents the port pin from going to an undefined state when it operates as an input.
To reduce power consumption, input buffers configured for general-purpose I/O are only enabled when they are read. When configured for an alternate function, the input buffers are enabled continuously. To minimize power consumption, The I/O pin characteristics are fully programmable. Each pin input signals to enabled buffers must be held within 0.2 volts can be configured to operate as a TRI-STATE output, push- of the VCC or GND voltage. pull output, weak pull-up input, or high-impedance input. The electrical characteristics and drive capabilities of the input and output buffers are described in Section 26.0.
D PxALTS Register
Q
D PxALT Register
Q
VCC
D PxWKPU Register
Q
Weak Pull-Up Enable
Alt. A Device Direction Alt. B Device Direction D PxDIR Register Pin Alt. A Device Data Outout Alt. B Device Data Outout D PxDOUT Register Q Data Out Q Output Enable
Alt. A Data Input PxDIN Register Alt. B Data Input 1 Data In Read Strobe Data In
Analog Input
DS190
Figure 8. I/O Port Pin Logic
14.1
PORT REGISTERS
Each port has an associated set of memory-mapped registers used for controlling the port and for holding the port data:
PxALT: Port alternate function register PxALTS: Port alternate function select register PxDIR: Port direction register PxDIN: Port data input register PxDOUT: Port data output register PxWPU: Port weak pull-up register PxHDRV: Port high drive strength register
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Table 30 Port Registers Table 30 Port Registers Name PBALT PBDIR PBDIN PBDOUT PBWPU PBHDRV PBALTS PCALT PCDIR PCDIN PCDOUT PCWPU PCHDRV PCALTS PGALT PGDIR PGDIN PGDOUT PGWPU PGHDRV PGALTS Address FF FB00h FF FB02h FF FB04h FF FB06h FF FB08h FF FB0Ah FF FB0Ch FF FB10h FF FB12h FF FB14h FF FB16h FF FB18h FF FB1Ah FF FB1Ch FF FCA0h FF FCA2h FF FCA4h FF FCA6h FF FCA8h FF FCAAh FF FCACh Description PHALT Port B Alternate Function Register PHDIR Port B Direction Register PHDIN Port B Data Input Register PHDOUT Port B Data Output Register PHWPU Port B Weak Pull-Up Register PHHDRV Port B High Drive Strength Register PHALTS Port B Alternate Function Select Register PIALT Port C Alternate Function Register PIDIR Port C Direction Register PIDIN Port C Data Input Register PIDOUT Port C Data Output Register PIWPU Port C Weak Pull-Up Register PIHDRV Port C High Drive Strength Register PIALTS Port C Alternate Function Select Register Port G Alternate Function Register Port G Direction Register Port G Data Input Register Port G Data Output Register Port G Weak Pull-Up Register Port G High Drive Strength Register Port G Alternate Function Select Register FF FEECh FF FEEAh FF FEE8h FF FEE6h FF FEE4h FF FEE2h FF FEE0h FF FCCCh FF FCCAh FF FCC8h FF FCC6h FF FCC4h FF FCC2h FF FCC0h Name Address Description Port H Alternate Function Register Port H Direction Register Port H Data Input Register Port H Data Output Register Port H Weak Pull-Up Register Port H High Drive Strength Register Port H Alternate Function Select Register Port I Alternate Function Register Port I Direction Register Port I Data Input Register Port I Data Output Register Port I Weak Pull-Up Register Port I High Drive Strength Register Port I Alternate Function Select Register
In the descriptions of the ports and port registers, the lowercase letter "x" represents the port designation, either B, C, G, H, or I. For example, "PxDIR register" means any one of the port direction registers: PBDIR, PCDIR, PGDIR, PHDIR, or PIDIR. All of the port registers are byte-wide read/write registers, except for the port data input registers, which are read-only registers. Each register bit controls the function of the corresponding port pin. For example, PGDIR.2 (bit 2 of the PGDIR register) controls the direction of port pin PG2.
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14.1.1
Port Alternate Function Register (PxALT)
14.1.3
Port Data Input Register (PxDIN)
The PxALT registers control whether the port pins are used for general-purpose I/O or for their alternate function. Each port pin can be controlled independently. A clear bit in the alternate function register causes the corresponding pin to be used for general-purpose I/O. In this configuration, the output buffer is controlled by the direction register (PxDIR) and the data output register (PxDOUT). The input buffer is visible to software as the data input register (PxDIN). A set bit in the alternate function register (PxALT) causes the corresponding pin to be used for its peripheral I/O function. When the alternate function is selected, the output buffer data and TRI-STATE configuration are controlled by signals from the on-chip peripheral device.
The data input register (PxDIN) is a read-only register that returns the current state on each port pin. The CPU can read this register at any time even when the pin is configured as an output. 7 PxDIN 0
PxDIN
The PxDIN bits indicate the state on the corresponding port pin. 0 - Pin is low. 1 - Pin is high.
14.1.4 Port Data Output Register (PxDOUT) A reset operation clears the port alternate function registers, which initializes the pins as general-purpose I/O ports. The data output register (PxDOUT) holds the data to be This register must be enabled before the corresponding al- driven on output port pins. In this configuration, writing to the register changes the output value. Reading the register ternate function is enabled. returns the last value written to the register. 7 PxALT 0 A reset operation leaves the register contents unchanged. At power-up, the PxDOUT registers contain unknown values. 0 PxDOUT
PxALT
7 The PxALT bits control whether the corresponding port pins are general-purpose I/O ports or are used for their alternate function by an on-chip peripheral. PxDOUT 0 - General-purpose I/O selected. 1 - Alternate function selected. Port Direction Register (PxDIR)
14.1.2
The port direction register (PxDIR) determines whether each port pin is used for input or for output. A clear bit in this register causes the corresponding pin to operate as an input, which puts the output buffer in the high-impedance state. A set bit causes the pin to operate as an output, which enables the output buffer.
The PxDOUT bits hold the data to be driven on pins configured as outputs in general-purpose I/O mode. 0 - Drive the pin low. 1 - Drive the pin high. Port Weak Pull-Up Register (PxWPU)
14.1.5
The weak pull-up register (PxWPU) determines whether the port pins have a weak pull-up on the output buffer. The pullup device, if enabled by the register bit, operates in the genA reset operation clears the port direction registers, which eral-purpose I/O mode whenever the port output buffer is disabled. In the alternate function mode, the pull-ups are alinitializes the pins as inputs. ways disabled. 7 PxDIR 7 PxDIR The PxDIR bits select the direction of the corresponding port pin. 0 - Input. 1 - Output. PxWPU 0 0 A reset operation clears the port weak pull-up registers, which disables all pull-ups.
PxWPU
The PxWPU bits control whether the weak pull-up is enabled. 0 - Weak pull-up disabled. 1 - Weak pull-up enabled.
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14.1.6
Port High Drive Strength Register (PxHDRV) Table 31 Port Pin PG0 PG1 PG2 Alternate Function Select PxALTS = 0 RXD TXD RTS CTS Reserved SRFS Reserved Reserved MSK MDIDO MDODI MWCS SCK SFS STD SRD Reserved Reserved Reserved Reserved Reserved Reserved WUI9 TA PxALTS = 1 WUI10 WUI11 WUI12 WUI13 TB NMI WUI14 WUI15 TIO1 TIO2 TIO3 TIO4 TIO5 TIO6 TIO7 TIO8 Reserved Reserved SRCLK Reserved Reserved Reserved Reserved Reserved
The PxHDRV register is a byte-wide, read/write register that controls the slew rate of the corresponding pins. The high drive strength function is enabled when the corresponding bits of the PxHDRV register are set. In both GPIO and alternate function modes, the drive strength function is enabled by the PxHDRV registers. At reset, the PxHDRV registers are cleared, making the ports low speed. 7 PxHDRV 0
PG3 PG4 PG5 PG6 PG7 PH0 PH1 PH2 PH3 PH4
PxHDRV
The PxHDRV bits control whether output pins are driven with slow or fast slew rate. 0 - Slow slew rate. 1 - Fast slew rate. Port Alternate Function Select Register (PxALTS)
14.1.7
The PxALTS register selects which of two alternate functions are selected for the port pin. These bits are ignored unless the corresponding PxALT bits are set. Each port pin can be controlled independently. 7 PxALTS 0
PH5 PH6 PH7
PxALTS
The PxALTS bits select among two alternate functions. Table 31 shows the mapping of the PxALTS bits to the alternate functions. Unused PxALTS bits must be clear.
PI0 PI1 PI2 PI3 PI4 PI5 PI6 PI7
14.2
OPEN-DRAIN OPERATION
A port pin can be configured to operate as an inverting open-drain output buffer. To do this, the CPU must clear the bit in the data output register (PxDOUT) and then use the port direction register (PxDIR) to set the value of the port pin. With the direction register bit set (direction = out), the value zero is forced on the pin. With the direction register bit clear (direction = in), the pin is placed in the TRI-STATE mode. If desired, the internal weak pull-up can be enabled to pull the signal high when the output buffer is in TRISTATE mode.
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15.0 USB Controller
The USB node is an integrated USB node controller that fea- ing a resume command on the USB bus, which signals an tures enhanced DMA support with many automatic data interrupt to the CPU. handling features. It is compatible with USB specification versions 1.0 and 1.1. It integrates the required USB transceiver, a Serial Interface Engine (SIE), and USB endpoint (EP) FIFOs. Seven endpoint pipes are supported: one for the mandatory control endpoint and six to support interrupt, bulk, and isochronous endpoints. Each endpoint pipe has a dedicated FIFO, 8 bytes for the control endpoint and 64 bytes for the other endpoints.
15.1
15.1.1
FUNCTIONAL STATES
Line Condition Detection
At any given time, the USB node is in one of the following states Table 32 State Descriptions State NodeOperational NodeSuspend NodeResume NodeReset Descriptions Normal operation Device operation suspend due to USB inactivity Device wake-up from suspended state Device reset
The NodeSuspend, NodeResume, or NodeReset line condition causes a transition from one operating state to another. These conditions are detected by specialized hardware and reported in the Alternate Event (ALTEV) register. If interrupts are enabled, an interrupt is generated on the occurrence of any of the specified conditions. In addition to the dedicated input to the ICU for generating interrupts on these USB state changes, a wake-up signal is sent to the MIWU (see Section 13.0) when any activity is detected on the USB, if the bus was in the Idle state and the USB node is in the NodeSuspend state. The MIWU can be programmed to generate an edge-triggered interrupt when this occurs. NodeOperational This is the normal operating state of the node. In this state, the node is configured for operation on the USB. NodeSuspend A USB node is expected to enter NodeSuspend state when 3 ms have elapsed without any detectable bus activity. The USB node looks for this event and signals it by setting the SD3 bit in the ALTEV register, which causes an interrupt, to be generated (if enabled). Software should respond by putting the USB node in the NodeSuspend state. The USB node can resume normal operation under software control in response to a local event in the device. It can wake up the USB bus via a NodeResume, or when detect-
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NodeResume If the host has enabled remote wake-ups from the node, the USB node can initiate a remote wake-up. Once software detects the event, which wakes up the bus, it releases the USB node from NodeSuspend state by initiating a NodeResume on the USB using the NFSR register. The node software must ensure at least 5 ms of Idle on the USB. While in NodeResume state, a constant "K" is signalled on the USB. This should last for at least 1 ms and no more than 5 ms, after which the USB host should continue sending the NodeResume signal for at least an additional 20 ms, and then completes the NodeResume operation by issuing the End Of Packet (EOP) sequence. To successfully detect the EOP, software must enter the USB NodeOperational state by setting the NFSR register. If no EOP is received from the host within 100 ms, software must re-initiate NodeResume. NodeReset When detecting a NodeResume or NodeReset signal while in NodeSuspend state, the USB node can signal this to the CPU by generating an interrupt. USB specifications require that a device must be ready to respond to USB tokens within 10 ms after wake-up or reset.
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15.2
15.2.1
ENDPOINT OPERATION
Address Detection
15.2.2
Transmit and Receive Endpoint FIFOs
The USB node uses a total of seven transmit and receive FIFOs: one bidirectional transmit and receive FIFO for the Packets are broadcast from the host controller to all nodes mandatory control endpoint, three transmit FIFOs, and on the USB network. Address detection is implemented in three receive FIFOs. As shown in Table 33, the bidirectional hardware to allow selective reception of packets and to per- FIFO for the control endpoint is 8 bytes deep. The additional mit optimal use of CPU bandwidth. One function address unidirectional FIFOs are 64 bytes each for both transmit and with seven different endpoint combinations is decoded in receive. Each FIFO can be programmed for one exclusive parallel. If a match is found, then that particular packet is re- USB endpoint, used together with one globally decoded ceived into the FIFO; otherwise it is ignored. USB function address. Software must not enable both transThe incoming USB Packet Address field and Endpoint field mit and receive FIFOs for endpoint zero at any given time. are extracted from the incoming bit stream. Then the adTable 33 Endpoint FIFO Sizes dress field is compared to the Function Address register (FADR). If a match is detected, the Endpoint field is comTX FIFO RX FIFO pared to all of the Endpoint Control registers (EPCn) in parEndpoint allel. A match then causes the payload data to be received Size Size Number Name Name or transmitted using the respective endpoint FIFO. (Bytes) (Bytes) 0
USB Packet ADDR Field Endpoint Field
FIFO0 (bidirectional, 8 bytes) 64 64 64 TXFIFO1 TXFIFO2 TXFIFO3 64 64 64 RXFIFO1 RXFIFO2 RXFIFO3
1 2 3
FADR Register
Match
4
Match
5
Receive/ Transmit FIFO0 EPC0 Register Transmit FIFO1 EPC1 Register Receive FIFO1 EPC2 Register Transmit FIFO2 EPC3 Register Receive FIFO2 EPC4Register Transmit FIFO3 EPC5 Register Receive FIFO3 EPC6 Register DS049
6
If two endpoints in the same direction are programmed with the same endpoint number and both are enabled, data is received or transmitted to/from the endpoint with the lower number, until that endpoint is disabled for bulk or interrupt transfers, or becomes full or empty for ISO transfers. For example, if receive EP2 and receive EP4 both use endpoint 5 and are both isochronous, the first OUT packet is received into EP2 and the second OUT packet into EP4, assuming no software interaction in between. For ISO endpoints, this allows implementing a ping-pong buffer scheme together with the frame number match logic. Endpoints in different directions programmed with the same endpoint number operate independently.
Figure 9.
USB Function Address/Endpoint Decoding
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Bidirectional Control Endpoint FIFO0 Operation FIFO0 should be used for the bidirectional control endpoint 0. It can be configured to receive data sent to the default address with the DEF bit in the EPC0 register. Isochronous transfers are not supported for the control endpoint. The Endpoint 0 FIFO can hold a single receive or transmit packet with up to 8 bytes of data. Figure 10 shows the basic operation in both receive and transmit direction. Note: The actual current operating state is not directly visible to software.
FLUSH Bit, TXC0 Register FLUSH Bit, RXC0 Register
Transmit Endpoint FIFO Operation (TXFIFO1, TXFIFO2, TXFIFO3) The Transmit FIFOs for endpoints 1, 3, and 5 support bulk, interrupt, and isochronous USB packet transfers larger than the actual FIFO size. Therefore, software must update the FIFO contents while the USB packet is transmitted on the bus. Figure 11 illustrates the operation of the transmit FIFOs.
FLUSH (Resets TXRP and TXWP)
TXRP TFnS - 1 0X0
+
IDLE Write to TXD0
+
RX_EN Bit, RXC0 Register TX FIFO n
TXFL = TXWP - TXRP
TXWP
TXFILL SETUP Token
RXWAIT
+
TX_EN Bit, TXC0 Register TX_EN Bit, TXC0 Register (Zero-Length Packet) TXWAIT
OUT or SETUP Token TCOUNT = TXRP - TXWP (= TFnS - TXFL) Transmission Done FIFO0 Empty (All Data Read) DS051
Figure 11. Transmit FIFO Operation TFnS
RX
IN Token
TXRP
DS050
TX
Figure 10. Endpoint 0 Operation A packet written to the FIFO is transmitted if an IN token for the respective endpoint is received. If an error condition is detected, the packet data remains in the FIFO and transmission is retried with the next IN token. The FIFO contents can be flushed to allow response to an OUT token or to write new data into the FIFO for the next IN token. If an OUT token is received for the FIFO, software is informed that the FIFO has received data only if there was no error condition (CRC or STUFF error). Erroneous receptions are automatically discarded. TXFL
TXWP
TCOUNT
The Transmit FIFO n Size is the total number of bytes available within the FIFO. The Transmit Read Pointer is incremented every time the Endpoint Controller reads from the transmit FIFO. This pointer wraps around to zero if TFnS is reached. TXRP is never incremented beyond the value of the write pointer TXWP. An underrun condition occurs if TXRP equals TXWP and an attempt is made to transmit more bytes when the LAST bit in the TXCMDx register is not set. The Transmit Write Pointer is incremented every time software writes to the transmit FIFO. This pointer wraps around to zero if TFnS is reached. If an attempt is made to write more bytes to the FIFO than actual space available (FIFO overrun), the write to the FIFO is ignored. If so, TCOUNT is checked for an indication of the number of empty bytes remaining. The Transmit FIFO Level indicates how many bytes are currently in the FIFO. A FIFO warning is issued if TXFL decreases to a specific value. The respective WARNn bit in the FWR register is set if TXFL is equal to or less than the number specified by the TFWL bit in the TXCn register. The Transmit FIFO Count indicates how many empty bytes can be filled within the transmit FIFO. This value is accessible by software in the TXSn register. www.national.com
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Receive Endpoint FIFO Operation (RXFIFO1, RXFIFO2, RXFIFO3) The Receive FIFOs for endpoints 2, 4, and 6 support bulk, interrupt, and isochronous USB packet transfers larger than the actual FIFO size. If the packet length exceeds the FIFO size, software must read the FIFO contents while the USB packet is being received on the bus. Figure 12 shows the detailed behavior of receive FIFOs.
FLUSH (Resets RXRP and RXWP)
15.3
USB CONTROLLER REGISTERS
The USB node has a set of memory-mapped registers that can be read/written from the CPU bus to control the USB interface. Some register bits are reserved; reading from these bits returns undefined data. Reserved register bits must always be written with 0. Table 34 USB Controller Registers Name MCNTRL Address FF FD80h FF FD8Ah FF FD8Ch FF FD90h FF FD8Eh FF FD92h FF FD94h FF FD96h FF FD98h FF FD9Ah FF FD9Ch FF FD9Eh FF FDA0h FF FDA2h FF FDA4h FF FDA6h FF FD88h FF FDA8h FF FDAAh FF FDACh FF FDAEh FF FDB0h FF FDB2h Description Main Control Register Node Functional State Register Main Event Register Alternate Event Register Main Mask Register Alternate Mask Register Transmit Event Register Transmit Mask Register Receive Event Register Receive Mask Register NAK Event Register NAK Mask Register FIFO Warning Event Register FIFO Warning Mask Register Frame Number High Byte Register Frame Number Low Byte Register Function Address Register DMA Control Register DMA Event Register DMA Mask Register Mirror Register DMA Count Register DMA Error Register
RXRP RFnS - 1 0X0
NFSR
RCOUNT = RXWP - RXRF
+ +
MAEV ALTEV
RX FIFO n
RXWP
MAMSK ALTMSK TXEV TXMSK RXEV RXMSK NAKEV NAKMSK FWEV FWMSK FNH FNL FAR DMACNTRL DMAEV DMAMSK MIR DMACNT DMAERR
+
RXFL = RXRP - RXWP (= RFnS
- RCOUNT)
DS052
Figure 12. Receive FIFO Operation RFnS RXRP The Receive FIFO n Size is the total number of bytes available within the FIFO. The Receive Read Pointer is incremented with every read by software from the receive FIFO. This pointer wraps around to zero if RFnS is reached. RXRP is never incremented beyond the value of RXWP. If an attempt is made to read more bytes than are actually available (FIFO underrun), the last byte is read repeatedly. The Receive Write Pointer is incremented every time the Endpoint Controller writes to the receive FIFO. This pointer wraps around to zero if RFnS is reached. An overrun condition occurs if RXRP equals RXWP and an attempt is made to write an additional byte. The Receive FIFO Level indicates how many more bytes can be received until an overrun condition occurs with the next write to the FIFO. A FIFO warning is issued if RXFL decreases to a specific value. The respective WARNn bit in the FWR register is set if RXFL is equal to or less than the number specified by the RFWL bit in the RXCn register. The Receive FIFO Count indicates how many bytes can be read from the receive FIFO. This value is accessible by software from the RXSn register.
RXWP
RXFL
RCOUNT
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Table 34 USB Controller Registers Name EPC0 EPC1 EPC2 EPC3 EPC4 EPC5 EPC6 TXS0 TXS1 TXS2 TXS3 TXC0 TXC1 TXC2 TXC3 TXD0 TXD1 TXD2 TXD3 RXS0 RXS1 RXS2 Address FF FDC0h FF FDD0h FF FDD8h FF FDE0h FF FDDE8h FF FDF0h FF FDF8h FF FDC4h FF FDD4h FF FDE4h FF FDF4h FF FDC6h FF FDD6 FF FDE6h FF FDF6h FF FDC2h FF FDD2h FF FDE2h FF FDF2h FF FDCCh FF FDDCh FF FDECh Description Endpoint Control 0 Register Endpoint Control 1 Register Endpoint Control 2 Register Endpoint Control 3 Register Endpoint Control 4 Register Endpoint Control 5 Register Endpoint Control 6 Register Transmit Status 0 Register Transmit Status 1 Register Transmit Status 2 Register Transmit Status 3 Register Transmit Command 0 Register Transmit Command 1 Register Transmit Command 2 Register Transmit Command 3 Register Transmit Data 0 Register Transmit Data 1 Register Transmit Data 2 Register Transmit Data 3 Register Receive Status 0 Register Receive Status 1 Register Receive Status 2 Register
Table 34 USB Controller Registers Name RXS3 RXC0 RXC1 RXC2 RXC3 RXD0 RXD1 RXD2 RXD3 15.3.1 Address FF FDFCh FF FDCEh FF FDDEh FF FDEEh FF FDFEh FF FDCAh FF FDDAh FF FDEAh FF FDFAh Description Receive Status 3 Register Receive Command 0 Register Receive Command 1 Register Receive Command 2 Register Receive Command 3 Register Receive Data 0 Register Receive Data 2 Register Receive Data 2 Register Receive Data 3 Register
Main Control Register (MCNTRL)
The MCNTRL register controls the main functions of the USB node. The MCNTRL register provides read/write access from the CPU bus. Reserved bits must be written with 0, and they return 0 when read. It is clear after reset. 7 Reserved 4 3 NAT 2 1 0 USBEN
Reserved
USBEN
The USB Enable controls whether the USB module is enabled. If the USB module is disabled, the 48 MHz clock within the USB node is stopped, all USB registers are initialized to their reset state, and the USB transceiver forces SE0 on the bus to prevent the hub from detected the USB node. The USBEN bit is clear after reset. 0 - The USB module is disabled. 1 - The USB module is enabled.
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NAT
The Node Attached indicates that this node is ready to be detected as attached to USB. When clear, the transceiver forces SE0 on the USB node controller to prevent the hub (to which this node is connected) from detecting an attach event. After reset or when the USB node is disabled, this bit is cleared to give the device time before it must respond to commands. After this bit has been set, the device no longer drives the USB and should be ready to receive Reset signaling from the hub. 0 - Node not ready to be detected as attached. 1 - Node ready to be detected as attached.
15.3.2
Node Functional State Register (NFSR)
The NFSR register reports and controls the current functional state of the USB node. The NFSR register provides read/write access. It is clear after reset. 7 Reserved 2 1 NFS 0
NFS
The Node Functional State bits set the node state, as shown in Table 35. Software should initiate all required state transitions according to the respective status bits in the Alternate Event (ALTEV) register.
Table 35 USB Functional States NFS Node State Description This is the USB Reset state. This is entered upon a module reset or by software upon detection of a USB Reset. Upon entry, all endpoint pipes are disabled. DEF in the Endpoint Control 0 (EPC0) register and AD_EN in the Function Address (FAR) register should be cleared by software on entry to this state. On exit, DEF should be reset so the device responds to the default address. In this state, resume "K" signalling is generated. This state should be entered by software to initiate a remote wake-up sequence by the device. The node must remain in this state for at least 1 ms and no more than 15 ms.
00
NodeReset
01 10
NodeResume
NodeOperational This is the normal operational state for operation on the USB bus. Suspend state should be entered by software on detection of a Suspend event while in Operational state. While in Suspend state, the transceivers operate in their low-power suspend mode. All endpoint controllers and the bits TX_EN, LAST, and RX_EN are reset, while all other internal states are frozen. On detection of bus activity, the RESUME bit in the ALTEV register is set. In response, software can cause entry to NodeOperational state.
11
NodeSuspend
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15.3.3
Main Event Register (MAEV)
RX_EV
The Main Event Register summarizes and reports the main events of the USB transactions. This register provides readonly access. The MAEV register is clear after reset. 7 6 5 4 3 2 1 0
INTR RX_EV ULD NAK FRAME TX_EV ALT WARN INTR WARN The Warning Event bit indicates whether one of the unmasked bits in the FIFO Warning Event (FWEV) register has been set. This bit is cleared by reading the FWEV register. 0 - No warning event occurred. 1 - A warning event has occurred. The Alternate Event bit indicates whether one of the unmasked ALTEV register bits has been set. This bit is cleared by reading the ALTEV register. 0 - No alternate event has occurred. 1 - An alternate event has occurred. The Transmit Event bit indicates whether any of the unmasked bits in the Transmit Event (TXEV) register (TXFIFOn or TXUNDRNn) is set. Therefore, it indicates that an IN transaction has been completed. This bit is cleared when all the TX_DONE bits and the TXUNDRN bits in each Transmit Status (TXSn) register are cleared. 0 - No transmit event has occurred. 1 - A transmit event has occurred. The Frame Event bit indicates whether the frame counter has been updated with a new value, due to receipt of a valid SOF packet on the USB or to an artificial update if the frame counter was unlocked or a frame was missed. This bit is cleared when the register is read. 0 - The frame counter has not been updated. 1 - Frame counter has been updated. The Negative Acknowledge Event indicates whether one of the unmasked NAK Event (NAKEV) register bits has been set. This bit is cleared when the NAKEV register is read. 0 - No unmasked NAK event has occurred. 1 - An unmasked NAK event has occurred. The Unlocked/Locked Detected bit is set when the frame timer has either entered unlocked condition from a locked condition, or has re-entered a locked condition from an unlocked condition as determined by the UL bit in the Frame Number (FNH or FNL) register. This bit is cleared when the register is read. 0 - Frame timer has not entered an unlocked condition from a locked condition or reentered a locked condition from an unlocked condition. 1 - Frame timer has either entered an unlocked condition from a locked condition or re-entered a locked condition from an unlocked condition.
The Receive Event bit is set if any of the unmasked bits in the Receive Event (RXEV) register is set. It indicates that a SETUP or OUT transaction has been completed. This bit is cleared when all of the RX_LAST bits in each Receive Status (RXSn) register and all RXOVRRN bits in the RXEV register are cleared. 0 - No receive event has occurred. 1 - A receive event has occurred. The Master Interrupt Enable bit is hardwired to 0 in the Main Event (MAEV) register; bit 7 in the Main Mask (MAMSK) register is the Master Interrupt Enable. 0 - USB interrupts disabled. 1 - USB interrupts enabled. Main Mask Register (MAMSK)
ALT
15.3.4
TX_EV
The MAMSK register masks out events reported in the MAEV registers. A set bit enables the interrupts for the respective event in the MAEV register. If the corresponding bit is clear, interrupt generation for this event is disabled. This register provides read/write access. The MAMSK register is clear after reset. 7 6 5 4 3 2 1 0
INTR RX_EV ULD NAK FRAME TX_EV ALT WARN
15.3.5
Alternate Event Register (ALTEV)
FRAME
The ALTEV register summarizes and reports the further events in the USB node. This register provides read-only access. The ALTEV register is clear after reset. 7 6 5 4 3 2 1 0
RESUME RESET SD5
SD3 EOP DMA Reserved
DMA
NAK
UL
EOP
The DMA Event bit indicates that one of the unmasked bits in the DMA Event (DMAEV) register has been set. The DMA bit is readonly and clear, when the DMAEV register is cleared. 0 - No DMA event has occurred. 1 - A DMA event has occurred. The End of Packet bit indicates whether a valid EOP sequence has been detected on the USB. It is used when this device has initiated a Remote wake-up sequence to indicate that the Resume sequence has been acknowledged and completed by the host. This bit is cleared when the register is read. 0 - No EOP sequence detected. 1 - EOP sequence detected.
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SD3
SD5
RESET
RESUME
The Suspend Detect 3 ms bit is set after 3 ms of IDLE have been detected on the upstream port, indicating that the device should be suspended. The suspend occurs under software control by writing the suspend value to the Node Functional State (NFSR) register. This bit is cleared when the register is read. 0 - No 3 ms in IDLE has been detected. 1 - 3 ms in IDLE has been detected. The Suspend Detect 5 ms bit is set after 5 ms of IDLE have been detected on the upstream port, indicating that this device is permitted to perform a remote wake-up operation. The resume may be initiated under software control by writing the resume value to the NFSR register. This bit is cleared when the register is read. 0 - No 5 ms in IDLE has been detected. 1 - 5 ms in IDLE has been detected. The Reset bit is set when 2.5 s of SEO have been detected on the upstream port. In response, the functional state should be reset (NFS in the NFSR register is set to RESET), where it must remain for at least 100 s. The functional state can then return to Operational state. This bit is cleared when the register is read. 0 - No 2.5 s in SEO have been detected. 1 - 2.5 s in SEO have been detected. The Resume bit indicates whether resume signalling has been detected on the USB when the device is in Suspend state (NFS in the NFSR register is set to SUSPEND), and a non-IDLE signal is present on the USB, indicating that this device should begin its wakeup sequence and enter Operational state. This bit is cleared when the register is read. 0 - No resume signalling detected. 1 - Resume signalling detected.
15.3.7
Transmit Event Register (TXEV)
The TXEV register reports the current status of the FIFOs, used by the three Transmit Endpoints. The TXEV register is clear after reset. It provides read-only access. 7 TXUDRRN 4 3 TXFIFO 0
TXFIFO
TXUDRRN
The Transmit FIFO n bits are copies of the TX_DONE bits from the corresponding Transmit Status registers (TXSn). A bit is set when the IN transaction for the corresponding transmit endpoint n has been completed. These bits are cleared when the corresponding TXSn register is read. The Transmit Underrun n bits are copies of the respective TX_URUN bits from the corresponding Transmit Status registers (TXSn). Whenever any of the Transmit FIFOs underflows, the respective TXUDRRN bit is set. These bits are cleared when the corresponding Transmit Status register is read. Note: Since Endpoint 0 implements a store and forward principle, an underrun condition for FIFO0 cannot occur. This results in the TXUDRRN0 bit always being read as 0.
15.3.8
Transmit Mask Register (TXMSK)
The TXMSK register is used to select the bits of the TXEV registers, which causes the TX_EV bit in the MAEV register to be set. When a bit is set and the corresponding bit in the TXEV register is set, the TX_EV bit in the MAEV register is set. When clear, the corresponding bit in the TXEV register does not cause TX_EV to be set. The TXMSK register provides read/write access. It is clear after reset. 7 TXUDRRN 4 3 TXFIFO 0
15.3.6
Alternate Mask Register (ALTMSK)
A set bit in the ALTMSK register enables automatic setting of the ALT bit in the MAEV register when the respective event in the ALTEV register occurs. Otherwise, setting MAEV.ALT bit is disabled. The ALTMSK register is clear after reset. It provides read/write access from the CPU bus. 7 6 5 4 3 2 1 0
RESUME RESET SD5
SD3 EOP DMA Reserved
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15.3.9
Receive Event Register (RXEV)
15.3.11 NAK Event Register (NAKEV) A bit in the NAKEV register is set when a Negative Acknowledge (NAK) was generated by the corresponding endpoint. The NAKEV register provides read-only access from the CPU bus. It is clear after reset. 7 OUT 4 3 IN 0
The RXEV register reports the current status of the FIFO, used by the three Receive Endpoints. The RXEV register is clear after reset. It provides read-only access from the CPU bus. 7 RXOVRRN 4 3 RXFIFO 0
RXFIFO
RXOVRRN
The Receive FIFO n are set whenever either RX_ERR or RX_LAST in the respective Receive Status registers (RXSn) are set. Reading the corresponding RXSn register automatically clears these bits. The USB node discards all packets for Endpoint 0 received with errors. This is necessary in case of retransmission due to media errors, ensuring that a good copy of a SETUP packet is captured. Otherwise, the FIFO may potentially be tied up, holding corrupted data and unable to receive a retransmission of the same packet (the RXFIFO0 bit only reflects the value of RX_LAST for Endpoint 0). If data streaming is used for the receive endpoints (EP2, EP4 and EP6), software must check the respective RX_ERR bits to ensure the packets received are not corrupted by errors. The Receive Overrun n bits are set when an overrun condition is indicated in the corresponding receive FIFO n. They are cleared when the register is read. Software must check the respective RX_ERR bits that packets received for the other receive endpoints (EP2, EP4 and EP6) are not corrupted by errors, as these endpoints support data streaming (packets which are longer than the actual FIFO depth).
IN
OUT
The IN n bits are set when a NAK handshake is generated for an enabled address/endpoint combination (AD_EN in the Function Address, FAR, register is set and EP_EN in the Endpoint Control, EPCx, register is set) in response to an IN token. These bits are cleared when the register is read. The OUT n bits are set when a NAK handshake is generated for an enabled address/ endpoint combination (AD_EN in the FAR register is set and EP_EN in the EPCx register is set) in response to an OUT token. These bits are not set if NAK is generated as result of an overrun condition. They are cleared when the register is read.
15.3.12 NAK Mask Register (NAKMSK) The NAKMSK register is used to select the bits of the NAKEV register, which cause the NAK bit in the MAEV register to be set. When set and the corresponding bit in the NAKEV register is set, the NAK bit in the MAEV register is set. When cleared, the corresponding bit in the NAKEV register does not cause NAK to be set. The NAKMSK register provides read/write access. It is clear after reset. 7 OUT 4 3 IN 0
15.3.10 Receive Mask Register (RXMSK) The RXMSK register is used to select the bits of the RXEV register, which cause the RX_EV bit in the MAEV register to be set. When set and the corresponding bit in the RXEV register is set, RX_EV bit in the MAEV register is set. When clear, the corresponding bit in the RXEV register does not cause the RX_EV bit to be set. The RXMSK register provides read/write access. This register is clear after reset. 7 RXOVRRN 4 3 RXFIFO 0
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15.3.13 FIFO Warning Event Register (FWEV) The FWEV register signals whether a receive or transmit FIFO has reached its warning limit. It reports the status for all FIFOs, except for the Endpoint 0 FIFO, as no warning limit can be specified for this FIFO. The FWEV register provides read-only access from the CPU bus. It is clear after reset. 7 RXWARN3:1 5 4 Res. 3 TXWARN3:1 1 0 Res.
15.3.15 Frame Number High Byte Register (FNH) The FNH register contains the three most significant bits (MSB) of the current frame counter as well as status and control bits for the frame counter. This register is loaded with C0h after reset. It provides access from the CPU bus as described below. 7 MF 6 UL 5 RFC 4 3 2 FN10:8 0
Reserved
FN10:8 TXWARN3:1 The Transmit Warning n bits are set when the respective transmit endpoint FIFO reaches the warning limit, as specified by the TFWL bits of the respective TXCn register, and transmission from the respective endpoint is enabled. These bits are cleared when the warning condition is cleared by either writing new data to the FIFO when the FIFO is flushed, or when transmission is done, as indicated by the TX_DONE bit in the TXSn register. RXWARN3:1 The Receive Warning n bits are set when the respective receive endpoint FIFO reaches the warning limit, as specified by the RFWL bits of the respective EPCx register. These bits are cleared when the warning condition is cleared by either reading data from the FIFO or when the FIFO is flushed. 15.3.14 FIFO Warning Mask Register (FWMSK) The FWMSK register selects which FWEV bits are reported in the MAEV register. A set FWMSK bit with the corresponding bit in the FWEV register set, causes the WARN bit in the RFC MAEV register to be set. When clear, the corresponding bit in the FWEV register does not cause WARN to be set. The FWMSK register provides read/write access. This register is clear after reset. 7 RXWARN3:1 5 4 Res. 3 TXWARN3:1 1 0 Res. UL
The Frame Number field holds the three most significant bits (MSB) of the current frame number, received in the last SOF packet. If a valid frame number is not received within 12060 bit times (Frame Length Maximum, FLMAX, with tolerance) of the previous change, the frame number is incremented artificially. If two successive frames are missed or are incorrect, the current FN is frozen and loaded with the next frame number from a valid SOF packet. If the frame number low byte was read by software before reading the FNH register, software actually reads the contents of a buffer register which holds the value of the three frame number bits of this register when the low byte was read. Therefore, the correct sequence to read the frame number is: FNL, FNH. Read operations to the FNH register, without first reading the Frame Number Low Byte (FNL) register directly, read the actual value of the three MSBs of the frame number. The FN bits provide read-only access. On reset, the FN bits are cleared. The Reset Frame Count bit is used to reset the frame number to 000h. This bit always reads as 0. Due to the synchronization elements the frame counter reset actually occurs a maximum of 3 USB clock cycles (12 MHz) plus 2.5 CPU clock cycles after the write to the RFC bit. 0 - Writing 0 has no effect. 1 - Writing 1 resets the frame counter. The Unlock Flag bit indicates that at least two frames were received without an expected frame number, or that no valid SOF was received within 12060 bit times. If this bit is set, the frame number from the next valid SOF packet is loaded in FN. The UL bit provides read-only access. After reset, this bit is set. This bit is set by the hardware and is cleared by reading the FNH register. 0 - No condition indicated. 1 - At least two frames were received without an expected frame number, or no valid SOF was received within 12060 bit times.
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MF
The Missed SOF bit is set when the frame number in a valid received SOF does not match the expected next value, or when an SOF is not received within 12060 bit times. The MF bit provides read-only access. On reset, this bit is set. This bit is set by the hardware and is cleared by reading the FNH register. 0 - No condition indicated. 1 - The frame number in a valid SOF does not match the expected next value, or no valid SOF was received within 12060 bit times.
15.3.18 Control Register (DMACNTRL) The DMACNTRL register controls the main DMA functions of the USB node. The DMACTRL register provides read/ write access. This register is clear after reset. 7 DEN 6 IGNRXTGL 5 4 3 2 DSRC 0
DTGL ADMA DMOD
DSRC
15.3.16 Frame Number Low Byte Register (FNL) The FNL register holds the low byte of the frame number, as described above. To ensure consistency, reading this low byte causes the three frame number bits in the FNH register to be locked until this register is read. The correct sequence to read the frame number is: FNL first, followed by FNH. This register provides read-only access. After reset, the FNL register is clear. 7 FN7:0 0
The DMA Source bit field holds the binary-encoded value that specifies which of the endpoints, 1 to 6, is enabled for DMA support. The DSRC bits are cleared on reset. Table 36 summarizes the DSRC bit settings. Table 36 DSRC Bit Description DSRC 000 001 010 011 100 Endpoint Number 1 2 3 4 5 6 Reserved
Note: If the frame counter is updated due to a receipt of a valid SOF or an artificial update (i.e. missed frame or unlocked/locked detect), it will take the synchronization elements a maximum of 2.5 CPU clock cycles to update the FNH and FNL registers. 15.3.17 Function Address Register (FAR) The Function Address Register specifies the device function address. The different endpoint numbers are set for each endpoint individually using the Endpoint Control registers. The FAR register provides read/write access. After reset, this register is clear. If the DEF bit in the Endpoint Control 0 register is set, Endpoint 0 responds to the default address. 7 AD_EN 6 AD 0
101 11x
DMOD
AD
AD_EN
The Address field holds the 7-bit function ad- ADMA dress used to transmit and receive all tokens addressed to this device. The Address Enable bit controls whether the AD field is used for address comparison. If not, the device does not respond to any token on the USB bus. 0 - The device does not respond to any token on the USB bus. 1 - The AD field is used for address comparison.
The DMA Mode bit specifies when a DMA request is issued. If clear, a DMA request is issued on transfer completion. For transmit endpoints EP1, EP3, and EP5, the data is completely transferred, as indicated by the TX_DONE bit (to fill the FIFO with new transmit data). For receive endpoints EP2, EP4, and EP6, this is indicated by the RX_LAST bit. When the DMOD bit is set, a DMA request is issued when the respective FIFO warning bit is set. The DMOD bit is cleared after reset. 0 - DMA request is issued on transfer completion. 1 - DMA request is issued when the respective FIFO warning bit is set. The Automatic DMA bit enables Automatic DMA (ADMA) and automatically enables the selected receive or transmit endpoint. Before ADMA mode can be enabled, the DEN bit in the DMA Control (DMACNTRL) register must be cleared. ADMA mode functions until any bit in the DMA Event (DMAEV) register is set, except for NTGL. To initiate ADMA mode, all bits in the DMAEV register must be cleared, except for NTGL. 0 - Automatic DMA disabled. 1 - Automatic DMA enabled.
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DTGL
The DMA Toggle bit is used to determine the initial state of Automatic DMA (ADMA) operations. Software initially sets this bit if starting with a DATA1 operation, and clears this bit if starting with a DATA0 operation. Writes to this bit also update the NTGL bit in the DMAEV register. IGNRXTGL The Ignore RX Toggle controls whether the compare between the NTGL bit in the DMAEV register and the TOGGLE bit in the respective RXSn register is ignored during receive operations. If the compare is ignored, a mismatch DCNT of the bits during a receive operation does not stop ADMA operation. If the compare is not ignored, the ADMA stops in case of a mismatch of the two toggle bits. After reset, this bit is cleared. 0 - Compare toggle bits. 1 - Ignore toggle bits. DEN The DMA Enable bit enables DMA mode. If DSIZ DMA mode is disabled and the current DMA cycle has been completed (or was not yet issued) the DMA transfer is terminated. This bit is cleared after reset. 0 - DMA mode disabled. 1 - DMA mode enabled. 15.3.19 DMA Event Register (DMAEV) The DMAEV register bits are used in ADMA mode. Bits 0 to 3 may cause an interrupt if not cleared, even if the device is not set to ADMA mode. Until all of these bits are cleared, ARDY ADMA mode cannot be initiated. Conversely, ADMA mode is automatically terminated when any of these bits are set. The DMAEV register provides access from the CPU bus as described below. It is clear after reset. 7 6 5 4 3 2 1 0
Reserved
NTGL ARDY DSIZ DCNT DERR DSHLT
DSHLT
DERR
The DMA Software Halt bit is set when ADMA operations have been halted by software. This NTGL bit is set by the hardware only after the DMA engine completes any necessary cleanup operations and returns to Idle state. The DSHLST bits provide read access and can only be written with a 0 from the CPU bus. After reset these bits are cleared. 0 - No software ADMA halt. 1 - ADMA operations have been halted by software. The DMA Error bit is set to indicate that a packet has not been received or transmitted correctly. It is also set, if the TOGGLE bit in the RXSx/TXSx register does not equal the NTGL bit in the DMAEV register after packet reception/transmission. (Note that this comparison is made before the NTGL bit changes state due to packet transfer). For receiving, the DERR bit is equivalent to the RX_ERR bit. For transmitting, the DERR bit is equivalent to the 78
TX_DONE bit (set) and the ACK_STAT bit (not set). If the AEH bit in the DMA Error Count (DMAERR) register is set, the DERR bit is not set until DMAERRCNT in the DMAERR register is cleared, and another error is detected. Errors are handled as specified in the DMAERR register. The DERR bit provides read access and can only be written with a 0 from the CPU bus. After reset this bit is cleared. 0 - No DMA error occurred. 1 - DMA error occurred. The DMA Count bit is set when the DMA Count (DMACNT) register is 0 (see the DMACNT register for more information). The DCNT bit provides read access and can only be written with a 0 from the CPU bus. After reset this bit is cleared. 0 - DMACNT register is not 0. 1 - DMACNT register is 0. The DMA Size bit is only significant for DMA receive operations. It indicates, by being set, that a packet has been received which is less than the full length of the FIFO. This normally indicates the end of a multi-packet transfer. The DSIZ bit provides read access and can only be written with a 0 from the CPU bus. After reset this bit is cleared. 0 - No condition indicated. 1 - A packet has been received which is less than the full length of the FIFO. The Automatic DMA Ready bit is set when the ADMA mode is ready and active. After setting the DMACNTRL.ADMA bit and the active USB transaction (if any) is finished and the specified endpoint (DMACNTRL.DSRC) is flushed, the USB node enters ADMA mode. This bit is automatically cleared when the ADMA mode is finished and the current DMA operation is completed. After reset the ARDY bit is cleared. 0 - ADMA mode not ready. 1 - ADMA mode ready and active. The Next Toggle bit determines the toggle state of the next data packet sent (if transmitting), or the expected toggle state of the next data packet (if receiving). This bit is initialized by writing to the DTGL bit of the DMACNTRL register. It then changes state with every packet sent or received on the endpoint presently selected by DSRC[2:0]. If DTGL write operation occurs simultaneously with the bit update operation, the write takes precedence. If transmitting, whenever ADMA operations are in progress the DTGL bit overrides the corresponding TOGGLE bit in the TXCx register. In this way, the alternating data toggle occurs correctly on the USB. Note that there is no corresponding mask bit for this event because it is not used to generate interrupts. The NTGL bit provides read-only access from the CPU bus and is cleared after reset.
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15.3.20 DMA Mask Register (DMAMSK) Any set bit in the DMAMSK register enables automatic setting of the DMA bit in the ALTEV register when the respective event in the DMAEV register occurs. Otherwise, setting the DMA bit is disabled. For a description of bits 0 to 3, see the DMAEV register. The DMAMSK register provides read/ write access. After reset it is clear. Reading reserved bits returns undefined data. 7 Reserved 4 3 2 1 0
15.3.23 DMA Error Register (DMAERR) The DMAERR register holds the 7-bit DMA error counter and a control bit to specify DMA error handling. The DMAERR register provides read/write access. It is clear after reset. 7 AEH 6 DMAERRCNT 0
DSIZ DCNT DERR DSHLT
15.3.21 Mirror Register (MIR) The MIR register is a read-only register. Because reading it does not alter the state of the TXSn or RXSn register to which it points, software can freely check the status of the channel. At reset it is initialized to 1Fh. 7 STAT 0
STAT
The Status field mirrors the status bits of the transmitter or receiver n selected by the DSRC[2:0] field in the DMACNTRL register (DMA need not be active or enabled). It corresponds to TXSn or RXSn, respectively.
15.3.22 DMA Count Register (DMACNT) The DMACNT register specifies a maximum count for ADMA operations. The DMACNT register provides read/ write access. After reset this register is clear. 7 DCOUNT 0
DCOUNT
The DMA Count field is decremented on completion of a DMA operation until it reaches 0. Then the DCNT bit in the DMA Event register is set, only when the next successful DMA operation is completed. This register does not underflow. For receive operations, this count decrements when the packet is received successfully, and then transferred to memory using DMA. For transmit operations, this count decrements when the packet is transferred from memory using DMA, and then transmitted successfully. Software loads DCOUNT with (number of packets to transfer) - 1. If a DMACNT write operation occurs simultaneously with the decrement operation, the write takes precedence.
DMAERRCNT The DMA Error Counter, together with the automatic error handling feature, defines the maximum number of consecutive bus errors before ADMA mode is stopped. Software can set the 7-bit counter to a preset value. Once ADMA is started, the counter decrements from the preset value by 1 every time a bus error is detected. Every successful transaction resets the counter back to the preset value. When ADMA mode is stopped, the counter is also set back to the preset value. If the counter reaches 0 and another erroneous packet is detected, the DERR bit in the DMA Event register is set. This register cannot underrun. Software loads DMAERRCNT with 3D (maximum number of allowable transfer attempts) - 1. A write access to this register is only possible when ADMA is inactive. Otherwise, it is ignored. Reading from this register while ADMA is active returns the current counter value. Reading from it while ADMA is inactive returns the preset value. The counter decrements only if the AEH bit is set (automatic error handling activated). AEH The Automatic Error Handling bit has two different meanings, depending on the current mode: Non-Isochronous mode--This mode is used for bulk, interrupt and control transfers. Setting AEH in this mode enables automatic handling of packets containing CRC or bit-stuffing errors. If this bit is set during transmit operations, the USB node automatically reloads the FIFO and reschedules the packet to which the host did not return an ACK. If this bit is clear, automatic error handling ceases. If this bit is set during receive operations, a packet received with an error (as specified in the DERR bit description in the DMAEV register) is automatically flushed from the FIFO being used so that the packet can be received again. If this bit is cleared, automatic error handling ceases. Isochronous mode--Setting this bit allows the USB node to ignore packets received with errors (as specified in the DERR bit description in the DMAMSK register). If this bit is set during receive operations, the USB node is automatically flushed and the receive FIFO is reset to www.national.com
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receive the next packet. The erroneous packet is ignored and not transferred via DMA. If this bit is cleared, automatic error handling ceases. 15.3.24 Endpoint Control 0 Register (EPC0) The EPC0 register controls the mandatory Endpoint 0. It is clear after reset. Reserved bits read undefined data. 7 STALL 6 DEF 5 4 3 EP 0
15.3.25 Transmit Status 0 Register (TXS0) The TXS0 register reports the transmit status of the mandatory Endpoint 0. It is loaded with 08h after reset. This register allows read-only access from the CPU bus. 7 6 5 4 3 TCOUNT 0
Res. ACK_STAT TX_DONE Res.
Reserved
TCOUNT
EP
DEF
STALL
The Endpoint Address field holds the 4-bit endpoint address. For Endpoint 0, these bits are hardwired to 0000b. Writing a 1 to any of the EP bits is ignored. The Default Address aids in the transition from the default address to the assigned address. When set, the device responds to the default address without regard to the contents of FAR6-0/EP03-0 fields. When an IN packet is transmitted for the endpoint, the DEF bit is automatically cleared. This bit provides read/ write access from the CPU bus. After reset, this bit is clear. The transition from the default address 00000000000b to an address assigned during bus enumeration may not occur in the middle of the SET_ADDRESS control sequence. This is necessary to complete the control sequence. However, the address must change immediately after this sequence finishes in order to avoid errors when another control sequence immediately follows the SET_ADDRESS command. On USB reset, software has 10 ms for set-up, and should write 80h to the FAR register and 00h to the EPC0 register. On receipt of a SET_ADDRESS command, software must write 40h to the EPC0 register and 80h ORed with assigned_function_address to the FAR register. It must then queue a zero length IN packet to complete the status phase of the SET_ADDRESS control sequence. 0 - Do not respond to the default address. 1 - Respond to default address. The Stall bit can be used to enable STALL handshakes under the following conditions: The transmit FIFO is enabled and an IN token is received. The receive FIFO is enabled and an OUT token is received. A SETUP token does not cause a STALL handshake to be generated when this bit is set. After transmitting the STALL handshake, the RX_LAST and the TX_DONE bits in the respective Receive/Transmit Status registers are set. This bit allows read/write access from the CPU bus. After reset this bit is cleared. 0 - Disable STALL handshakes. 1 - Enable STALL handshakes. 80
TX_DONE
ACK_STAT
The Transmission Count field indicates the number of empty bytes available in the FIFO. This field is never larger than 8 for Endpoint 0. The Transmission Done bit indicates whether a packet has completed transmission. The TX_DONE bit is cleared when this register is read. 0 - No completion of packet transmission has occurred. 1 - A packet has completed transmission. The Acknowledge Status bit indicates the status, as received from the host, of the ACK for the packet previously sent. This bit is to be interpreted when TX_DONE is set. It is set when an ACK is received; otherwise, it remains cleared. This bit is cleared when this register is read. 0 - No ACK received. 1 - ACK received.
15.3.26 Transmit Command 0 Register (TXC0) The TXC0 register controls the mandatory Endpoint 0 when used in transmit direction. This register allows read/write access from the CPU bus. It is clear after reset. Reading reserved bits returns undefined data. 7 5 4 3 2 1 0
Reserved
IGN_IN FLUSH TOGGLE Res. TX_EN
TX_EN
TOGGLE
The Transmission Enable bit enables data transmission from the FIFO. It is cleared by hardware after transmitting a single packet, or a STALL handshake, in response to an IN token. It must be set by software to start packet transmission. The RX_EN bit in the Receive Command 0 (RXC0) register takes precedence over this bit; i.e. if the RX_EN bit is set, the TX_EN bit is ignored until RX_EN is reset. Zero length packets are indicated by setting this bit without writing any data to the FIFO. 0 - Transmission from the FIFO disabled. 1 - Transmission from the FIFO enabled. The Toggle bit specifies the PID used when transmitting the packet. A value of 0 causes a DATA0 PID to be generated, while a value of 1 causes a DATA1 PID to be generated. This bit is not altered by the hardware. 0 - DATA0 PID is used. 1 - DATA1 PID is used.
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Writing a 1 to the Flush FIFO bit flushes all TOGGLE The Toggle bit reports the PID used when redata from the control endpoint FIFOs, resets ceiving the packet. When clear, this bit indithe endpoint to Idle state, clears the FIFO cates that the last successfully received read and write pointer, and then clears itself. packet had a DATA0 PID. When set, this bit inIf the endpoint is currently using the FIFO0 to dicates that the packet had a DATA1 PID. This transfer data on USB, flushing is delayed until bit is unchanged for zero-length packets. It is after the transfer is complete. The FLUSH bit cleared when this register is read. is cleared on reset. It is equivalent to the 0 - DATA0 PID was used. FLUSH bit in the RXC0 register. 1 - DATA1 PID was used. 0 - Writing 0 has no effect. SETUP The Setup bit indicates that the setup packet 1 - Writing 1 flushed the FIFOs. has been received. This bit is unchanged for IGN_IN When the Ignore IN Tokens bit is set, the endzero-length packets. It is cleared when this point will ignore any IN tokens directed to its register is read. configured address. 0 - Setup packet has not been received. 0 - Do not ignore IN tokens. 1 - Setup packet has been received. 1 - Ignore IN tokens. 15.3.29 Receive Command 0 Register (RXC0) 15.3.27 Transmit Data 0 Register (TXD0) The RXC0 register controls the mandatory Endpoint 0 when Data written to the TXD0 register is copied into the FIFO of used in receive direction. This register provides read/write Endpoint 0 at the current location of the transmit write point- access from the CPU bus. It is clear after reset. er. The register allows write-only access from the CPU bus. 7 7 TXFD The Receive Enable bit enables receiving packets. OUT packet reception is disabled after every data packet is received, or when a STALL handshake is returned in response to an OUT token. The RX_EN bit must be set to re-enable data reception. Reception of SET15.3.28 Receive Status 0 Register (RXS0) UP packets is always enabled. In the case of The RXS0 register indicates status conditions for the bidiback-to-back SETUP packets (for a given rectional Control Endpoint 0. To receive a SETUP packet afendpoint) where a valid SETUP packet is reter receiving a zero length OUT/SETUP packet, there are ceived with no other intervening non-SETUP two copies of this register in hardware. One holds the retokens, the Endpoint Controller discards the ceive status of a zero length packet, and another holds the new SETUP packet and returns an ACK handstatus of the next SETUP packet with data. If a zero length shake. If any other reasons prevent the Endpacket is followed by a SETUP packet, the first read of this point Controller from accepting the SETUP register indicates the status of the zero length packet (with packet, it must not generate a handshake. RX_LAST set and RCOUNT clear), and the second read inThis allows recovery from a condition where dicates the status of the SETUP packet. This register prothe ACK of the first SETUP token was lost by vides read-only access from the CPU bus. After reset it is the host. clear. 0 - Receive disabled. 1 - Receive enabled. IGN_OUT The Ignore OUT Tokens bit controls whether 7 6 5 4 3 0 OUT tokens are ignored. When this bit is set, Res. SETUP TOGGLE RX_LAST RCOUNT the endpoint ignores any OUT tokens directed to its configured address. 0 - Do not ignore OUT tokens. RCOUNT The Receive Count field reports the number of 1 - Ignore OUT tokens. bytes presently in the RX FIFO. This number IGN_SETUP The Ignore SETUP Tokens bit controls whethis never larger than 8 for Endpoint 0. er SETUP tokens are ignored. When this bit is RX_LAST The Receive Last Bytes bit indicates that an set, the endpoint ignores any SETUP tokens ACK was sent on completion of a successful directed to its configured address. receive operation. This bit is unchanged for 0 - Do not ignore SETUP tokens. zero-length packets. It is cleared when this 1 - Ignore SETUP tokens. register is read. 0 - No ACK was sent. 1 - An ACK was sent. TXFD The Transmit FIFO Data Byte is used to load the transmit FIFO. Software is expected to write only the packet payload data. The PID and CRC16 are created automatically. RX_EN 0 4 3 2 1 0
FLUSH
Reserved
FLUSH IGN_SETUP IGN_OUT RX_EN
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FLUSH
Writing 1 to the Flush bit flushes all data from ISO the control endpoint FIFOs, resets the endpoint to Idle state, clears the FIFO read and write pointer, and then clears itself. If the endpoint is currently using FIFO0 to transfer data on USB, flushing is delayed until after the transfer is done. This bit is cleared on reset. This bit is equivalent to FLUSH in the TXC0 register. 0 - Writing 0 has no effect. 1 - Writing 1 flushes the FIFOs. STALL
15.3.30 Receive Data 0 Register (RXD0) Reading the RXD0 register returns the data located at the current position of the receive read pointer of the Endpoint 0 FIFO. The register allows read-only access from the CPU bus. After reset, reading this register returns undefined data. 7 RXFD7:0 0
When the Isochronous bit is set, the endpoint is isochronous. This implies that no NAK is sent if the endpoint is not ready but enabled; i.e. if an IN token is received and no data is available in the FIFO to transmit, or if an OUT token is received and the FIFO is full since there is no USB handshake for isochronous transfers. 0 - Isochronous mode disabled. 1 - Isochronous mode enabled. The Stall bit can be used to enable STALL handshakes under the following conditions: The transmit FIFO is enabled and an IN token is received. The receive FIFO is enabled and an OUT token is received. A SETUP token does not cause a STALL handshake to be generated when this bit is set. 0 - Disable STALL handshakes. 1 - Enable STALL handshakes.
15.3.32 Transmit Status Register n (TXSn) Each of the three transmit endpoints has a TXSn register. The Receive FIFO Data Byte is used to un- The format of the TXSn registers is given below. The regisload the FIFO. Software should expect to read ters provide read-only access from the CPU bus. They are only the packet payload data. The PID and loaded with 1Fh at reset. CRC16 are removed from the incoming data stream automatically. 7 6 5 4 0 15.3.31 Endpoint Control Register n (EPCn) TX_URUN ACK_STAT TX_DONE TCOUNT Each unidirectional endpoint has an EPCn register. The format of the EPCn registers is defined below. These registers provide read/write access from the CPU bus. After reset, the TCOUNT The Transmission Count field reports the EPCn registers are clear. number of empty bytes available in the FIFO. If this number is greater than 31, a value of 31 is reported. 7 6 5 4 3 0 TX_DONE When set, the Transmission Done bit indiSTALL Res. ISO EP_EN EP cates that the endpoint responded to a USB packet. Three conditions can cause this bit to be set: EP The Endpoint Address field holds the endA data packet completed transmission in point address. response to an IN token with non-ISO opEP_EN When the Endpoint Enable bit is set, the eration. EP[3:0] field is used in address comparison, The endpoint sent a STALL handshake in together with the AD[6:0] field in the FAR regresponse to an IN token. ister. When clear, the endpoint does not reA scheduled ISO frame was transmitted or spond to any token on the USB bus. (The discarded. AD_EN bit in the FAR register is the global adThis bit is cleared when this register is read. dress compare enable for the USB node. If it is clear, the device does not respond to any address, without regard to the EP_EN state.) 0 - Address comparison is disabled. 1 - If the AD_EN bit is also set, address comparison is enabled. RXFD
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ACK_STAT
TX_URUN
The Acknowledge Status bit is valid when the LAST TX_DONE bit is set. The meaning of the ACK_STAT bit differs depending on whether ISO or non-ISO operation is used (as selected by the ISO bit in the EPCn register). Non-Isochronous mode--This bit indicates the acknowledge status (from the host) about the ACK for the previously sent packet. This bit itself is set when an ACK is received; otherwise, it is clear. Isochronous mode--This bit is set if a frame number LSB match occurs (see Section 15.3.33), and data was sent in response to an IN token. Otherwise, this bit is cleared, the FIFO is flushed, and TX_DONE is set. The ACK_STAT bit is cleared when this regis- TOGGLE ter is read. The Transmit FIFO Underrun indicates whether the transmit FIFO became empty during a transmission, and no new data was written to the FIFO. If so, the Media Access Controller (MAC) forces a bit stuff error followed by an EOP. This bit is cleared when this register is read. 0 - No transmit FIFO underrun event occurred. 1 - Transmit FIFO underrun event occurred.
15.3.33 Transmit Command Register n (TXCn) Each of the transmit endpoints (1, 3, and 5) has a Transmit Command Register, TXCn. These registers provide read/ write access from the CPU bus. After reset the registers are clear. 7 65 4 3 2 1 0 FLUSH
IGN_ISOMSK TFWL RFF FLUSH TOGGLE LAST TX_EN
TX_EN
The Transmission Enable bit enables data transmission from the FIFO. It is cleared by hardware after transmitting a single packet or after a STALL handshake in response to an IN token. It must be set by software to start packet transmission. 0 - Transmission disabled. 1 - Transmission enabled. RFF
The Last Byte bit indicates whether the entire packet has been written into the FIFO. This is used especially for streaming data to the FIFO while the actual transmission occurs. If the LAST bit is not set and the transmit FIFO becomes empty during a transmission, a stuff error followed by an EOP is forced on the bus. Zero length packets are indicated by setting this bit without writing any data to the FIFO. The transmit state machine transmits the payload data, CRC16, and the EOP signal before clearing this bit. 0 - Last byte of the packet has not been written to the FIFO. 1 - Last byte of the packet has been written to the FIFO. The function of the Toggle bit differs depending on whether ISO or non-ISO operation is used (as selected by the ISO bit in the EPCn register). Non-Isochronous mode--The TOGGLE bit specifies the PID used when transmitting the packet. A value of 0 causes a DATA0 PID to be generated, while a value of 1 causes a DATA1 PID to be generated. Isochronous mode--The TOGGLE bit and the LSB of the frame counter (FNL0) act as a mask for the TX_EN bit to allow pre-queueing of packets to specific frame numbers. (I.e. transmission is enabled only if bit 0 in the FNL register is set to TOGGLE.) If an IN token is not received while this condition is true, the contents of the FIFO are flushed with the next SOF. If the endpoint is set to ISO, data is always transferred with a DATA0 PID. This bit is not altered by hardware. Writing 1 to the Flush bit flushes all data from the corresponding transmit FIFO, resets the endpoint to Idle state, and clears both the FIFO read and write pointers. If the MAC is currently using the FIFO to transmit, data is flushed after the transmission is complete. After data flushing, this bit is cleared by hardware. 0 - Writing 0 has no effect. 1 - Writing 1 flushes the FIFO. The Refill FIFO bit is used to repeat a transmission for which no ACK was received. Setting the LAST bit to 1 automatically saves the Transmit Read Pointer (TXRP) to a buffer. When the RFF bit is set, the buffered TXRP is reloaded into the TXRP. This allows software to repeat the last transaction if no ACK was received from the host. If the MAC is currently using the FIFO to transmit, TXRP is reloaded only after the transmission is complete. After reload, this bit is cleared by hardware. 0 - No action. 1 - Reload the saved TXRP.
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TFWL
The Transmit FIFO Warning Limit bits specify how many more bytes can be transmitted from the respective FIFO before an underrun condition occurs. If the number of bytes remaining in the FIFO is equal to or less than the selected warning limit, the TXWARN bit in the FWEV register is set. To avoid interrupts caused by setting this bit while the FIFO is being filled before a transmission begins, TXWARN is only set when transmission from the endpoint is enabled (TX_ENn in the TXCn register is set). See Table 37. Table 37 Transmit FIFO Warning Limit TFWL 00 01 10 11 Bytes Remaining in FIFO TFWL disabled 4 8 16
15.3.35 Receive Status Register n (RXSn) Each receive endpoint pipe (2, 4, and 6) has one RXSn register with the bits defined below. To allow a SETUP packet to be received after a zero length OUT packet is received, hardware contains two copies of this register. One holds the receive status of a zero length packet, and another holds the status of the next SETUP packet with data. If a zero length packet is followed by a SETUP packet, the first read of this register indicates the zero-length packet status, and the second read, the SETUP packet status. This register provides read-only access from the CPU bus. After reset it is clear. 7 6 5 4 3 RCOUNT 0
RX_ERR SETUP TOGGLE RX_LAST
RCOUNT
RX_LAST IGN_ISOMSK The Ignore ISO Mask bit has an effect only if the endpoint is set to be isochronous. If set, this bit disables locking of specific frame numbers with the alternate function of the TOGGLE bit. Therefore, data is transmitted upon TOGGLE reception of the next IN token. If clear, data is only transmitted when FNL0 matches TOGGLE. This bit is cleared after reset. 0 - Data transmitted only when FNL0 matches TOGGLE. 1 - Locking of frame numbers disabled. 15.3.34 Transmit Data Register n (TXDn) Each transmit FIFO has one TXDn register. Data written to the TXDn register is loaded into the transmit FIFO n at the current location of the transmit write pointer. The TXDn registers provide write-only access from the CPU bus. 7 TXFD 0
SETUP
TXFD
The Transmit FIFO Data Byte is used to load the transmit FIFO. Software is expected to RX_ERR write only the packet payload data. The PID and CRC16 are inserted automatically in the transmit data stream.
The Receive Counter holds the number of bytes presently in the endpoint receive FIFO. If this number is greater than 15, a value of 15 is actually reported. The Receive Last Bytes bit indicates that an ACK was sent on completion of a successful receive operation. This bit is cleared when this register is read. 0 - No ACK was sent. 1 - An ACK was sent. The function of the Toggle bit differs depending on whether ISO or non-ISO operation is used (as controlled by the ISO bit in the EPCn register). Non-Isochronous mode--A value of 0 indicates that the last successfully received packet had a DATA0 PID, while a value of 1 indicates that this packet had a DATA1 PID. Non-Isochronous mode--This bit reflects the LSB of the frame number (FNL0) after a packet was successfully received for this endpoint. This bit is cleared by reading the RXSn register. The Setup bit indicates that the setup packet has been received. This bit is cleared when this register is read. 0 - Setup packet has not been received. 1 - Setup packet has been received. The Receive Error indicates a media error, such as bit-stuffing or CRC. If this bit is set, software must flush the respective FIFO. 0 - No receive error occurred. 1 - Receive error occurred.
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15.3.36 Receive Command Register n (RXCn) Each of the receive endpoints (2, 4, and 6) has one RXCn register. The registers provide read/write access from the CPU bus. Reading reserved bits returns undefined data. After reset, it is clear. 7 6 5 4 3 2 1 0
15.3.37 Receive Data Register n (RXD) Each of the three Receive Endpoint FIFOs has one RXD register. Reading the Receive Data register n returns the data located in the receive FIFO n at the current position of the receive read pointer. These registers provide read-only access from the CPU bus. 7 RXFD 0
Res. RFWL Res. FLUSH IGN_SETUP Res. RX_EN
RX_EN
The Receive Enable bit enables receiving packets. OUT packet reception is disabled after every data packet is received, or when a STALL handshake is returned in response to an OUT token. The RX_EN bit must be set to re-enable data reception. Reception of SETUP packets is always enabled. In the case of back-to-back SETUP packets (for a given endpoint) where a valid SETUP packet is received with no other intervening non-SETUP tokens, the Endpoint Controller discards the new SETUP packet and returns an ACK handshake. If any other reasons prevent the Endpoint Controller from accepting the SETUP packet, it must not generate a handshake. 0 - Receive disabled. 1 - Receive enabled. IGN_SETUP The Ignore SETUP Tokens bit controls whether SETUP tokens are ignored. When this bit is set, the endpoint ignores any SETUP tokens directed to its configured address. 0 - Do not ignore SETUP tokens. 1 - Ignore SETUP tokens. FLUSH Writing 1 to the Flush bit flushes all data from the corresponding receive FIFO, resets the endpoint to Idle state, and clears the FIFO read and write pointers. If the endpoint is currently using FIFO to receive data, flushing is delayed until after the transfer is complete. 0 - Writing 0 has no effect. 1 - Writing 1 flushes the FIFOs. RFWL The Receive FIFO Warning Limit field specifies how many more bytes can be received to the respective FIFO before an overrun condition occurs. If the number of empty bytes remaining in the FIFO is equal to or less than the selected warning limit, the RXWARN bit in the FWEV register is set. Table 38 Receive FIFO Warning Limit RFWL 00 01 10 11 Bytes Remaining in FIFO RFWL disabled 4 8 16
RXFD
The Receive FIFO Data Byte is used to read the receive FIFO. Software should expect to read only the packet payload data. The PID and CRC16 are terminated by the receive state machine.
15.4
TRANSCEIVER INTERFACE
Separate UVCC and UGND pins are provided for the USB transceiver, so it can be powered at the standard USB voltage of 3.3V while the other parts of the device run at other voltages. The USB transceiver is powered by the system, not the USB cable, so these pins must be connected to a power supply and the system ground. The on-chip USB transceiver does not have enough impedance to meet the USB specification requirement, so external 22-ohm resistors are required in series with the D+ and D- pins, as shown in Figure 13.
+3.3V UVCC D+ CP3UB17 DUGND 22
22 USB Cable
DS150
Figure 13. USB Transceiver Interface
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16.0 Advanced Audio Interface
The Advanced Audio Interface (AAI) provides a serial synchronous, full duplex interface to codecs and similar serial devices. The transmit and receive paths may operate asynchronously with respect to each other. Each path uses a 3wire interface consisting of a bit clock, a frame synchronization signal, and a data signal. The CPU interface can be either interrupt-driven or DMA. If the interface is configured for interrupt-driven I/O, data is buffered in the receive and transmit FIFOs. If the interface is configured for DMA, the data is buffered in registers. The AAI is functionally similar to a MotorolaTM Synchronous Serial Interface (SSI). Compared to a standard SSI implementation, the AAI interface does not support the so-called "On-demand Mode". It also does not allow gating of the shift clocks, so the receive and transmit shift clocks are always active while the AAI is enabled. The AAI also does not support 12- and 24-bit data word length or more than 4 slots (words) per frame. The reduction of supported modes is acceptable, because the main purpose of the AAI is to connect to audio codecs, rather than to other processors (DSPs). this signal is used as frame sync by both the transmitter and receiver. The frame sync signal may be generated internally, or it may be provided by an external source. 16.1.4 Serial Receive Data (SRD)
The SRD pin is used as an input when data is shifted into the Audio Receive Shift Register (ARSR). In asynchronous mode, data on the SRD pin is sampled on the negative edge of the serial receive shift clock (SRCLK). In synchronous mode, data on the SRD pin is sampled on the negative edge of the serial shift clock (SCK). The data is shifted into ARSR with the most significant bit (MSB) first. 16.1.5 Serial Receive Clock (SRCLK)
The SRCLK pin is a bidirectional signal that provides the receive serial shift clock in asynchronous mode. In this mode, data is sampled on the negative edge of SRCLK. The SRCLK signal may be generated internally or it may be provided by an external clock source. In synchronous mode, the SCK pin is used as shift clock for both the receiver and transmitter, so the SRCLK pin is available for use as a genThe implementation of a FIFO as a 16-word receive and eral-purpose port pin or an auxiliary frame sync signal to actransmit buffer is an additional feature, which simplifies cess multiple slave devices (e.g. codecs) within a network communication and reduces interrupt load. Independent (see Network mode). DMA is provided for each of the four supported audio chan- 16.1.6 Serial Receive Frame Sync (SRFS) nels (slots). The AAI also provides special features and operating modes to simplify gain control in an external codec The SRFS pin is a bidirectional signal that provides frame and to connect to an ISDN controller through an IOM-2 synchronization for the receiver in asynchronous mode. The frame sync signal may be generated internally, or it may be compatible interface. provided by an external source. In synchronous mode, the 16.1 AUDIO INTERFACE SIGNALS SFS signal is used as the frame sync signal for both the transmitter and receiver, so the SRFS pin is available for use 16.1.1 Serial Transmit Data (STD) as a general-purpose port pin or an auxiliary frame sync sigThe STD pin is used to transmit data from the serial transmit nal to access multiple slave devices (e.g. codecs) within a shift register (ATSR). The STD pin is an output when data is network (see Network mode). being transmitted and is in high-impedance mode when no AUDIO INTERFACE MODES data is being transmitted. The data on the STD pin changes 16.2 on the positive edge of the transmit shift clock (SCK). The There are two clocking modes: asynchronous mode and STD pin goes into high-impedance mode on the negative synchronous mode. These modes differ in the source and edge of SCK of the last bit of the data word to be transmit- timing of the clock signals used to transfer data. When the ted, assuming no other data word follows immediately. If an- AAI is generating the bit shift clock and frame sync signals other data word follows immediately, the STD pin will not internally, synchronous mode must be used. change to the high-impedance mode, instead remaining acThere are two framing modes: normal mode and network tive. The data is shifted out with the most significant bit mode. In normal mode, one word is transferred per frame. (MSB) first. In network mode, up to four words are transferred per frame. A word may be 8 or 16 bits. The part of the frame which car16.1.2 Serial Transmit Clock (SCK) ries a word is called a slot. Network mode supports multiple The SCK pin is a bidirectional signal that provides the serial external devices sharing the interface, in which each device shift clock. In asynchronous mode, this clock is used only by is assigned its own slot. Separate frame sync signals are the transmitter to shift out data on the positive edge. The seprovided, so that each device is triggered to send or receive rial shift clock may be generated internally or it may be proits data during its assigned slot. vided by an external clock source. In synchronous mode, the SCK pin is used by both the transmitter and the receiver. 16.2.1 Asynchronous Mode Data is shifted out from the STD pin on the positive edge, In asynchronous mode, the receive and transmit paths of and data is sampled on the SRD pin on the negative edge the audio interface operate independently, with each path of SCK. using its own bit clock and frame sync signal. Independent clocks for receive and transmit are only used when the bit 16.1.3 Serial Transmit Frame Sync (SFS) clock and frame sync signal are supplied externally. If the bit The SFS pin is a bidirectional signal which provides frame clock and frame sync signals are generated internally, both synchronization. In asynchronous mode, this signal is used as frame sync only by the transmitter. In synchronous mode, www.national.com 86
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paths derive their clocks from the same set of clock prescalers. 16.2.2 Synchronous Mode
In synchronous mode, the receive and transmit paths of the audio interface use the same shift clock and frame sync signal. The bit shift clock and frame sync signal for both paths are derived from the same set of clock prescalers. 16.2.3 Normal Mode
If the transmitter interface is configured for interrupt-driven I/O (TXDSA0 = 0), all data to be transmitted is read from the transmit FIFO. An IRQ is asserted as soon as the number data bytes or words available in the transmit FIFO is equal or less than a programmable warning limit. DMA Support If the receiver interface is configured for DMA (RXDSA0 = 1), received data is transferred from the ARSR into the DMA receive buffer 0 (ARDR0). A DMA request is asserted when the ARDR0 register is full. If the transmitter interface is configured for DMA (TXDSA0 = 1), data to be transmitted are read from the DMA transmit buffer 0 (ATDR0). A DMA request is asserted to the DMA controller when the ATDR0 register is empty.
In normal mode, each rising edge on the frame sync signal marks the beginning of a new frame and also the beginning of a new slot. A slot does not necessarily occupy the entire frame. (A frame can be longer than the data word transmitted after the frame sync pulse.) Typically, a codec starts transmitting a fixed length data word (e.g. 8-bit log PCM daFigure 15 shows the data flow for IRQ and DMA mode in ta) with the frame sync signal, then the codec's transmit pin normal Mode. returns to the high-impedance state for the remainder of the frame. The Audio Receive Shift Register (ARSR) de-serializes received on the SRD pin (serial receiver data). Only the data sampled after the frame sync signal are treated as valid. If the interface is interrupt-driven, valid data bits are transferred from the ARSR to the receive FIFO. If the interface is configured for DMA, the data is transferred to the receive DMA register 0 (ARDR0). The serial transmit data (STD) pin is only an active output while data is shifted out. After the defined number of data bits have been shifted out, the STD pin returns to the highimpedance state. For operation in normal mode, the Slot Count Select bits (SCS[1:0]) in the Global Configuration register (AGCR) must be loaded with 00b (one slot per frame). In addition, the Slot Assignment bits for receive and transmit must be programmed to select slot 0. If the interface is configured for DMA, the DMA slot assignment bits must also be programmed to select slot 0. In this case, the audio data is transferred to or from the receive or transmit DMA register 0 (ARDR0/ATDR0). Figure 14 shows the frame timing while operating in normal mode with a long frame sync interval.
Long Frame Sync (SFS/SRFS) SRD ARSR
A DS TX =1
DMA Request 1
ARDR 0
DMA Slot Assignment
TXDSA = 0
RX FIFO
IRQ
STD ATSR
R S XD A =1
DMA Request 0 ATDR 0
DMA Slot Assignment
RXDSA = 0
TX FIFO
IRQ DS054
Figure 15. IRQ/DMA Support in Normal Mode Network Mode In network mode, each frame is composed of multiple slots. Each slot may transfer 8 or 16 bits. All of the slots in a frame must have the same length. In network mode, the sync signal marks the beginning of a new frame. Only frames with up to four slots are supported by this audio interface. More than two devices can communicate within a network using the same clock and data lines. The devices connected to the same bus use a time-multiplexed approach to share access to the bus. Each device has certain slots assigned to it, in which only that device is allowed to transfer data. One master device provides the bit clock and the frame sync signal(s). On all other (slave) devices, the bit clock and frame sync pins are inputs. Up to four slots can be assigned to the interface, as it supports up to four slots per frame. Any other slots within the frame are reserved for other devices.
Shift Data (STD/SRD)
Data
High-impedance Frame
Data
DS053
Figure 14. IRQ Support
Normal Mode Frame
The transmitter only drives data on the STD pin during slots which have been assigned to this interface. During all other If the receiver interface is configured for interrupt-driven I/O slots, the STD output is in high-impedance mode, and data (RXDSA0 = 0), all received data are loaded into the receive can be driven by other devices. The assignment of slots to FIFO. An IRQ is asserted as soon as the number of data the transmitter is specified by the Transmit Slot Assignment bytes or words in the receive FIFO is greater than a pro- bits (TXSA) in the ATCR register. It can also be specified grammable warning limit. whether the data to be transmitted is transferred from the
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transmit FIFO or the corresponding DMA transmit register. There is one DMA transmit register (ATDRn) for each of the maximum four data slots. Each slot can be configured independently. On the receiver side, only the valid data bits which were received during the slots assigned to this interface are copied into the receive FIFO or DMA registers. The assignment of slots to the receiver is specified by the Receive Slot Assignment bits (RXSA) in the ATCR register. It can also be specified whether the received data is copied into the receive FIFO or into the corresponding DMA receive register. There is one DMA receive register (ARDRn) for each of the maximum four data slots. Each slot may be configured individually. Figure 16 shows the frame timing while operating in network mode with four slots per frame, slot 1 assigned to the interface, and a long frame sync interval.
STD Long Frame Sync (SFS/SRFS)
da
ARDR 0 SRD
0 da
DMA Request 1 DMA Request 3
ARSR
Sl ot
ta
ARDR 1
ata
DMA Slot Assignment
Sl
ot
1d
ARDR 2
Sl
ot
ARDR 3
2
an
d
3
da
ta
RX FIFO
IRQ
ATDR 0 ATSR
Sl ot ta
DMA Request 0 DMA Request 2
0
ATDR 1
1d ata
Shift Data (STD/SRD)
Data (ignored)
Data (valid)
High-impedance
Data (ignored)
DMA Slot Assignment
ot Sl
ATDR 2
Sl
Slot0 Slot1 Unused Slots
ATDR 3
ot
2
an
d
3
da
Frame DS055
ta
TX FIFO
IRQ DS056
Figure 16. IRQ Support
Network Mode Frame
Figure 17. IRQ/DMA Support in Network Mode
If the interface operates in synchronous mode, the receiver uses the transmit bit clock (SCK) and transmit frame sync signal (SFS). This allows the pins used for the receive bit clock (SRCLK) and receive frame sync (SRFS) to be used as additional frame sync signals in network mode. The extra frame sync signals are useful when the audio interface comIf DMA is not enabled for a transmit slot n (TXDSAn = 0), all municates to more than one codec, because codecs typicaldata to be transmitted in this slot are read from the transmit ly start transmission immediately after the frame sync pulse. FIFO. An IRQ is asserted as soon as the number data bytes The SRCLK pin is driven with a frame sync pulse at the beor words available in the transmit FIFO is equal or less than ginning of the second slot (slot 1), and the SRFS pin is driva configured warning limit. en with a frame sync pulse at the beginning of slot 2. Figure 18 shows a frame timing diagram for this configuraDMA Support tion, using the additional frame sync signals on SRCLK and If DMA support is enabled for a receive slot n (RXDSA0 = SRFS to address up to three devices. 1), all data received in this slot is only transferred from the ARSR into the corresponding DMA receive register (ARDRn). A DMA request is asserted when the ARDRn register is full. If DMA is not enabled for a receive slot n (RXDSAn = 0), all data received in this slot is loaded into the receive FIFO. An IRQ is asserted as soon as the number of data bytes or words in the receive FIFO is greater than a configured warning limit. If DMA is enabled for a transmit slot n (TXDSAn = 1), all data to be transmitted in slot n are read from the corresponding DMA transmit register (ATDRn). A DMA request is asserted to the DMA controller when the ATDRn register is empty. Figure 17 illustrates the data flow for IRQ and DMA support in network mode, using four slots per frame and DMA support enabled for slots 0 and 1 in receive and transmit direction.
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The ideal required prescaler value Pideal can be calculated as follows:
SFS
Pideal = fAudio In / fbit = 12 MHz / 256 kHz = 46.875 Therefore, the real prescaler value is 47. This results in a bit clock error equal to: fbit_error = (fbit - fAudio In/Preal) / fbit x 100 = (256 kHz - 12 MHz/47) / 256 kHz x 100 = 0.27%
SRCLK (auxiliary frame sync) SRFS (auxiliary frame sync) Data from/to Data from/to Data from/to Codec 1 Codec 2 Codec 3 Slot0 Slot1 Slot2 Slot2
16.4
FRAME CLOCK GENERATION
STD/SRD
Frame DS057
Figure 18.
Accessing Three Devices in Network Mode
The clock for the frame synchronization signals is derived from the bit clock of the audio interface. A 7-bit prescaler is used to divide the bit clock to generate the frame sync clock for the receive and transmit operations. The bit clock is divided by FCPRS + 1. In other words, the value software must write into the ACCR.FCPRS field is equal to the bit number per frame minus one. Be aware, however, that a frame may be longer than the valid data word. In addition, software can specify the length of a long frame sync signal. A long frame sync signal can be either 6, 13, 14, 15, or 16 bits long, depending on the external codec being used. The frame sync length can be configured by the Frame Sync Length field (FSL) in the AGCR register.
16.3
BIT CLOCK GENERATION
An 8-bit prescaler is provided to divide the audio interface input clock down to the required bit clock rate. Software can choose between two input clock sources, a primary and a secondary clock source. On the CP3UB17, the two optional input clock sources are the 12-MHz Aux1 clock and the 48-MHz PLL output clock (also used by the USB node). The input clock is divided by the value of the prescaler BCPRS[7:0] + 1 to generate the bit clock.
16.5
16.5.1
AUDIO INTERFACE OPERATION
Clock Configuration
The Aux1 clock (generated by the Clock module described in Section 11.9) must be configured, because it is the time base for the AAI module. Software must write an appropriThe bit clock rate fbit can be calculated by the following ate divisor to the ACDIV1 field of the PRSAC register to provide a 12 MHz input clock. Software also must enable the equation: Aux1 clock by setting the ACE1 bit in the CRCTRL register. fbit = n x fSample x Data Length For example: n = Number of Slots per Frame PRSAC &= 0xF0; fSample = Sample Frequency in Hz Data Length = Length of data word in multiples of 8 bits The ideal required prescaler value Pideal can be calculated as follows: Pideal = fAudio In / fbit // Set Aux1 prescaler to 1 (F = 12 MHz) CRCTRL |= ACE1; // Enable Aux1 clk 16.5.2 Interrupts
The real prescaler must be set to an integer value, which should be as close as possible to the ideal prescaler value, The four interrupt sources are: to minimize the bit clock error, fbit_error. RX FIFO Overrun - ASCR.RXEIP = 1 fbit_error [%] = (fbit - fAudio In/Preal) / fbit x 100 RX FIFO Almost Full (Warning Level) - ASCR.RXIP = 1 Example: TX FIFO Under run - ASCR.TXEIP = 1 TX FIFO Almost Empty (Warning Level) - ASCR.TXIP=1 The audio interface is used to transfer 13-bit linear PCM data for one audio channel at a sample rate of 8k samples In addition to the dedicated input to the ICU for handling per second. The input clock of the audio interface is 12 MHz. these interrupt sources, the Serial Frame Sync (SFS) signal Furthermore, the codec requires a minimum bit clock of 256 is an input to the MIWU (see Section 13.0), which can be kHz to operate properly. Therefore, the number of slots per programmed to generate edge-triggered interrupts. frame must be set to 2 (network mode) although actually only one slot (slot 0) is used. The codec and the audio interface will tristate their data transmit pins after the PCM data word has been transferred. The required bit clock rate fbit can be calculated by the following equation: fbit = n x fSample x Data Length = 2 x 8 kHz x 16 = 256 kHz
The interrupt logic of the AAI combines up to four interrupt sources and generates one interrupt request signal to the Interrupt Control Unit (ICU).
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Figure 19 shows the interrupt structure of the AAI.
RXIE
RXIP = 1
RXEIE
from the FIFO to ATSR is performed (while the FIFO is already empty), a transmit FIFO underrun occurs. In this event, the read pointer (TRP) will be decremented by 1 (incremented by 15) and the previous data word will be transmitted again. A transmit FIFO underrun is indicated by the TXU bit in the Audio Interface Transmit Status and Control Register (ATSCR). Also, no transmit interrupt will be generated (even if enabled). When the TRP is equal to the TWP and the last access to the FIFO was a write operation (to the ATFR), the FIFO is full. If an additional write to ATFR is performed, a transmit FIFO overrun occurs. This error condition is not prevented by hardware. Software must ensure that no transmit overrun occurs. The transmit frame synchronization pulse on the SFS pin and the transmit shift clock on the SCK pin may be generated internally, or they can be supplied by an external source.
RXEIP = 1
AAI Interrupt TXIE
TXIP = 1
TXEIE
TXEIP = 1 DS155
16.5.5
Receive
Figure 19. AAI Interrupt Structure 16.5.3 Normal Mode
At the receiver, the received data on the SRD pin is shifted into ARSR on the negative edge of SRCLK (or SCK in synchronous mode), following the receive frame sync pulse, SRFS (or SFS in synchronous mode). DMA Operation When a complete data word has been received through the SRD pin, the new data word is copied to the receive DMA register 0 (ARDR0). A DMA request is asserted when the ARDR0 register is full. If a new data word is received while the ARDR0 register is still full, the ARDR0 register will be overwritten with the new data. FIFO Operation When a complete word has been received, it is transferred to the receive FIFO at the current location of the Receive FIFO Write Pointer (RWP). Then, the RWP is automatically incremented by 1.
In normal mode, each frame sync signal marks the beginning of a new frame and also the beginning of a new slot, since each frame only consists of one slot. All 16 receive and transmit FIFO locations hold data for the same (and only) slot of a frame. If 8-bit data are transferred, only the low byte of each 16-bit FIFO location holds valid data. 16.5.4 Transmit
Once the interface has been enabled, transmit transfers are initiated automatically at the beginning of every frame. The beginning of a new frame is identified by a frame sync pulse. Following the frame sync pulse, the data is shifted out from the ATSR to the STD pin on the positive edge of the transmit data shift clock (SCK). DMA Operation
A read from the Audio Receive FIFO Register (ARFR) results in a read from the receive FIFO at the current location When a complete data word has been transmitted through of the Receive FIFO Read Pointer (RRP). After every read the STD pin, a new data word is reloaded from the transmit operation from the receive FIFO, the RRP is automatically DMA register 0 (ATDR0). A DMA request is asserted when incremented by 1. the ATDR0 register is empty. If a new data word must be When the RRP is equal to the RWP and the last access to transmitted while the ATDR0 register is still empty, the prethe FIFO was a copy operation from the ARFR, the receive vious data will be re-transmitted. FIFO is full. When a new complete data word has been shifted into ARSR while the receive FIFO was already full, the FIFO Operation shift register overruns. In this case, the new data in the When a complete data word has been transmitted through ARSR will not be copied into the FIFO and the RWP will not the STD pin, a new data word is loaded from the transmit be incremented. A receive FIFO overrun is indicated by the FIFO from the current location of the Transmit FIFO Read RXO bit in the Audio Interface Receive Status and Control Pointer (TRP). After that, the TRP is automatically increRegister (ARSCR). No receive interrupt will be generated mented by 1. (even if enabled). A write to the Audio Transmit FIFO Register (ATFR) results When the RWP is equal to the TWP and the last access to in a write to the transmit FIFO at the current location of the the receive FIFO was a read from the ARFR, a receive FIFO Transmit FIFO Write Pointer (TWP). After every write operunderrun has occurred. This error condition is not prevented ation to the transmit FIFO, TWP is automatically incrementby hardware. Software must ensure that no receive undered by 1. run occurs. When the TRP is equal to the TWP and the last access to The receive frame synchronization pulse on the SRFS pin the FIFO was a read operation (a transfer to the ATSR), the (or SFS in synchronous mode) and the receive shift clock on transmit FIFO is empty. When an additional read operation the SRCLK (or SCK in synchronous mode) may be generwww.national.com 90
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ated internally, or they can be supplied by an external source. 16.5.6 Network Mode
ferred to the receive FIFO or DMA receive register which were received during the assigned time slots. A receive interrupt or DMA request is initiated when this occurs. DMA Operation When a complete data word has been received through the SRD pin in a slot n, the new data word is transferred to the corresponding receive DMA register n (ARDRn). A DMA request is asserted when the ARDRn register is full. If a new slot n data word is received while the ARDRn register is still full, the ARDRn register will be overwritten with the new data. FIFO Operation When a complete word has been received, it is transferred to the receive FIFO at the current location of the Receive FIFO Write Pointer (RWP). After that, the RWP is automatically incremented by 1. Therefore, data received in the next slot is copied to the next higher FIFO location.
In network mode, each frame sync signal marks the beginning of new frame. Each frame can consist of up to four slots. The audio interface operates in a similar way to normal mode, however, in network mode the transmitter and receiver can be assigned to specific slots within each frame as described below. 16.5.7 Transmit
The transmitter only shifts out data during the assigned slot. During all other slots the STD output is in TRI-STATE mode. DMA Operation
When a complete data word has been transmitted through the STD pin, a new data word is reloaded from the corresponding transmit DMA register n (ATDRn). A DMA request is asserted when ATDRn is empty. If a new data word must A read from the Audio Receive FIFO Register (ARFR) rebe transmitted in a slot n while ATDRn is still empty, the pre- sults in a read from the receive FIFO at the current location vious slot n data will be retransmitted. of the Receive FIFO Read Pointer (RRP). After every read operation from the receive FIFO, the RRP is automatically FIFO Operation incremented by 1. When a complete data word has been transmitted through the STD pin, a new data word is reloaded from the transmit When the RRP is equal to the RWP and the last access to FIFO from the current location of the Transmit FIFO Read the FIFO was a transfer to the ARFR, the receive FIFO is Pointer (TRP). After that, the TRP is automatically incre- full. When a new complete data word has been shifted into mented by 1. Therefore, the audio data to be transmitted in the ARSR while the receive FIFO was already full, the shift the next slot of the frame is read from the next FIFO loca- register overruns. In this case, the new data in the ARSR will not be transferred to the FIFO and the RWP will not be intion. cremented. A receive FIFO overrun is indicated by the RXO A write to the Audio Transmit FIFO Register (ATFR) results bit in the Audio Interface Receive Status and Control Regisin a write to the transmit FIFO at the current location of the ter (ARSCR). No receive interrupt will be generated (even if Transmit FIFO Write Pointer (TWP). After every write operenabled). ation to the transmit FIFO, the TWP is automatically increWhen the current RWP is equal to the TWP and the last acmented by 1. cess to the receive FIFO was a read from ARFR, a receive When the TRP is equal to the TWP and the last access to FIFO underrun has occurred. This error condition is not prethe FIFO was a read operation (transfer to the ATSR), the vented by hardware. Software must ensure that no receive transmit FIFO is empty. When an additional read operation underrun occurs. from the FIFO to the ATSR is performed (while the FIFO is already empty), a transmit FIFO underrun occurs. In this The receive frame synchronization pulse on the SRFS pin case, the read pointer (TRP) will be decremented by 1 (in- (or SFS in synchronous mode) and the receive shift clock on cremented by 15) and the previous data word will be trans- the SRCLK (or SCK in synchronous mode) may be genermitted again. A transmit FIFO underrun is indicated by the ated internally, or they can be supplied by an external TXU bit in the Audio Interface Transmit Status and Control source. Register (ATSCR). No transmit interrupt will be generated 16.6 COMMUNICATION OPTIONS (even if enabled). If the current TRP is equal to the TWP and the last access 16.6.1 Data Word Length to the FIFO was a write operation (to the ATFR), the FIFO is full. If an additional write to the ATFR is performed, a transmit FIFO overrun occurs. This error condition is not prevented by hardware. Software must ensure that no transmit overrun occurs. The word length of the audio data can be selected to be either 8 or 16 bits. In 16-bit mode, all 16 bits of the transmit and receive shift registers (ATSR and ARSR) are used. In 8bit mode, only the lower 8 bits of the transmit and receive shift registers (ATSR and ARSR) are used.
The transmit frame synchronization pulse on the SFS pin 16.6.2 Frame Sync Signal and the transmit shift clock on the SCK pin may be generated internally, or they can be supplied by an external source. The audio interface can be configured to use either long or short frame sync signals to mark the beginning of a new 16.5.8 Receive data frame. If the corresponding Frame Sync Select (FSS) The receive shift register (ARSR) receives data words of all bit in the Audio Control and Status register is clear, the reslots in the frame, regardless of the slot assignment of the ceive and/or transmit path generates or recognizes short interface. However, only those ARSR contents are trans- frame sync pulses with a length of one bit shift clock period. When these short frame sync pulses are used, the transfer
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of the first data bit or the first slot begins at the first positive edge of the shift clock after the negative edge on the frame sync pulse. If the corresponding Frame Sync Select (FSS) bit in the Audio Control and Status register is set, the receive and/or transmit path generates or recognizes long frame sync pulses. For 8-bit data, the frame sync pulse generated will be 6 bit shift clock periods long, and for 16-bit data the frame sync pulse can be configured to be 13, 14, 15, or 16 bit shift clock periods long. When receiving frame sync, it should be active on the first bit of data and stay active for a least two bit clock periods . It must go low for at least one bit clock period before starting a new frame. When long frame sync pulses are used, the transfer of the first word (first slot) begins at the first positive edge of the bit shift clock after the positive edge of the frame sync pulse. Figure 20 shows examples of short and long frame sync pulses.
Some codecs require an inverted frame sync signal. This is available by setting the Inverted Frame Sync bit in the AGCR register. 16.6.3 Audio Control Data
Bit Shift Clock (SCK/SRCLK)
The audio interface provides the option to fill a 16-bit slot with up to three data bits if only 13, 14, or 15 PCM data bits are transmitted. These additional bits are called audio control data and are appended to the PCM data stream. The AAI can be configured to append either 1, 2, or 3 audio control bits to the PCM data stream. The number of audio data bits to be used is specified by the 2-bit Audio Control On (ADMACR. ACO[1:0]) field. If the ACO field is not equal to 0, the specified number of bits are taken from the Audio Control Data field (ADMACR. ACD[2:0]) and appended to the data stream during every transmit operation. The ADC[0] bit is the first bit added to the transmit data stream after the last PCM data bit. Typically, these bits are used for gain control, if this feature is supported by the external PCM codec.Figure 21 shows a 16-bit slot comprising a 13-bit PCM data word plus three audio control bits.
Shift Data (STD/SRD)
D0
D1
D2
D3
D4
D5
D6
D7
Short Frame Sync Pulse
Long Frame Sync Pulse DS156
Figure 20. Short and Long Frame Sync Pulses
SCK
SFS
STD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10 D11
D12 ACD2 ACD1 ACD0 Audio Control Bits
13-bit PCM Data Word
16-bit Slot DS161
Figure 21. Audio Slot with Audio Control Data
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16.6.4
IOM-2 Mode
The IOM-2 interface has the following properties:
The AAI can operate in a special IOM-2 compatible mode to Bit clock of 1536 kHz (output from the ISDN controller) allow to connect to an external ISDN controller device. In Frame repetition rate of 8 ksps (output from the ISDN this IOM-2 mode, the AAI can only operate as a slave, i.e. controller) the bit clock and frame sync signal is provided by the ISDN Double-speed bit clock (one data bit is two bit clocks controller. The AAI only supports the B1 and B2 data of the wide) IOM-2 channel 0, but ignores the other two IOM-2 channels. B1 and B2 data use 8-bit log PCM format The AAI handles the B1 and B2 data as one 16-bit data Long frame sync pulse word. Figure 22 shows the structure of an IOM-2 Frame.
SFS
STD/SRD
B1
B2
M
C
IC1
IC2
M
C
C
IOM-2 Channel 0
IOM-2 Channel 1
IOM-2 Channel 2
IOM-2 Frame (125 s) DS162
Figure 22. IOM-2 Frame Structure Figure 23 shows the connections between an ISDN controller and a CP3UB17 using a standard IOM-2 interface for the B1/B2 data communication and the external bus interface (IO Expansion) for controlling the ISDN controller. To connect the AAI to an ISDN controller through an IOM-2 compatible interface, the AAI needs to be configured in this way: The AAI must be in IOM-2 Mode (AGCR.IOM2 = 1). The AAI operates in synchronous mode (AGCR.ASS = 0). The AAI operates as a slave, therefore the bit clock and frame sync source selection must be set to external (ACGR.IEFS = 1, ACGR.IEBC = 1). The frame sync length must be set to long frame sync (ACGR.FSS = 1). The data word length must be set to 16-bit (AGCR.DWL = 1). The AAI must be set to normal mode (AGCR.SCS[1:0] = 0). The internal frame rate must be 8 ksps (ACCR = 00BE). 16.6.5
SELIO Chip Select
SCK
Bit Clock
SFS CP3UB17 STD
Frame Sync ISDN Controller Data In
SRD
Data Out
A[7:0]
Address
D[7:0]
Data
Loopback Mode
RD
Output Enable
DS160
In loopback mode, the STD and SRD pins are internally connected together, so data shifted out through the ATSR register will be shifted into the ARSR register. This mode may be used for development, but it also allows testing the transmit and receive path without external circuitry, for example during Built-In-Self-Test (BIST).
Figure 23. CP3UB17/ISDN Controller Connections
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16.6.6
Freeze Mode
16.7
AUDIO INTERFACE REGISTERS
Table 39 Audio Interface Registers Name ARFR ARDR0 ARDR1 ARDR2 ARDR3 ATFR ATDR0 ATDR1 ATDR2 ATDR3 AGCR AISCR ARSCR ATSCR ACCR Address FF FD40h FF FD42h FF FD44h FF FD46h FF FD48h FF FD4Ah FF FD4Ch FF FD4Eh FF FD50h FF FD52h FF FD54h FF FD56h FF FD58h FF FD5Ah FF FD5Ch FF FD5Eh Description Audio Receive FIFO Register Audio Receive DMA Register 0 Audio Receive DMA Register 1 Audio Receive DMA Register 2 Audio Receive DMA Register 3 Audio Transmit FIFO Register Audio Transmit DMA Register 0 Audio Transmit DMA Register 1 Audio Transmit DMA Register 2 Audio Transmit DMA Register 3 Audio Global Configuration Register Audio Interrupt Status and Control Register Audio Receive Status and Control Register Audio Transmit Status and Control Register Audio Clock Control Register Audio DMA Control Register
The audio interface provides a FREEZE input, which allows to freeze the status of the audio interface while a development system examines the contents of the FIFOs and registers. When the FREEZE input is asserted, the audio interface behaves as follows: The receive FIFO or receive DMA registers are not updated with new data. The receive status bits (RXO, RXE, RXF, and RXAF) are not changed, even though the receive FIFO or receive DMA registers are read. The transmit shift register (ATSR) is not updated with new data from the transmit FIFO or transmit DMA registers. The transmit status bits (TXU, TXF, TXE, and TXAE) are not changed, even though the transmit FIFO or transmit DMA registers are written. The time at which these registers are frozen will vary because they operate from a different clock than the one used to generate the freeze signal.
ADMACR
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16.7.1
Audio Receive FIFO Register (ARFR)
16.7.3
Audio Transmit FIFO Register (ATFR)
The Audio Receive FIFO register shows the receive FIFO location currently addressed by the Receive FIFO Read Pointer (RRP). The receive FIFO receives 8-bit or 16-bit data from the Audio Receive Shift Register (ARSR), when the ARSR is full. In 8-bit mode, only the lower byte of the ARFR is used, and the upper byte contains undefined data. In 16-bit mode, a 16-bit word is copied from ARSR into the receive FIFO. The CPU bus master has read-only access to the receive FIFO, represented by the ARFR register. After reset, the receive FIFO (ARFR) contains undefined data. 7 ARFL 0
The ATFR register shows the transmit FIFO location currently addressed by the Transmit FIFO Write Pointer (TWP). The Audio Transmit Shift Register (ATSR) receives 8-bit or 16-bit data from the transmit FIFO, when the ATSR is empty. In 8-bit mode, only the lower 8-bit portion of the ATSR is used, and the upper byte is ignored (not transferred into the ATSR). In 16-bit mode, a 16-bit word is copied from the transmit FIFO into the ATSR. The CPU bus master has write-only access to the transmit FIFO, represented by the ATFR register. After reset, the transmit FIFO (ATFR) contains undefined data. 7 ATFL 0
15 ARFH
8
15 ATFH
8
ARFL
ARFH
The Audio Receive FIFO Low Byte shows the lower byte of the receive FIFO location currently addressed by the Receive FIFO Read Pointer (RRP). The Audio Receive FIFO High Byte shows the upper byte of the receive FIFO location currently addressed by the Receive FIFO Read Pointer (RRP). In 8-bit mode, ARFH contains undefined data. Audio Receive DMA Register n (ARDRn)
ATFL
ATFH
The Audio Transmit Low Byte field represents the lower byte of the transmit FIFO location currently addressed by the Transmit FIFO Write Pointer (TWP). In 16-bit mode, the Audio Transmit FIFO High Byte field represents the upper byte of the transmit FIFO location currently addressed by the Transmit FIFO Write Pointer (TWP). In 8bit mode, the ATFH field is not used. Audio Transmit DMA Register n (ATDRn)
16.7.2
16.7.4
The ARDRn register contains the data received within slot n, assigned for DMA support. In 8-bit mode, only the lower 8-bit portion of the ARDRn register is used, and the upper byte contains undefined data. In 16-bit mode, a 16-bit word is transferred from the Audio Receive Shift Register (ARSR) into the ARDRn register. The CPU bus master, typically a DMA controller, has read-only access to the receive DMA registers. After reset, these registers are clear. 7 ARDL 0
The ATDRn register contains the data to be transmitted in slot n, assigned for DMA support. In 8-bit mode, only the lower 8-bit portion of the ATDRn register is used, and the upper byte is ignored (not transferred into the ATSR). In 16bit mode, the whole 16-bit word is transferred into the ATSR. The CPU bus master, typically a DMA controller, has writeonly access to the transmit DMA registers. After reset, these registers are clear. 7 ATDL 0
15 ARDH
8
15 ATDH
8
ARDL
ARDH
The Audio Receive DMA Low Byte field receives the lower byte of the audio data copied from the ARSR. In 16-bit mode, the Audio Receive DMA High Byte field receives the upper byte of the audio data word copied from ARSR. In 8-bit mode, the ARDH register holds undefined data.
ATDL ATDH
The Audio Transmit DMA Low Byte field holds the lower byte of the audio data. In 16-bit mode, the Audio Transmit DMA High Byte field holds the upper byte of the audio data word. In 8-bit mode, the ATDH field is ignored.
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16.7.5
Audio Global Configuration Register (AGCR)
IEFS
The AGCR register controls the basic operation of the interface. The CPU bus master has read/write access to the AGCR register. After reset, this register is clear. 7 IEBC 6 FSS 5 IEFS 4 SCS 3 2 LPB 1 DWL 0 ASS FSS 15 14 13 12 IFS 11 10 9 CTF 8 CRF CLKEN AAIEN IOM2 FSL
ASS
DWL
LPB
SCS
The Asynchronous/Synchronous Mode Select bit controls whether the audio interface operates in Asynchronous or in Synchronous mode. After reset the ASS bit is clear, so the Synchronous mode is selected by default. 0 - Synchronous mode. 1 - Asynchronous mode. The Data Word Length bit controls whether the transferred data word has a length of 8 or 16 bits. After reset, the DWL bit is clear, so 8bit data words are used by default. 0 - 8-bit data word length. 1 - 16-bit data word length. The Loop Back bit enables the loop back mode. In this mode, the SRD and STD pins are internally connected. After reset the LPB bit is clear, so by default the loop back mode is disabled. 0 - Loop back mode disabled. 1 - Loop back mode enabled. The Slot Count Select field specifies the number of slots within each frame. If the number of slots per frame is equal to 1, the audio interface operates in normal mode. If the number of slots per frame is greater than 1, the interface operates in network mode. After reset all SCS bits are cleared, so by default the audio interface operates in normal mode. Number of Slots per Frame 1 2 3 4
IEBC
CRF
CTF
FSL
SCS
Mode
The Internal/External Frame Sync bit controls, whether the frame sync signal for the receiver and transmitter are generated internally or provided from an external source. After reset, the IEFS bit is clear, so the frame synchronization signals are generated internally by default. 0 - Internal frame synchronization signal. 1 - External frame synchronization signal. The Frame Sync Select bit controls whether the interface (receiver and transmitter) uses long or short frame synchronization signals. After reset the FSS bit is clear, so short frame synchronization signals are used by default. 0 - Short (bit length) frame synchronization signal. 1 - Long (word length) frame synchronization signal. The Internal/External Bit Clock bit controls whether the bit clocks for receiver and transmitter are generated internally or provided from an external source. After reset, the IEBC bit is clear, so the bit clocks are generated internally by default. 0 - Internal bit clock. 1 - External bit clock. The Clear Receive FIFO bit is used to clear the receive FIFO. When this bit is written with a 1, all pointers of the receive FIFO are set to their reset state. After updating the pointers, the CRF bit will automatically be cleared again. 0 - Writing 0 has no effect. 1 - Writing 1 clears the receive FIFO. The Clear Transmit FIFO bit is used to clear the transmit FIFO. When this bit is written with a 1, all pointers of the transmit FIFO are set to their reset state. After updating the pointers, the CTF bit will automatically be cleared again. 0 - Writing 0 has no effect. 1 - Writing 1 clears the transmit FIFO. The Frame Sync Length field specifies the length of the frame synchronization signal, if the AAI is configured to use a long frame sync signal (FSS = 1) and a data word length of 16bit (DWL = 1). FSL 00 01 10 11 Frame Sync Length 13-bit clocks 14-bit clocks 15-bit clocks 16-bit clocks
00 01 10 11
Normal mode Network mode Network mode Network mode
IFS
The Inverted Frame Sync bit controls the polarity of the frame sync signal. 0 - Active-high frame sync signal. 1 - Active-low frame sync signal.
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IOM2
AAIEN
CLKEN
The IOM-2 Mode bit selects the normal PCM interface mode or a special IOM-2 mode used to connect to external ISDN controller devices. The AAI can only operate as a slave in the IOM-2 mode, i.e. the bit clock and frame sync signals are provided by the ISDN controller. If the IOM2 bit is clear, the AAI operates in the normal PCM interface mode used to connect to external PCM codecs and other PCM audio devices. 0 - IOM-2 mode disabled. 1 - IOM-2 mode enabled. The AAI Enable bit controls whether the Advanced Audio Interface is enabled. All AAI registers provide read/write access while (CLKEN = 1) AAIEN is clear. The AAIEN bit is clear after reset. 0 - AAI module disabled. 1 - AAI module enabled. The Clock Enable bit controls whether the Advanced Audio Interface clock is enabled. The CLKEN bit must be set to allow access to any AAI register. It must also be set before any other bit of the AGCR can be set. The CLKEN bit is clear after reset. 0 - AAI module clock disabled. 1 - AAI module clock enabled. Audio Interrupt Status and Control Register (AISCR)
TXIE
TXEIE
RXIP
RXEIP
16.7.6
The ASCR register is used to specify the source and the conditions, when the audio interface interrupt is asserted to TXIP the Interrupt Control Unit. It also holds the interrupt pending bits and the corresponding interrupt clear bits for each audio interface interrupt source. The CPU bus master has read/ write access to the ASCR register. After reset, this register is clear. 7 6 5 4 3 2 1 0 TXEIP
TXEIP TXIP RXEIP RXIP TXEIE TXIE RXEIE RXIE
15 Reserved
12
11
10
9
8 RXIC
TXEIC TXIC RXEIC RXIC
RXIE
RXEIE
The Receive Interrupt Enable bit controls whether receive interrupts are generated. If the RXIE bit is clear, no receive interrupt will RXEIC be generated. 0 - Receive interrupt disabled. 1 - Receive interrupt enabled. The Receive Error Interrupt Enable bit con- TXIC trols whether receive error interrupts are generated. Setting this bit enables a receive error interrupt, when the Receive Buffer Overrun (RXOR) bit is set. If the RXEIE bit is clear, no TXEIC receive error interrupt will be generated. 0 - Receive error interrupt disabled. 1 - Receive error interrupt enabled.
The Transmit Interrupt Enable bit controls whether transmit interrupts are generated. Setting this bit enables a transmit interrupt, when the Transmit Buffer Almost Empty (TXAE) bit is set. If the TXIE bit is clear, no interrupt will be generated. 0 - Transmit interrupt disabled. 1 - Transmit interrupt enabled. The Transmit Error Interrupt Enable bit controls whether transmit error interrupts are generated. Setting this bit to 1 enables a transmit error interrupt, when the Transmit Buffer Underrun (TXUR) bit is set. If the TXEIE bit is clear, no transmit error interrupt will be generated. 0 - Transmit error interrupt disabled. 1 - Transmit error interrupt enabled. The Receive Interrupt Pending bit indicates that a receive interrupt is currently pending. The RXIP bit is cleared by writing a 1 to the RXIC bit. The RXIP bit provides read-only access. 0 - No receive interrupt pending. 1 - Receive interrupt pending. The Receive Error Interrupt Pending bit indicates that a receive error interrupt is currently pending. The RXEIP bit is cleared by writing a 1 to the RXEIC bit. The RXEIP bit provides read-only access. 0 - No receive error interrupt pending. 1 - Receive error interrupt pending. The Transmit Interrupt Pending bit indicates that a transmit interrupt is currently pending. The TXIP bit is cleared by writing a 1 to the TXIC bit. The TXIP bit provides read-only access. 0 - No transmit interrupt pending. 1 - Transmit interrupt pending. Transmit Error Interrupt Pending. This bit indicates that a transmit error interrupt is currently pending. The TXEIP bit is cleared by software by writing a 1 to the TXEIC bit. The TXEIP bit provides read-only access. 0 - No transmit error interrupt pending. 1 - Transmit error interrupt pending. The Receive Interrupt Clear bit is used to clear the RXIP bit. 0 - Writing a 0 to the RXIC bit is ignored. 1 - Writing a 1 clears the RXIP bit. The Receive Error Interrupt Clear bit is used to clear the RXEIP bit. 0 - Writing a 0 to the RXEIC bit is ignored. 1 - Writing a 1 clears the RXEIP bit. The Transmit Interrupt Clear bit is used to clear the TXIP bit. 0 - Writing a 0 to the TXIC bit is ignored. 1 - Writing a 1 clears the TXIP bit. The Transmit Error Interrupt Clear bit is used to clear the TXEIP bit. 0 - Writing a 0 to the TXEIC bit is ignored. 1 - Writing a 1 clears the TXEIP bit.
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16.7.7
Audio Receive Status and Control Register (ARSCR)
The following table shows the slot assignment scheme. RXSA Bit RXSA0 RXSA1 RXSA2 RXSA3 Slots Enabled 0 1 2 3
The ARSCR register is used to control the operation of the receiver path of the audio interface. It also holds bits which report the current status of the receive FIFO. The CPU bus master has read/write access to the ASCR register. At reset, this register is loaded with 0004h. 7 RXSA 4 3 RXO 2 RXE 1 0
RXF RXAF
15 RXFWL
12
11 RXDSA
8 RXDSA
RXAF
RXF
RXE
RXO
RXSA
The Receive Buffer Almost Full bit is set when the number of data bytes/words in the receive buffer is equal to the specified warning limit. 0 - Receive FIFO below warning limit. 1 - Receive FIFO is almost full. The Receive Buffer Full bit is set when the receive buffer is full. The RXF bit is set when the RWP is equal to the RRP and the last access was a write to the FIFO. 0 - Receive FIFO is not full. 1 - Receive FIFO full. The Receive Buffer Empty bit is set when the the RRP is equal to the RWP and the last access to the FIFO was a read operation (read from ARDR). 0 - Receive FIFO is not empty. 1 - Receive FIFO is empty. The Receive Overflow bit indicates that a receive shift register has overrun. This occurs, when a completed data word has been shifted RXFWL into ARSR, while the receive FIFO was already full (the RXF bit was set). In this case, the new data in ARSR will not be copied into the FIFO and the RWP will not be incremented. Also, no receive interrupt and DMA request will generated (even if enabled). 0 - No overflow has occurred. 1 - Overflow has occurred. The Receive Slot Assignment field specifies which slots are recognized by the receiver of the audio interface. Multiple slots may be enabled. If the frame consists of less than 4 slots, the RXSA bits for unused slots are ignored. For example, if a frame only consists of 2 slots, RXSA bits 2 and 3 are ignored.
After reset the RXSA field is clear, so software must load the correct slot assignment. The Receive DMA Slot Assignment field specifies which slots (audio channels) are supported by DMA. If the RXDSA bit is set for an assigned slot n (RXSAn = 1), the data received within this slot will not be transferred into the receive FIFO, but will instead be written into the corresponding Receive DMA data register (ARDRn). A DMA request n is asserted, when the ARDRn is full and if the RMA bit n is set. If the RXSD bit for a slot is clear, the RXDSA bit is ignored. The following table shows the DMA slot assignment scheme. RXDSA Bit RXDSA0 RXDSA1 RXDSA2 RXDSA3 Slots Enabled for DMA 0 1 2 3
The Receive FIFO Warning Level field specifies when a receive interrupt is asserted. A receive interrupt is asserted, when the number of bytes/words in the receive FIFO is greater than the warning level value. An RXFWL value of 0 means that a receive interrupt is asserted if one or more bytes/words are in the RX FIFO. After reset, the RXFWL bit is clear.
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16.7.8
Audio Transmit Status and Control Register (ATSCR) TXSA Bit TXSA0 TXSA1 TXSA2 Slots Enabled 0 1 2 3
The ASCR register controls the basic operation of the interface. It also holds bits which report the current status of the audio communication. The CPU bus master has read/write access to the ASCR register. At reset, this register is loaded with F003h. 7 TXSA 4 3 TXU 2 TXF 1 0
TXSA3
TXE TXAE After reset, the TXSA field is clear, so software must load the correct slot assignment. The Transmit DMA Slot Assignment field specifies which slots (audio channels) are supported by DMA. If the TXDSA bit is set for an assigned slot n (TXSAn = 1), the data to be transmitted within this slot will not be read from the transmit FIFO, but will instead be read from the corresponding Transmit DMA data register (ATDRn). A DMA request n is asserted when the ATDRn is empty. If the TSA bit for a slot is clear, the TXDSA bit is ignored. The following table shows the DMA slot assignment scheme. TXDSA Bit TXDSA0 TXDSA1 TXDSA2 TXDSA3 Slots Enabled for DMA 0 1 2 3
15 TXFWL
12
11 TXDSA
8
TXDSA
TXAE
TXE
TXF
TXU
TXSA
The Transmit FIFO Almost Empty bit is set when the number of data bytes/words in transmit buffer is equal to the specified warning limit. 0 - Transmit FIFO above warning limit. 1 - Transmit FIFO at or below warning limit. The Transmit FIFO Empty bit is set when the transmit buffer is empty. The TXE bit is set to one every time the TRP is equal to the TWP and the last access to the FIFO was read operation (into ATSR). 0 - Transmit FIFO not empty. 1 - Transmit FIFO empty. The Transmit FIFO Full bit is set when the TWP is equal to the TRP and the last access to the FIFO was write operation (write to ATDR). 0 - Transmit FIFO not full. 1 - Transmit FIFO full. The Transmit Underflow bit indicates that the TFWL transmit shift register (ATSR) has underrun. This occurs when the transmit FIFO was already empty and a complete data word has been transferred. In this case, the TRP will be decremented by 1 and the previous data will be retransmitted. No transmit interrupt and no DMA request will be generated (even if enabled). 0 - Transmit underrun occurred. 1 - Transmit underrun did not occur. The Transmit Slot Assignment field specifies during which slots the transmitter is active and drives data through the STD pin. The STD pin is in high impedance state during all other slots. If the frame consists of less than 4 slots, the TXSA bits for unused slots are ignored. For example, if a frame only consists of 2 slots, TXSA bits 2 and 3 are ignored. The following table shows the slot assignment scheme.
The Transmit FIFO Warning Level field specifies when a transmit interrupt is asserted. A transmit interrupt is asserted when the number of bytes or words in the transmit FIFO is equal or less than the warning level value. A TXFWL value of Fh means that a transmit interrupt is asserted if one or more bytes or words are available in the transmit FIFO. At reset, the TXFWL field is loaded with Fh.
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16.7.9
Audio Clock Control Register (ACCR)
The ACCR register is used to control the bit timing of the audio interface. After reset, this register is clear. 7 FCPRS 1 0 CSS
ignored. The following table shows the receive DMA request scheme. RMD 0000 0001 0010 DMA Request Condition None ARDR0 full ARDR1 full ARDR0 full or ARDR1 full Not supported on CP3UB17
15 BCPRS
8
0011 x1xx
CSS
FCPRS
BCPRS
The Clock Source Select bit selects one out of two possible clock sources for the audio interTMD face. After reset, the CSS bit is clear. 0 - The Aux1 clock is used to clock the Audio Interface. 1 - The 48-MHz USB clock is used to clock the Audio Interface. The Frame Clock Prescaler is used to divide the bit clock to generate the frame clock for the receive and transmit operations. The bit clock is divided by (FCPRS + 1). After reset, the FCPRS field is clear. The maximum allowed bit clock rate to achieve an 8 kHz frame clock is 1024 kHz. The Bit Clock Prescaler is used to divide the audio interface clock (selected by the CSS bit) to generate the bit clock for the receive and transmit operations. The audio interface input clock is divided by (BCPRS + 1). After reset, the BCPRS[7:0] bits are clear.
1xxx
The Transmit Master DMA field specifies which slots (audio channels) are supported by DMA, i.e. when a DMA request is asserted to the DMA controller. If the TMD bit is set for an assigned slot n (TXDSAn = 1), a DMA request n is asserted, when the ATDRn register is empty. If the TXDSA bit for a slot is clear, the TMD bit is ignored. The following table shows the transmit DMA request scheme. TMD 0000 0001 0010 0011 x1xx 1xxx DMA Request Condition None ATDR0 empty ATDR1 empty ATDR0 empty or ATDR1 empty Not supported on CP3UB17
16.7.10 Audio DMA Control Register (ADMACR) The ADMACR register is used to control the DMA support of the audio interface. In addition, it is used to configure the automatic transmission of the audio control bits. After reset, this register is clear. 7 TMD 4 3 RMD 0
ACD
ACO
15 Reserved
13
12 ACO
11
10 ACD
8
The Audio Control Data field is used to fill the remaining bits of a 16-bit slot if only 13, 14, or 15 bits of PCM audio data are transmitted. The Audio Control Output field controls the number of control bits appended to the PCM data word. 00 - No Audio Control bits are appended. 01 - Append ACD0. 10 - Append ACD1:0. 11 - Append ACD2:0.
RMD
The Receive Master DMA field specify which slots (audio channels) are supported by DMA, i.e. when a DMA request is asserted to the DMA controller. If the RMDn bit is set for an assigned slot n (RXDSAn = 1), a DMA request n is asserted, when the ARDRn is full. If the RXDSAn bit for a slot is clear, the RMDn bit is
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17.0 CVSD/PCM Conversion Module
The CVSD/PCM module performs conversion between CVSD data and PCM data, in which the CVSD encoding is as defined in the Bluetooth specification and the PCM encoding may be 8-bit -Law, 8-bit A-Law, or 13-bit to 16-bit Linear. The CVSD conversion module operates at a fixed rate of 125 s (8 kHz) per PCM sample. On the CVSD side, there
2 MHz Clock Input
is a read and a write FIFO allowing up to 8 words of data to be read or written at the same time. On the PCM side, there is a double-buffered register requiring data to be read and written every 125 s. The intended use is to move CVSD data into the module with a CVSD interrupt handler, and to move PCM data with DMA. Figure 24 shows a block diagram of the CVSD to PCM module.
Interrupt
DMA
16-Bit 8 kHz 16-Bit u/A-Law 16-Bit 8 kHz Filter Engine 16-Bit u/A-Law 64 kHz 64 kHz CVSD Encoder
1-Bit 64 kHz 16-Bit Shift Reg
1-Bit 64 kHz CVSD Decoder 16-Bit Shift Reg
Peripheral Bus
DS058
Figure 24. CVSD/PCM Converter Block Diagram
17.1
Inside the module, a filter engine receives the 8 kHz stream of 16-bit samples and interpolates to generate a 64 kHz The Aux2 clock (generated by the Clock module described stream of 16-bit samples. This goes into a CVSD encoder in Section 11.9) must be configured, because it drives the which converts the data into a single-bit delta stream using CVSD module. Software must set its prescaler to provide a the CVSD parameters as defined by the Bluetooth specifi2 MHz input clock based upon the System Clock (usually cation. There is a similar path that reverses this process 12 MHz). This is done by writing an appropriate divisor to converting the CVSD 64 kHz bit stream into a 64 kHz 16-bit the ACDIV2 field of the PRSAC register. Software must also data stream. The filter engine then decimates this stream enable the Aux2 clock by setting the ACE2 bit within the into an 8 kHz, 16-bit data stream. CRCTRL register. For example: PRSAC &= 0x0f; // Set Aux2 prescaler to generate // 2 MHz (Fsys = 12 MHz) PRSAC |= 0x50; CRCTRL |= ACE2; // Enable Aux2 clk The module converts between PCM data and CVSD data at a fixed rate of 8 kHz per PCM sample. Due to compression, the data rate on the CVSD side is only 4 kHz per CVSD sample.
OPERATION
17.2
PCM CONVERSIONS
If PCM interrupts are enabled (PCMINT is set) every 125 s (8 kHz) an interrupt will occur and the interrupt handler can operate on some or all of the four audio streams CVSD in, CVSD out, PCM in, and PCM out. Alternatively, a DMA request is issued every 125 s and the DMA controller is used If a conversion is performed between linear and -Law log to move the PCM data between the PCM2CVSD module PCM data, the linear PCM data are treated in the leftand the audio interface. aligned 14-bit linear data format with the two LSBs unused. If CVSD interrupts are enabled, an interrupt is issued when If a conversion is performed between linear and A-Law log either one of the CVSD FIFOs is almost empty or almost full. PCM data, the linear PCM data are treated in the leftOn the PCM data side there is double buffering, and on the aligned 13-bit linear data format with the three LSBs unCVSD side there is an eight word (8 x 16-bit) FIFO for the used. read and write paths.
During conversion between CVSD and PCM, any PCM format changes are done automatically depending on whether the PCM data is -Law, A-Law, or Linear. In addition to this, a separate function can be used to convert between the various PCM formats as required. Conversion is performed by setting up the control bit CVCTL1.PCMCONV to define the conversion and then writing to the LOGIN and LINEARIN registers and reading from the LOGOUT and LINEAROUT registers. There is no delay in the conversion operation and it does not have to operate at a fixed rate. It will only convert between -Law/A-Law and linear, not directly between Law and A-Law. (This could easily be achieved by converting between -Law and linear and between linear and ALaw.)
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If the module is only used for PCM conversions, the CVSD ready empty CVSD In FIFO, the FIFO automatically returns clock can be disabled by clearing the CVSD Clock Enable a checkerboard pattern to guarantee a minimum level of disbit (CLKEN) in the control register. tortion of the audio stream.
17.3
CVSD CONVERSION
17.6
INTERRUPT GENERATION
The PCM2CVSD converter module transforms either 8-bit An interrupt is generated in any of the following cases: logarithmic or 13- to 16-bit linear PCM samples at a fixed When a new PCM sample has been written into the rate of 8 ksps. The CVSD to PCM conversion format must PCMOUT register and the CVCTRL.PCMINT bit is set. be specified by the CVSDCONV control bits in the CVSD When a new PCM sample has been read from the Control register (CVCTRL). PCMIN register and the CVCTRL.PCMINT bit is set. The CVSD algorithm is tuned for 13- or 14-bit right-aligned When the CVSD In FIFO is nearly empty data. It will operate with 16-bit data, but this will produce dis(CVSTAT.CVNE = 1) and the CVCTRL.CVSDINT bit is tortion. This can be handled by using the RESOLUTION set. control bits in the CVSD Control register (CVCTRL) to specWhen the CVSD Out FIFO is nearly full ify shifting the data by 1, 2, or 3 bit positions before perform(CVSTAT.CVNF = 1) and the CVCTRL.CVSDINT bit is ing the conversion. set. When the CVSD In FIFO is empty (CVSTAT.CVE = 1) For linear PCM data, the resolution (13-, 14-, 15-, or 16-bit) and the CVCTRL.CVSDERRINT bit is set. should be specified by the RESOLUTION bits for the resoWhen the CVSD Out FIFO is full (CVSTAT.CVF = 1) and lution of the linear data format. For maximum resolution with the CVCTRL.CVSDERRINT bit is set. A-Law log PCM data, the RESOLUTION bits should be programmed for 13-bit resolution. For -Law log PCM data, the Both the CVSD In and CVSD Out FIFOs have a size of RESOLUTION bits should be programmed for 14-bit resolu- 8 x 16 bit (8 words). The warning limits for the two FIFOs is set at 5 words. (The CVSD In FIFO interrupt will occur when tion. If the resolution is not set properly, the audio signal may be there are 3 words left in the FIFO, and the CVSD Out FIFO interrupt will occur when there are 3 or less empty words left clipped or have reduced attenuation. in the FIFO.) The limit is set to 5 words because Bluetooth 17.4 PCM TO CVSD CONVERSION audio data is transferred in packages composed of 10 or The converter core reads out the double-buffered PCMIN multiples of 10 bytes. register every 125 s and writes a new 16-bit CVSD data stream into the CVSD Out FIFO every 250 s. If the PCMIN buffer has not been updated with a new PCM sample between two reads from the CVSD core, the old PCM data is used again to maintain a fixed conversion rate. Once a new 16-bit CVSD data stream has been calculated, it is copied into the 8 x 16-bit wide CVSD Out FIFO. If there are only three empty words (16-bit) left in the FIFO, the nearly full bit (CVNF) is set, and, if enabled (CVSDINT = 1), an interrupt request is asserted. If the CVSD Out FIFO is full, the full bit (CVF) is set, and, if enabled (CVSDERRINT = 1), an interrupt request is asserted. In this case, the CVSD Out FIFO remains unchanged. Within the interrupt handler, the CPU can read out the new CVSD data. If the CPU reads from an already empty CVSD Out FIFO, the FIFO automatically returns a checkerboard pattern to guarantee a minimum level of distortion of the audio stream.
17.7
DMA SUPPORT
The CVSD module can operate with any of four DMA channels. Four DMA channels are required for processor independent operation. Both receive and transmit for CVSD data and PCM data can be enabled individually. The PCM2CVSD module asserts a DMA request to the on-chip DMA controller under the following conditions: The DMAPO bit is set and the PCMOUT register is full, because it has been updated by the converter core with a new PCM sample. (The DMA controller can read out one PCM data word from the PCMOUT register.) The DMAPI bit is set and the PCMIN register is empty, because it has been read by the converter core. (The DMA controller can write one new PCM data word into the PCMIN register.) The DMACO bit is set and a new 16-bit CVSD data stream has been copied into the CVSD Out FIFO. (The DMA controller can read out one 16-bit CVSD data word from the CVSD Out FIFO.) The DMACI bit is set and a 16-bit CVSD data stream has been read from the CVSD In FIFO. (The DMA controller can write one new 16-bit CVSD data word into the CVSD In FIFO.)
17.5
CVSD TO PCM CONVERSION
The converter core reads from the CVSD In FIFO every 250 s and writes a new PCM sample into the PCMOUT buffer every 125 s. If the previous PCM data has not yet been transferred to the audio interface, it will be overwritten The CVSD/PCM module only supports indirect DMA transwith the new PCM sample. fers. Therefore, transferring PCM data between the CVSD/ If there are only three unread words left, the CVSD In Nearly PCM module and another on-chip module requires two bus Empty bit (CVNE) is set and, if enabled (CVSDINT = 1), an cycles. interrupt request is generated. If the CVSD In FIFO is empty, the CVSD In Empty bit (CVE) is set and, if enabled (CVSDERRINT = 1), an interrupt request is generated. If the converter core reads from an alwww.national.com 102
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The trigger for DMA may also trigger an interrupt if the corresponding enable bits in the CVCTRL register is set. Therefore care must be taken when setting the desired interrupt and DMA enable bits. The following conditions must be avoided: Setting the PCMINT bit and either of the DMAPO or DMAPI bits. Setting the CVSDINT bit and either of the DMACO or DMACI bits.
17.9.1
CVSD Data Input Register (CVSDIN)
The CVSDIN register is a 16-bit wide, write-only register. It is used to write CVSD data into the CVSD to PCM converter FIFO. The FIFO is 8 words deep. The CVSDIN bit 15 represents the CVSD data bit at t = t0, CVSDIN bit 0 represents the CVSD data bit at t = t0 - 250 ms. 15 CVSDIN 0
17.8
FREEZE
17.9.2
The CVSD/PCM module provides support for an In-SystemEmulator by means of a special FREEZE input. While FREEZE is asserted the module will exhibit the following behavior: CVSD In FIFO will not have data removed by the converter core. CVSD Out FIFO will not have data added by the converter core. PCM Out buffer will not be updated by the converter core. The Clear-on-Read function of the following status bits in the CVSTAT register is disabled: PCMINT CVE CVF
CVSD Data Output Register (CVSDOUT)
The CVSDOUT register is a 16-bit wide read-only register. It is used to read the CVSD data from the PCM to CVSD converter. The FIFO is 8 words deep. Reading the CVSDOUT register after reset returns undefined data. 15 CVSDOUT 0
17.9.3
PCM Data Input Register (PCMIN)
17.9
CVSD/PCM CONVERTER REGISTERS
Table 40 CVSD/PCM Registers Name Address FF FC20h FF FC22h FF FC24h FF FC26h FF FC28h FF FC2Ah FF FC2Ch FF FC2Eh FF FC30h FF FC32h Description CVSD Data Input Register CVSD Data Output Register PCM Data Input Register PCM Data Output Register Logarithmic PCM Data Input Register Logarithmic PCM Data Output Register Linear PCM Data Input Register Linear PCM Data Output Register CVSD Control Register CVSD Status Register
The PCMIN register is a 16-bit wide write-only register. It is used to write PCM data to the PCM to CVSD converter via the peripheral bus. It is double-buffered, providing a 125 s period for an interrupt or DMA request to respond. 15 PCMIN 0
Table 40 lists the CVSD/PCM registers.
CVSDIN CVSDOUT PCMIN PCMOUT LOGIN LOGOUT LINEARIN LINEAROUT CVCTRL CVSTAT
17.9.4
PCM Data Output Register (PCMOUT)
The PCMOUT register is a 16-bit wide read-only register. It is used to read PCM data from the CVSD to PCM converter. It is double-buffered, providing a 125 s period for an interrupt or DMA request to respond. After reset the PCMOUT register is clear. 15 PCMOUT 0
17.9.5
Logarithmic PCM Data Input Register (LOGIN)
The LOGIN register is an 8-bit wide write-only register. It is used to receive 8-bit logarithmic PCM data from the peripheral bus and convert it into 13-bit linear PCM data. 7 LOGIN 0
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17.9.6
The CVSD Clock Enable bit enables the 2MHz clock to the filter engine and CVSD encoders and decoders. The LOGOUT register is an 8-bit wide read-only register. It 0 - CVSD module clock disabled. holds logarithmic PCM data that has been converted from 1 - CVSD module clock enabled. linear PCM data. After reset, the LOGOUT register is clear. PCMINT The PCM Interrupt Enable bit controls generation of the PCM interrupt. If set, this bit en7 0 ables the PCM interrupt. If the PCMINT bit is clear, the PCM interrupt is disabled. After reLOGOUT set, this bit is clear. 0 - PCM interrupt disabled. 1 - PCM interrupt enabled. 17.9.7 Linear PCM Data Input Register (LINEARIN) CVSDINT The CVSD FIFO Interrupt Enable bit controls The LINEARIN register is a 16-bit wide write-only register. generation of the CVSD interrupt. If set, this The data is left-aligned. When converting to A-law, bits 2:0 bit enables the CVSD interrupt that occurs if are ignored. When converting to -law, bits 1:0 are ignored. the CVSD In FIFO is nearly empty or the CVSD Out FIFO is nearly full. If the CVSDINT 15 0 bit is clear, the CVSD nearly full/nearly empty interrupt is disabled. After reset, this bit is LINEARIN clear. 0 - CVSD interrupt disabled. 1 - CVSD interrupt enabled. 17.9.8 Linear PCM Data Output Register CVSDERRINT The CVSD FIFO Error Interrupt Enable bit (LINEAROUT) controls generation of the CVSD error interThe LINEAROUT register is a 16-bit wide read-only register. rupt. If set, this bit enables an interrupt to ocThe data is left-aligned. When converting from A-law, bits cur when the CVSD Out FIFO is full or the 2:0 are clear. When converting from -law, bits 1:0 are clear. CVSD In FIFO is empty. If the CVSDERRORAfter reset, this register is clear. INT bit is clear, the CVSD full/empty interrupt is disabled. After reset, this bit is clear. 0 - CVSD error interrupt disabled. 15 0 1 - CVSD error interrupt enabled. LINEAROUT DMACO The DMA Enable for CVSD Out bit enables hardware DMA control for reading CVSD data from the CVSD Out FIFO. If clear, DMA sup17.9.9 CVSD Control Register (CVCTRL) port is disabled. After reset, this bit is clear. The CVCTRL register is a 16-bit wide, read/write register 0 - CVSD output DMA disabled. that controls the mode of operation and of the module's in1 - CVSD output DMA enabled. terrupts. At reset, all implemented bits are cleared. DMACI The DMA Enable for CVSD In bit enables hardware DMA control for writing CVSD data into the CVSD In FIFO. If clear, DMA support 7 6 5 4 3 2 1 0 is disabled. After reset, this bit is clear. CVSD 0 - CVSD input DMA disabled. DMA DMA DMA CVSD PCM CLK CVEN ERR1 - CVSD input DMA enabled. PO CI CO INT INT EN INT DMAPO The DMA Enable for PCM Out bit enables hardware DMA control for reading PCM data from the PCMOUT register. If clear, DMA sup15 14 13 12 11 10 9 8 port is disabled. After reset, this bit is clear. 0 - PCM output DMA disabled. Res. RESOLUTION PCMCONV CVSDCONV DMAPI 1 - PCM output DMA enabled. DMAPI The DMA Enable for PCM In bit enables hardware DMA control for writing PCM data into CVEN The Module Enable bit enables or disables the the PCMIN register. If cleared, DMA support CVSD conversion module interface. When the is disabled. After reset, this bit is clear. bit is set, the interface is enabled which allows 0 - PCM input DMA disabled. read and write operations to the rest of the 1 - PCM input DMA enabled. module. When the bit is clear, the module is disabled. When the module is disabled the CVSDCONV The CVSD to PCM Conversion Format field specifies the PCM format for PCM/CVSD constatus register CVSTAT will be cleared to its versions. After reset, this field is clear. reset state. 00 - CVSD <-> 8-bit -Law PCM. 0 - CVSD module enabled. 01 - CVSD <-> 8-bit A-Law PCM. 1 - CVSD module disabled. 10 - CVSD <-> Linear PCM. 11 - Reserved. www.national.com 104
Logarithmic PCM Data Output Register (LOGOUT)
CLKEN
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PCMCONV The PCM to PCM Conversion Format bit se- CVE lects the PCM format for PCM/PCM conversions. 0 - Linear PCM <-> 8-bit -Law PCM 1 - Linear PCM <-> 8-bit A-Law PCM RESOLUTION The PCM Resolution field specifies the resolution of the PCM format for the linear PCM/ CVSD conversions. It also affects log data, because log data is converted to 16-bit linear form before resolution adjustment. After reset, these two bits are clear. 00 - 16-bit linear PCM CVF 01 - 15-bit linear PCM 10 - 14-bit linear PCM 11 - 13-bit linear PCM 17.9.10 CVSD Status Register (CVSTAT) The CVSTAT register is a 16-bit wide, read-only register that holds the status information of the CVSD/PCM module. At reset, and if the CVCTL1.CVEN bit is clear, all implemented bits are cleared. 7 CVINST 5 4 CVF 3 2 1 0 CVINST
CVE PCMINT CVNF CVNE CVOUTST
15 Reserved
11
10 CVOUTST
8
The CVSD In FIFO Empty bit indicates when the CVSD In FIFO has been read by the CVSD converter while the FIFO was already empty. If the CVSDERRORINT bit is set, an interrupt will be asserted when the CVE bit is set. The CVE bit is cleared when the CVSTAT register is read. 0 - CVSD In FIFO has not been read while empty. 1 - CVSD In FIFO has been read while empty. The CVSD Out FIFO Full bit set indicates whether the CVSD Out FIFO has been written by the CVSD converter while the FIFO was already full. If the CVSDERRORINT bit is set, an interrupt will be asserted when the CVF bit is set. The CVF bit is cleared when the CVSTAT register is read. 0 - CVSD Out FIFO has not been written while full. 1 - CVSD Out FIFO has been written while full. The CVSD In FIFO Status field reports the current number of empty 16-bit word locations in the CVSD In FIFO. CVSD Out FIFO Status field reports the current number of valid 16-bit CVSD data words in the CVSD Out FIFO.
CVNE
CVNF
PCMINT
The CVSD In FIFO Nearly Empty bit indicates when only three CVSD data words are left in the CVSD In FIFO, so new CVSD data should be written into the CVSD In FIFO. If the CVSDINT bit is set, an interrupt will be asserted when the CVNE bit is set. If the DMACI bit is set, a DMA request will be asserted when this bit is set. The CVNE bit is cleared when the CVSTAT register is read. 0 - CVSD In FIFO is not nearly empty. 1 - CVSD In FIFO is nearly empty. The CVSD Out FIFO Nearly Full bit indicates when only three empty word locations are left in the CVSD Out FIFO, so the CVSD Out FIFO should be read. If the CVSDINT bit is set, an interrupt will be asserted when the CVNF bit is set. If the DMACO bit is set, a DMA request will be asserted when this bit is set. The CVNF bit is cleared when the CVSTAT register is read. 0 - CVSD Out FIFO is not nearly full. 1 - CVSD Out FIFO is nearly full. The PCM Interrupt bit set indicates that the PCMOUT register is full and needs to be read or the PCMIN register is empty and needs to be loaded with new PCM data. The PCMINT bit is cleared when the CVSTAT register is read. 0 - PCM does not require service. 1 - PCM requires loading or unloading.
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18.0 UART Module
The UART module is a full-duplex Universal Asynchronous Receiver/Transmitter that supports a wide range of software-programmable baud rates and data formats. It handles automatic parity generation and several error detection schemes. The UART module offers the following features: Full-duplex double-buffered receiver/transmitter Programmable baud rate Programmable framing formats: 7, 8, or 9 data bits; even, odd, or no parity; one or two stop bits (mark or space) Hardware parity generation for data transmission and parity check for data reception Interrupts on "transmit ready" and "receive ready" conditions, separately enabled Software-controlled break transmission and detection Internal diagnostic capability Automatic detection of parity, framing, and overrun errors Hardware flow control (CTS and RTS signals) DMA capability of data from the UART, it de-asserts the clear-to-send (CTS) signal which causes the UART to pause after sending the current frame (if any). The UART asserts the ready-to-send (RTS) signal to the peripheral when it is ready to send a character.
18.2
UART OPERATION
The UART normally operates in asynchronous mode. There are two special-purpose modes, called attention and diagnostic. This section describes the operating modes of the UART. 18.2.1 Asynchronous Mode
The asynchronous mode of the UART enables the device to communicate with other devices using just two communication signals: transmit and receive.
In asynchronous mode, the transmit shift register (TSFT) and the transmit buffer (UTBUF) double-buffer the data for transmission. To transmit a character, a data byte is loaded in the UTBUF register. The data is then transferred to the TSFT register. While the TSFT register is shifting out the 18.1 FUNCTIONAL OVERVIEW current character (LSB first) on the TXD pin, the UTBUF Figure 25 is a block diagram of the UART module showing register is loaded by software with the next byte to be transthe basic functional units in the UART: mitted. When TSFT finishes transmission of the last stop bit Transmitter of the current frame, the contents of UTBUF are transferred Receiver to the TSFT register and the Transmit Buffer Empty bit (UTBaud Rate Generator BE) is set. The UTBE bit is automatically cleared by the Control and Error Detection UART when software loads a new character into the UTBUF The Transmitter block consists of an 8-bit transmit shift reg- register. During transmission, the UXMIP bit is set high by ister and an 8-bit transmit buffer. Data bytes are loaded in the UART. This bit is reset only after the UART has sent the parallel from the buffer into the shift register and then shifted last stop bit of the current character and the UTBUF register is empty. The UTBUF register is a read/write register. The out serially on the TXD pin. TSFT register is not software accessible. The Receiver block consists of an 8-bit receive shift register and an 8-bit receive buffer. Data is received serially on the In asynchronous mode, the input frequency to the UART is RXD pin and shifted into the shift register. Once eight bits 16 times the baud rate. In other words, there are 16 clock have been received, the contents of the shift register are cycles per bit time. In asynchronous mode, the baud rate generator is always the UART clock source. transferred in parallel to the receive buffer. The receive shift register (RSFT) and the receive buffer (URBUF) double buffer the data being received. The UART receiver continuously monitors the signal on the RXD pin for a low level to detect the beginning of a start bit. On sensing The Baud Rate Generator generates the bit shift clock. It this low level, the UART waits for seven input clock cycles consists of two registers and a two-stage counter. The regand samples again three times. If all three samples still inisters are used to specify a prescaler value and a baud rate dicate a valid low, then the receiver considers this to be a divisor. The first stage of the counter divides the UART clock valid start bit, and the remaining bits in the character frame based on the value of the programmed prescaler to create are each sampled three times, around the mid-bit position. a slower clock. The second stage of the counter creates the For any bit following the start bit, the logic value is found by baud rate clock by dividing the output of the first stage majority voting, i.e. the two samples with the same value debased on the programmed baud rate divisor. fine the value of the data bit. Figure 26 illustrates the proThe Control and Error Detection block contains the UART cess of start bit detection and bit sampling. control registers, control logic, error detection circuit, parity Data bits are sensed by taking a majority vote of three samgenerator/checker, and interrupt generation logic. The conples latched near the midpoint of each baud (bit time). Nortrol registers and control logic determine the data format, mally, the position of the samples within the baud is mode of operation, clock source, and type of parity used. determined automatically, but software can override the auThe error detection circuit generates parity bits and checks tomatic selection by setting the USMD bit in the UMDSL2 for parity, framing, and overrun errors. register and programming the USPOS register. The Flow Control Logic block provides the capability for Serial data input on the RXD pin is shifted into the RSFT hardware handshaking between the UART and a peripheral register. On receiving the complete character, the contents device. When the peripheral device needs to stop the flow The Transmitter and Receiver blocks both contain extensions for 9-bit data transfers, as required by the 9-bit and loopback operating modes. www.national.com 106
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of the RSFT register are copied into the URBUF register from the URBUF register. The RSFT register is not software and the Receive Buffer Full bit (URBF) is set. The URBF bit accessible. is automatically reset when software reads the character
Transmitter
TXD
Baud Clock RTS System Clock Flow Control Logic CTS Internal Bus Control and Error Detection
Baud Rate Generator
Parity Generator/Checker Baud Clock
Receiver
RXD
DS163
Figure 25.
UART Block Diagram
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
Sample STARTBIT
Sample DATA (LSB)
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
Sample DATABIT DS061
Figure 26. 18.2.2 Attention Mode
UART Asynchronous Communication acter, the contents of the receive shift register are copied to the receive buffer. The URBF bit is set and an interrupt (if enabled) is generated. The UATN bit is automatically cleared, and the UART begins receiving all subsequent characters. Software must examine the contents of the URBUF register and respond by accepting the subsequent characters (by leaving the UATN bit reset) or waiting for the next address character (by setting the UATN bit again). The operation of the UART transmitter is not affected by the selection of this mode. The value of the ninth bit to be transmitted is programmed by setting or clearing the UXB9 bit in
The Attention mode is available for networking this device with other processors. This mode requires the 9-bit data format with no parity. The number of start bits and number of stop bits are programmable. In this mode, two types of 9-bit characters are sent on the network: address characters consisting of 8 address bits and a 1 in the ninth bit position and data characters consisting of 8 data bits and a 0 in the ninth bit position. While in Attention mode, the UART receiver monitors the communication flow but ignores all characters until an address character is received. On receiving an address char-
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the UART Frame Select register. The value of the ninth bit received is read from URB9 in the UART Status Register. 18.2.3 Diagnostic Mode
the control registers, called UXB9 and URB9. Parity is not generated or verified in this mode.
3 Start Bit 9-Bit Data 1S
The Diagnostic mode is available for testing of the UART. In this mode, the TXD and RXD pins are internally connected together, and data shifted out of the transmit shift register is immediately transferred to the receive shift register. This mode supports only the 9-bit data format with no parity. The number of start and stop bits is programmable. 18.2.4 Frame Format Selection
3a
Start Bit
9-Bit Data
2S
DS065
Figure 29. 9-bit Data Frame Options The format shown in Figure 27 consists of a start bit, seven 18.2.5 Baud Rate Generator data bits (excluding parity), and one or two stop bits. If parity bit generation is enabled by setting the UPEN bit, a parity bit The Baud Rate Generator creates the basic baud clock from is generated and transmitted following the seven data bits. the System Clock. The System Clock is passed through a two-stage divider chain consisting of a 5-bit baud rate prescaler (UPSC) and an 11-bit baud rate divisor (UDIV). Start
1 Bit 7-Bit Data 1S
The relationship between the 5-bit prescaler select (UPSC) setting and the prescaler factors is shown in Table 41.
2S
1a
Start Bit
7-Bit Data
Table 41 Prescaler Factors Prescaler Select Prescaler Factor No clock 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 10.5 11 11.5 12 12.5 13
1b
Start Bit
7-Bit Data
PA
1S
00000
1c Start Bit 7-Bit Data PA 2S
00001 00010
DS063
00011 00100 00101
Figure 27.
7-Bit Data Frame Options
The format shown in Figure 28 consists of one start bit, eight data bits (excluding parity), and one or two stop bits. If parity bit generation is enabled by setting the UPEN bit, a parity bit is generated and transmitted following the eight data bits.
Start Bit
00110 00111 01000 01001
2
8-Bit Data
1S
01010 01011
2a
Start Bit
8-Bit Data
2S
01100 01101
2b
Start Bit
8-Bit Data
PA
1S
01110 01111
2c
Start Bit
8-Bit Data
PA
2S DS064
10000 10001 10010 10011 10100 10101 10110 10111 11000 11001
Figure 28.
8-Bit Data Frame Options
The format shown in Figure 29 consists of one start bit, nine data bits, and one or two stop bits. This format also supports the UART attention feature. When operating in this format, all eight bits of UTBUF and URBUF are used for data. The ninth data bit is transmitted and received using two bits in
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Table 41 Prescaler Factors (Continued) Prescaler Select 11010 11011 11100 11101 11110 11111 Prescaler Factor 13.5 14 14.5 15 15.5 16
In asynchronous mode, the baud rate is calculated by: SYS_CLK BR = ----------------------------(O x N x P) where BR is the baud rate, SYS_CLK is the System Clock frequency, O is the oversample rate, N is the value of the baud rate divisor + 1, and P is the prescaler divide factor selected by the value in the UPSR register. 18.2.6 Interrupts
The UART is capable of generating interrupts on:
Receive Buffer Full Receive Error A prescaler factor of zero corresponds to "no clock." The "no Transmit Buffer Empty clock" condition is the UART power down mode, in which the UART clock is turned off to reduce power consumption. Figure 30 shows a diagram of the interrupt sources and asSoftware must select the "no clock" condition before enter- sociated enable bits. ing a new baud rate. Otherwise, it could cause incorrect data to be received or transmitted.
UEEI
UFE
UDOE
UERR RX Interrupt UERI
UPE
URBF
UETI
UTBE
TX Interrupt UEFCI
UDCTS
FC Interrupt DS066
Figure 30.
UART Interrupts bit or read the UICTRL register (which clears the UDCTS bit).
The interrupts can be individually enabled or disabled using the Enable Transmit Interrupt (UETI), Enable Receive Interrupt (UERI), and Enable Receive Error Interrupt (UEER) bits in the UICTRL register.
In addition to the dedicated inputs to the ICU for UART interrupts, the UART receive (RXD) and Clear To Send (CTS) A transmit interrupt is generated when both the UTBE and signals are inputs to the MIWU (see Section 13.0), which UETI bits are set. To remove this interrupt, software must ei- can be programmed to generate edge-triggered interrupts. ther disable the interrupt by clearing the UETI bit or write to 18.2.7 DMA Support the UTBUF register (which clears the UTBE bit). The UART can operate with one or two DMA channels. Two A receive interrupt is generated on these conditions: DMA channels must be used for processor-independent Both the URBF and UERI bits are set. To remove this in- full-duplex operation. Both receive and transmit DMA can terrupt, software must either disable the interrupt by be enabled simultaneously. clearing the UERI bit or read from the URBUF register If transmit DMA is enabled (the UETD bit is set), the UART (which clears the URBF bit). generates a DMA request when the UTBE bit changes state Both the UERR and the UEEI bits are set. To remove this from clear to set. Enabling transmit DMA automatically disinterrupt, software must either disable the interrupt by ables transmit interrupts, without regard to the state of the clearing the UEEI bit or read the USTAT register (which UETI bit. clears the UERR bit). If receive DMA is enabled (the UERD bit is set), the UART A flow control interrupt is generated when both the UDCTS generates a DMA request when the URBF bit changes state and the UEFCI bits are set. To remove this interrupt, softfrom clear to set. Enabling receive DMA automatically disware must either disable the interrupt by clearing the UEFCI
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ables receive interrupts, without regard to the state of the UERI bit. However, receive error interrupts should be enabled (the UEEI bit is set) to allow detection of receive errors when DMA is used. 18.2.8 Break Generation and Detection
18.3.1
UART Receive Data Buffer (URBUF)
The URBUF register is a byte-wide, read/write register used to receive each data byte. 7 URBUF 0
A line break is generated when the UBRK bit is set in the UMDSL1 register. The TXD line remains low until the program resets the UBRK bit.
A line break is detected if RXD remains low for 10 bit times 18.3.2 UART Transmit Data Buffer (UTBUF) or longer after a missing stop bit is detected. The UTBUF register is a byte-wide, read/write register used to transmit each data byte. 18.2.9 Parity Generation and Detection Parity is only generated or checked with the 7-bit and 8-bit 7 0 data formats. It is not generated or checked in the diagnostic loopback mode, the attention mode, or in normal mode with UTBUF the 9-bit data format. Parity generation and checking are enabled and disabled using the PEN bit in the UFRS register. The UPSEL bits in the UFRS register are used to select 18.3.3 UART Baud Rate Prescaler (UPSR) odd, even, or no parity. The UPSR register is a byte-wide, read/write register that contains the 5-bit clock prescaler and the upper three bits of 18.3 UART REGISTERS the baud rate divisor. This register is cleared upon reset. Software interacts with the UART by accessing the UART The register format is shown below. registers. There are eight registers, as listed in Table 42. Table 42 UART Registers Name URBUF UTBUF UPSR UBAUD UFRS UMDSL1 USTAT UICTRL UOVR UMDSL2 USPOS Address FF FE42h FF FE40h FF FE4Eh FF FE4Ch FF FE48h FF FE4Ah FF FE46h FF FE44h FF FE50h FF FE52h FF FE54h Description UART Receive Data Buffer UART Transmit Data Buffer UART Baud Rate Prescaler UART Baud Rate Divisor UART Frame Select Register UART Mode Select Register 1 UART Status Register UART Interrupt Control Register UART Oversample Rate Register UART Mode Select Register 2 UART Sample Position Register UDIV7:0 The Baud Rate Divisor field holds the eight lowest-order bits of the UART baud rate divisor used in the second stage of the two-stage divider chain. The three most significant bits are held in the UPSR register. The divisor value used is (UDIV[10:0] + 1). 18.3.4 UDIV10:8 7 UPSC 3 2 UDIV10:8 0
UPSC
The Prescaler field specifies the prescaler value used for dividing the System Clock in the first stage of the two-stage divider chain. For the prescaler factors corresponding to each 5bit value, see Table 41. The Baud Rate Divisor field holds the three most significant bits (bits 10, 9, and 8) of the UART baud rate divisor used in the second stage of the two-stage divider chain. The remaining bits of the baud rate divisor are held in the UBAUD register.
UART Baud Rate Divisor (UBAUD)
The UBAUD register is a byte-wide, read/write register that contains the lower eight bits of the baud rate divisor. The register contents are unknown at power-up and are left unchanged by a reset operation. The register format is shown below. 7 UDIV7:0 0
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18.3.5
UART Frame Select Register (UFRS)
18.3.6
UART Mode Select Register 1 (UMDSL1)
The UFRS register is a byte-wide, read/write register that controls the frame format, including the number of data bits, number of stop bits, and parity type. This register is cleared upon reset. The register format is shown below. 7 6 5 4 3 UXB9 2 USTP 1 0
The UMDSL1 register is a byte-wide, read/write register that selects the clock source, synchronization mode, attention mode, and line break generation. This register is cleared at reset. When software writes to this register, the reserved bits must be written with 0 for proper operation. The register format is shown below. 7 6 5 4 3 2 1 0 Res.
Reserved UPEN
UPSEL
UCHAR
URTS UFCE UERD UETD Res. UBRK UATN UCHAR The Character Frame Format field selects the number of data bits per frame, not including the parity bit, as follows: 00 - 8 data bits per frame. 01 - 7 data bits per frame. 10 - 9 data bits per frame. 11 - Loop-back mode, 9 data bits per frame. The Stop Bits bit specifies the number of stop bits transmitted in each frame. If this bit is 0, one stop bit is transmitted. If this bit is 1, two stop bits are transmitted. 0 - One stop bit per frame. 1 - Two stop bits per frame. The Transmit 9th Data Bit holds the value of the ninth data bit, either 0 or 1, transmitted when the UART is configured to transmit nine data bits per frame. It has no effect when the UART is configured to transmit seven or eight data bits per frame. The Parity Select field selects the treatment of the parity bit. When the UART is configured to transmit nine data bits per frame, the parity bit is omitted and the UPSEL field is ignored. 00 - Odd parity. 01 - Even parity. 10 - No parity, transmit 1 (mark). 11 - No parity, transmit 0 (space). The Parity Enable bit enables or disables parity generation and parity checking. When the UART is configured to transmit nine data bits per frame, there is no parity bit and the UPEN bit is ignored. 0 - Parity generation and checking disabled. 1 - Parity generation and checking enabled.
UATN
USTP
UBRK
UXB9
UETD
UPSEL
UERD
UPEN
UFCE
URTS
The Attention Mode bit is used to enable Attention mode. When set, this bit selects the attention mode of operation for the UART. When clear, the attention mode is disabled. The hardware clears this bit after an address frame is received. An address frame is a 9-bit character with a 1 in the ninth bit position. 0 - Attention mode disabled. 1 - Attention mode enabled. The Force Transmission Break bit is used to force the TXD output low. Setting this bit to 1 causes the TXD pin to go low. TXD remains low until the UBRK bit is cleared by software. 0 - Normal operation. 1 - TXD pin forced low. The Enable Transmit DMA bit controls whether DMA is used for UART transmit operations. Enabling transmit DMA automatically disables transmit interrupts, without regard to the state of the UETI bit. 0 - Transmit DMA disabled. 1 - Transmit DMA enabled. The Enable Receive DMA bit controls whether DMA is used for UART receive operations. Enabling receive DMA automatically disables receive interrupts, without regard to the state of the UERI bit. Receive error interrupts are unaffected by the UERD bit. 0 - Receive DMA disabled. 1 - Receive DMA enabled. The Flow Control Enable bit controls whether flow control interrupts are enabled. 0 - Flow control interrupts disabled. 1 - Flow control interrupts enabled. The Ready To Send bit directly controls the state of the RTS output. 0 - RTS output is high. 1 - RTS output is low.
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18.3.7
UART Status Register (USTAT)
UXMIP
The USTAT register is a byte-wide, read-only register that contains the receive and transmit status bits. This register is cleared upon reset. Any attempt by software to write to this register is ignored. The register format is shown below. 7 Res. 6 5 4 3 2 1 0
The Transmit In Progress bit indicates when the UART is transmitting. The hardware sets this bit when the UART is transmitting data and clears the bit at the end of the last frame bit. 0 - UART is not transmitting. 1 - UART is transmitting. UART Interrupt Control Register (UICTRL)
UXMIP URB9 UBKD UERR UDOE UFE UPE
18.3.8
UPE
UFE
UDOE
UERR
UBKD
URB9
The UICTRL register is a byte-wide register that contains the receive and transmit interrupt status bits (read-only bits) The Parity Error bit indicates whether a parity and the interrupt enable bits (read/write bits). The register is error is detected within a received character. initialized to 01h at reset. The register format is shown beThis bit is automatically cleared by the hard- low. ware when the USTAT register is read. 0 - No parity error occurred. 7 6 5 4 3 2 1 0 1 - Parity error occurred. UEEI UERI UETI UEFCI UCTS UDCTS URBF UTBE The Framing Error bit indicates whether the UART fails to receive a valid stop bit at the end of a frame. This bit is automatically cleared by UTBE The Transmit Buffer Empty bit is set by hardthe hardware when the USTAT register is ware when the UART transfers data from the read. UTBUF register to the transmit shift register 0 - No framing error occurred. for transmission. It is automatically cleared by 1 - Framing error occurred. the hardware on the next write to the UTBUF The Data Overrun Error bit is set when a new register. character is received and transferred to the 0 - Transmit buffer is loaded. URBUF register before software has read the 1 - Transmit buffer is empty. previous character from the URBUF register. URBF The Receive Buffer Full bit is set by hardware This bit is automatically cleared by the hardwhen the UART has received a complete data ware when the USTAT register is read. frame and has transferred the data from the 0 - No receive overrun error occurred. receive shift register to the URBUF register. It 1 - Receive overrun error occurred. is automatically cleared by the hardware The Error Status bit indicates when a parity, when the URBUF register is read. framing, or overrun error occurs (any time that 0 - Receive buffer is empty. the UPE, UFE, or UDOE bit is set). It is auto1 - Receive buffer is loaded. matically cleared by the hardware when the UDCTS The Delta Clear To Send bit indicates whether UPE, UFE, and UDOE bits are all 0. the CTS input has changed state since the 0 - No receive error occurred. CPU last read this register. 1 - Receive error occurred. 0 - No change since last read. The Break Detect bit indicates when a line 1 - State has changed since last read. break condition occurs. This condition is deUCTS The Clear To Send bit indicates the state on tected if RXD remains low for at least ten bit the CTS input. times after a missing stop bit has been detect0 - CTS input is high. ed at the end of a frame. The hardware auto1 - CTS input is low. matically clears the UBKD bit upon read of the UEFCI The Enable Flow Control Interrupt bit controls USTAT register, but only if the break condition whether a flow control interrupt is generated on RXD no longer exists. If reading the USTAT when the UDCTS bit changes from clear to register does not clear the UBKD bit because set. the break is still actively driven on the line, the 0 - Flow control interrupt disabled. hardware clears the bit as soon as the break 1 - Flow control interrupt enabled. condition no longer exists (when the RXD inUETI The Enable Transmitter Interrupt bit, when put returns to a high level). set, enables generation of an interrupt when 0 - No break condition occurred. the hardware sets the UTBE bit. 1 - Break condition occurred. 0 - Transmit buffer empty interrupt disabled. The Received 9th Data Bit holds the ninth 1 - Transmit buffer empty interrupt enabled. data bit, when the UART is configured to opUERI The Enable Receiver Interrupt bit, when set, erate in the 9-bit data format. enables generation of an interrupt when the hardware sets the URBF bit. 0 - Receive buffer full interrupt disabled. 1 - Receive buffer full interrupt enabled.
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UEEI
The Enable Receive Error Interrupt bit, when set, enables generation of an interrupt when the hardware sets the UERR bit in the USTAT register. 0 - Receive error interrupt disabled. 1 - Receive error interrupt enabled. UART Oversample Rate Register (UOVR)
18.3.11 UART Sample Position Register (USPOS) The USPOS register is a byte-wide, read/write register that specifies the sample position when the USMD bit in the UMDSL2 register is set. At reset, the USPOS register is initialized to 06h. The register format is shown below. 7 Reserved 4 3 USAMP 0
18.3.9
The UOVR register is a byte-wide, read/write register that specifies the oversample rate. At reset, the UOVR register is cleared. The register format is shown below. USAMP 7 Reserved 4 3 UOVSR 0
UOVSR
The Oversampling Rate field specifies the oversampling rate, as given in the following table. UOVSR3:0 0000-0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Oversampling Rate 16 7 8 9 10 11 12 13 14 15
The Sample Position field specifies the oversample clock period at which to take the first of three samples for sensing the value of data bits. The clocks are numbered starting at 0 and may range up to 15 for 16x oversampling. The maximum value for this field is (oversampling rate - 3). The table below shows the clock period at which each of the three samples is taken, when automatic sampling is enabled (UMDSL2.USMD = 0). Sample Position Oversampling Rate 1 7 8 9 10 11 12 13 14 15 16 2 2 3 3 4 4 5 5 6 6 2 3 3 4 4 5 5 6 6 7 7 3 4 4 5 5 6 6 7 7 8 8
18.3.10 UART Mode Select Register 2 (UMDSL2) The UMDSL2 register is a byte-wide, read/write register that controls the sample mode used to recover asynchronous data. At reset, the UOVR register is cleared. The register format is shown below. 7 Reserved 1 0 USMD
The USAMP field may be used to override the automatic selection, to choose any other clock period at which to start taking the three samples.
USMD
The USMD bit controls the sample mode for asynchronous transmission. 0 - UART determines the sample position automatically. 1 - The USPOS register determines the sample position.
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18.4
BAUD RATE CALCULATIONS
The UART baud rate is determined by the System Clock frequency and the values in the UOVR, UPSR, and UBAUD registers. Unless the System Clock is an exact multiple of the baud rate, there will be a small amount of error in the resulting baud rate. The equation to calculate the baud rate is: SYS_CLK BR = ----------------------------(O x N x P) where BR is the baud rate, SYS_CLK is the System Clock, O is the oversample rate, N is the the baud rate divisor + 1, and P is the prescaler divisor selected by the UPSR register. Assuming a System Clock of 5 MHz, a desired baud rate of 9600, and an oversample rate of 16, the N x P term according to the equation above is: ( 5 x10 ) N x P = ------------------------------ = 32.552 ( 16 x 9600 )
6
The N x P term is then divided by each Prescaler Factor from Table 41 to obtain a value closest to an integer. The factor for this example is 6.5. N = 32.552 = 5.008 (N = 5) ----------------6.5 The baud rate register is programmed with a baud rate divisor of 4 (N = baud rate divisor + 1). This produces a baud clock of: ( 5 x10 ) BR = ----------------------------------- = 9615.385 ( 16 x 5 x 6.5 ) %error = ( 9615.385 - 9600 ) = 0.16 -----------------------------------------------9600 Note that the percent error is much lower than would be possible without the non-integer prescaler factor. Error greater than 3% is marginal and may result in unreliable operation. Refer to Table 43 below for more examples.
6
Table 43 Baud Rate Programming Baud Rate 300 600 1200 1800 2000 2400 3600 4800 7200 9600 14400 19200 38400 56000 115200 128000 230400 345600 460800 576000 691200 806400 921600 1105920 1382400 1536000 www.national.com SYS_CLK = 48 MHz O 16 16 16 7 16 16 8 16 12 16 11 10 10 7 7 15 13 9 13 8 10 7 13 11 10 9 N 2000 2000 1250 401 1500 1250 1111 625 101 125 202 250 125 49 17 25 16 1 8 7 7 1 4 4 1 1 P 5.0 2.5 2.0 9.5 1.0 1.0 1.5 1.0 5.5 2.5 1.5 1.0 1.0 2.5 3.5 1.0 1.0 %err 0.00 0.00 0.00 0.00 0.00 0.00 0.01 0.00 0.01 0.00 0.01 0.00 0.00 0.04 0.04 0.00 0.16 SYS_CLK = 24 MHz O 16 16 16 8 16 16 12 16 11 10 11 10 10 13 13 15 13 10 13 12 10 15 13 11 7 8 N 2000 1250 1250 1111 750 625 101 125 303 250 101 125 25 33 16 5 8 7 4 1 1 2 2 2 1 2 P 2.5 2.0 1.0 1.5 1.0 1.0 5.5 2.5 1.0 1.0 1.5 1.0 2.5 1.0 1.0 2.5 1.0 1.0 1.0 3.5 3.5 1.0 1.0 1.0 2.5 1.0 %err 0.00 0.00 0.00 0.01 0.00 0.00 0.01 0.00 0.01 0.00 0.01 0.00 0.00 0.10 0.16 0.00 0.16 0.79 0.16 0.79 0.79 0.79 0.16 1.36 0.79 2.34 SYS_CLK = 12 MHz O 16 16 16 12 16 16 11 10 11 10 14 10 16 13 13 11 13 10 13 14 7 10 13 N 1250 1250 625 101 250 125 202 250 101 125 17 25 13 11 8 1 4 1 2 1 1 1 1 P 2.0 1.0 1.0 5.5 1.5 2.5 1.5 1.0 1.5 1.0 3.5 2.5 1.5 1.5 1.0 8.5 1.0 3.5 1.0 1.5 2.5 1.5 1.0 %err 0.00 0.00 0.00 0.01 0.00 0.00 0.01 0.00 0.01 0.00 0.04 0.00 0.16 0.10 0.16 0.27 0.16 0.79 0.16 0.79 0.79 0.79 0.16 9 1 1.0 0.47 11 7 2 1 1.0 2.5 1.36 0.79 SYS_CLK = 10 MHz O 13 13 13 12 16 9 11 7 10 7 14 16 8 7 7 12 11 N 1282 1282 641 463 125 463 101 119 139 149 33 13 13 17 5 1 4 P 2.0 1.0 1.0 1.0 2.5 1.0 2.5 2.5 1.0 1.0 1.5 2.5 2.5 1.5 2.5 6.5 1.0 %err 0.00 0.00 0.00 0.01 0.00 0.01 0.01 0.04 0.08 0.13 0.21 0.16 0.16 0.04 0.79 0.16 1.36
15.5 0.44 1.0 1.5 1.0 8.5 1.0 1.0 3.5 3.5 0.16 0.79 0.79 0.04 0.16 1.36 0.79 0.79
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Table 44 Baud Rate Programming Baud Rate 300 600 1200 1800 2000 2400 3600 4800 7200 9600 14400 19200 38400 56000 115200 128000 230400 345600 460800 576000 Baud Rate 300 600 1200 1800 2000 2400 3600 4800 7200 9600 14400 19200 38400 56000 115200 128000 230400 SYS_CLK = 8 MHz O 7 12 12 8 16 11 11 11 11 14 15 7 16 13 10 9 10 15 7 7 N 401 1111 101 101 250 303 202 101 101 17 37 17 13 11 7 7 1 1 1 2 P 9.5 1.0 5.5 5.5 1.0 1.0 1.0 1.5 1.0 3.5 1.0 3.5 1.0 1.0 1.0 1.0 3.5 1.5 2.5 1.0 %err 0.00 0.01 0.01 0.01 0.00 0.01 0.01 0.01 0.01 0.04 0.10 0.04 0.16 0.10 0.79 0.79 0.79 2.88 0.79 0.79 SYS_CLK = 6 MHz O 16 16 16 11 16 10 11 10 14 10 7 16 8 9 13 16 13 7 13 7 N 1250 625 125 303 125 250 101 125 17 25 17 13 13 12 4 3 2 1 1 1 P 1.0 1.0 2.5 1.0 1.5 1.0 1.5 1.0 3.5 2.5 3.5 1.5 1.5 1.0 1.0 1.0 1.0 2.5 1.0 1.5 %err 0.00 0.00 0.00 0.01 0.00 0.00 0.01 0.00 0.04 0.00 0.04 0.16 0.16 0.79 0.16 2.34 0.16 0.79 0.16 0.79 SYS_CLK = 1 MHz O 11 11 14 15 10 7 9 16 9 16 10 8 13 9 N 202 101 17 37 50 17 31 13 1 1 7 1 2 2 P 1.5 1.5 3.5 1.0 1.0 3.5 1.0 1.0 %err 0.01 0.01 0.04 0.10 0.00 0.04 0.44 0.16 SYS_CLK = 500 kHz O 11 14 7 9 10 16 9 16 10 8 10 13 13 N 101 17 17 31 25 13 1 1 7 1 1 2 1 P 1.5 3.5 3.5 1.0 1.0 1.0 %err 0.01 0.04 0.04 0.44 0.00 0.16 SYS_CLK = 5 MHz O 11 11 10 11 10 7 10 7 14 16 7 8 13 15 11 13 11 N 202 101 119 101 250 119 139 149 33 13 33 13 10 6 4 3 2 P 7.5 7.5 3.5 2.5 1.0 2.5 1.0 1.0 1.5 2.5 1.5 2.5 1.0 1.0 1.0 1.0 1.0 %err 0.01 0.01 0.04 0.01 0.00 0.04 0.08 0.13 0.21 0.16 0.21 0.16 0.16 0.79 1.36 0.16 1.36 SYS_CLK = 4 MHz O 12 12 11 11 16 11 11 14 15 7 9 16 16 13 10 9 7 N 202 101 202 202 125 101 101 17 37 17 31 13 1 1 1 1 1 P 5.5 5.5 1.5 1.0 1.0 1.5 1.0 3.5 1.0 3.5 1.0 1.0 6.5 5.5 3.5 3.5 2.5 %err 0.01 0.01 0.01 0.01 0.00 0.01 0.01 0.04 0.10 0.04 0.44 0.16 0.16 0.10 0.79 0.79 0.79
SYS_CLK = 3 MHz O 16 16 10 11 15 10 14 10 7 16 13 8 13 9 13 16 13 N 250 125 250 101 100 125 17 25 17 13 16 13 6 6 2 1 1 P 2.5 2.5 1.0 1.5 1.0 1.0 3.5 2.5 3.5 1.5 1.0 1.5 1.0 1.0 1.0 1.5 1.0 %err 0.00 0.00 0.00 0.01 0.00 0.00 0.04 0.00 0.04 0.16 0.16 0.16 0.16 0.79 0.16 2.34 0.16
SYS_CLK = 2 MHz O 12 11 11 11 16 14 15 7 9 16 9 16 8 9 7 8 N 101 202 101 101 25 17 37 17 31 13 1 1 1 4 1 2 P 5.5 1.5 1.5 1.0 2.5 3.5 1.0 3.5 1.0 1.0 %err 0.01 0.01 0.01 0.01 0.00 0.04 0.10 0.04 0.44 0.16
15.5 0.44 6.5 1.0 6.5 3.5 1.0 1.0 0.16 0.79 0.16 0.79 0.16 0.16
15.5 0.44 6.5 1.0 6.5 1.0 1.0 0.16 0.79 0.16 0.16 0.79
15.5 0.44 6.5 6.5 1.0 2.5 1.0 0.16 0.16 0.79 0.79 2.34
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19.0 Microwire/SPI Interface
Microwire/Plus is a synchronous serial communications protocol, originally implemented in National Semiconductor's COP8(R) and HPC families of microcontrollers to minimize the number of connections, and therefore the cost, of communicating with peripherals. The CP3UB17 has an enhanced Microwire/SPI interface module (MWSPI) that can communicate with all peripherals that conform to Microwire or Serial Peripheral Interface (SPI) specifications. This enhanced Microwire interface is capable of operating as either a master or slave and in 8- or 16-bit mode. Figure 31 shows a typical enhanced Microwire interface application.
MWCS
5
MWCS
CS 8-Bit A/D I/O Lines Master DO SK DI DO
CS 1K Bit EEPROM
CS LCD Display Driver DI SK DI
CS VF Display Driver Slave SK DI
I/O Lines
SK
MDIDO MDODI MSK
MDIDO MDODI MSK DS067
Figure 31.
Microwire Interface The three-wire system includes: the serial data in signal (MDIDO for master mode, MDODI for slave mode), the serial data out signal (MDODI for master mode, MDIDO for slave mode), and the serial clock (MSK). In slave mode, an optional fourth signal (MWCS) may be used to enable the slave transmit. At any given time, only one slave can respond to the master. Each slave device has its own chip select signal (MWCS) for this purpose. Figure 32 shows a block diagram of the enhanced Microwire serial interface in the device.
The enhanced Microwire interface module includes the following features: Programmable operation as a Master or Slave Programmable shift-clock frequency (master only) Programmable 8- or 16-bit mode of operation 8- or 16-bit serial I/O data shift register Two modes of clocking data Serial clock can be low or high when idle 16-bit read buffer Busy bit, Read Buffer Full bit, and Overrun bit for polling and as interrupt sources Supports multiple masters Maximum bit rate of 10M bits/second (master mode) 5M bits/second (slave mode) at 20 MHz System Clock Supports very low-end slaves with the Slave Ready output Echo back enable/disable (Slave only)
19.1
MICROWIRE OPERATION
The Microwire interface allows several devices to be connected on one three-wire system. At any given time, one of these devices operates as the master while all other devices operate as slaves. The Microwire interface allows the device to operate either as a master or slave transferring 8- or 16bits of data. The master device supplies the synchronous clock (MSK) for the serial interface and initiates the data transfer. The slave devices respond by sending (or receiving) the requested data. Each slave device uses the master's clock for serially shifting data out (or in), while the master shifts the data in (or out).
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Interrupt Request
Control + Status
MWCS
Write Data
16-BIt Read Buffer
Write Data
8
8 MWDAT
16-BIt Shift Register
Data Out
Slave Master MDODI
Data In
Slave Master MDIDO
MSK
MSK
System Clock
Clock Prescaler + Select Master DS068
Figure 32. 19.1.1 Shifting
Microwire Block Diagram The "Receive Buffer Full" (RBF) bit indicates if the MWDAT register holds valid data. The OVR bit indicates that an overrun condition has occurred. 19.1.3 Writing
The Microwire interface is a full duplex transmitter/receiver. A 16-bit shifter, which can be split into a low and high byte, is used for both transmitting and receiving. In 8-bit mode, only the lower 8-bits are used to transfer data. The transmitted data is shifted out through MDODI pin (master mode) or MDIDO pin (slave mode), starting with the most significant bit. At the same time, the received data is shifted in through MDIDO pin (master mode) or MDODI pin (slave mode), also starting with the most significant bit first. The shift in and shift out are controlled by the MSK clock. In each clock cycle of MSK, one bit of data is transmitted/received. The 16-bit shifter is accessible as the MWDAT register. Reading the MWDAT register returns the value in the read buffer. Writing to the MWDAT register updates the 16bit shifter. 19.1.2 Reading
The "Microwire Busy" (BSY) bit indicates whether the MWDAT register can be written. All write operations to the MWDAT register update the shifter while the data contained in the read buffer is not affected. Undefined results will occur if the MWDAT register is written to while the BSY bit is set. 19.1.4 Clocking Modes
Two clocking modes are supported: the normal mode and the alternate mode. In the normal mode, the output data, which is transmitted on the MDODI pin (master mode) or the MDIDO pin (slave mode), is clocked out on the falling edge of the shift clock MSK. The input data, which is received via the MDIDO pin (master mode) or the MDODI pin (slave mode), is sampled on the rising edge of MSK.
The enhanced Microwire interface implements a double buffer on read. As illustrated in Figure 32, the double read buffer consists of the 16-bit shifter and a buffer, called the read buffer.
In the alternate mode, the output data is shifted out on the rising edge of MSK on the MDODI pin (master mode) or MDIDO pin (slave mode). The input data, which is received The 16-bit shifter loads the read buffer with new data when via MDIDO pin (master mode) or MDODI pin (slave mode), the data transfer sequence is completed and previous data is sampled on the falling edge of MSK. in the read buffer has been read. In master mode, an Overrun error occurs when the read buffer is full, the 16-bit shifter The clocking modes are selected with the MSKM bit. The SCIDL bit allows selection of the value of MSK when it is idle is full and a new data transfer sequence starts. (when there is no data being transferred). Various MSK When 8-bit mode is selected, the lower byte of the shift regclock frequencies can be programmed via the MCDV bits. ister is loaded into the lower byte of the read buffer and the Figures 27, 28, 29, and 30 show the data transfer timing for read buffer's higher byte remains unchanged.
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the normal and the alternate modes with the SCIDL bit equal to 0 and equal to 1. Note that when data is shifted out on MDODI (master mode) or MDIDO (slave mode) on the leading edge of the MSK clock, bit 14 (16-bit mode) is shifted out on the second leading edge of the MSK clock. When data are shifted out on MDODI (master mode) or MDIDO (slave mode) on the trailing edge of MSK, bit 14 (16-bit mode) is shifted out on the first trailing edge of MSK.
19.2
MASTER MODE
In Master mode, the MSK pin is an output for the shift clock, MSK. When data is written to the (MWnDAT register), eight or sixteen MSK clocks, depending on the mode selected, are generated to shift the 8 or 16 bits of data and then MSK goes idle again. The MSK idle state can be either high or low, depending on the SCIDL bit.
End of Transfer MSK Shift Out Bit 0 (LSB)
Data Out
MSB
MSB - 1
MSB - 2
Bit 1
Sample Point Data In MSB MSB - 1 MSB - 2 Bit 1 Bit 0 (LSB) DS069
Figure 33.
Normal Mode (SCIDL = 0)
End of Transfer MSK Shift Out Bit 0 (LSB)
Data Out
MSB Sample Point
MSB - 1
MSB - 2
Bit 1
Data In
MSB
MSB - 1
MSB - 2
Bit 1
Bit 0 (LSB)
DS070
Figure 34.
Normal Mode (SCIDL = 1)
End of Transfer MSK Shift Out
Data Out
MSB
MSB - 1
MSB - 2
Bit 1
Bit 0 (LSB)
Sample Point Data In MSB MSB - 1 MSB - 2 Bit 1 Bit 0 (LSB)
DS071
Figure 35. Alternate Mode (SCIDL = 0)
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End of Transfer MSK Shift Out
Data Out
MSB
MSB - 1
MSB - 2
Bit 1
Bit 0 (LSB)
Sample Point Data In MSB MSB - 1 MSB - 2 Bit 1 Bit 0 (LSB)
DS072
Figure 36. Alternate Mode (SCIDL = 1)
19.3
SLAVE MODE
In Slave mode, the MSK pin is an input for the shift clock MSK. MDIDO is placed in TRI-STATE mode when MWCS is inactive. Data transfer is enabled when MWCS is active. The slave starts driving MDIDO when MWCS is activated. The most significant bit (lower byte in 8-bit mode or upper byte in 16-bit mode) is output onto the MDIDO pin first. After eight or sixteen clocks (depending on the selected mode), the data transfer is completed.
Figure 37 illustrates the various interrupt capabilities of this module.
EIO
OVR = 1
EIR
If a new shift process starts before MWDAT was written, i.e., while MWDAT does not contain any valid data, and the "Echo Enable" (ECHO) bit is set, the data received from MDODI is transmitted on MDIDO in addition to being shifted to MWDAT. If the ECHO bit is clear, the data transmitted on MDIDO is the data held in the MWDAT register, regardless of its validity. The master may negate the MWCS signal to synchronize the bit count between the master and the slave. In the case that the slave is the only slave in the system, MWCS can be tied to VSS. 19.5
RBF = 1
MWSPI Interrupt
EIW
BSY = 0 DS073
Figure 37.
MWSPI Interrupts
MICROWIRE INTERFACE REGISTERS
19.4
INTERRUPT GENERATION
An interrupt is generated in any of the following cases: When the read buffer is full (RBF = 1) and the "Enable Interrupt for Read" bit is set (EIR = 1). Whenever the shifter is not busy, i.e. the BSY bit is clear (BSY = 0) and the "Enable Interrupt for Write" bit is set (EIW = 1). When an overrun condition occurs (OVR is set) and the "Enable Interrupt on Overrun" bit is set (MEIO = 1). This usage is restricted to master mode. In addition, MWCS is an input to the MIWU (see Section 13.0), which can be programmed to generate an edge-triggered interrupt.
Software interacts with the Microwire interface by accessing the Microwire registers. There are three such registers: Table 45 Microwire Interface Registers Name MWDAT MWCTL1 MWSTAT 19.5.1 Address FF FE60h FF FE62h FF FE64h Description Microwire Data Register Microwire Control Register Microwire Status Register
Microwire Data Register (MWDAT)
The MWDAT register is a word-wide, read/write register used to transmit and receive data through the MDODI and MDIDO pins. Figure 38 shows the hardware structure of the register.
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MWDAT Write
DIN
Shifter (Low Byte)
Shifter (High Byte)
1 DOUT 0
Read Buffer (Low Byte)
Read Buffer (High Byte)
MOD
Read DS074
Figure 38. 19.5.2 Microwire Control Register (MWCTL1)
MWDAT Register MNS The Master/Slave Select bit controls whether the CP3UB17 is a master or slave. When clear, the device operates as a slave. When set, the device operates as the master. 0 - CP3UB17 is slave. 1 - CP3UB17 is master. The Mode Select bit controls whether 8- or 16bit mode is used. When clear, the device operates in 8-bit mode. When set, the device operates in 16-bit mode. This bit must only be changed when the module is disabled or idle (MWSTAT.BSY = 0). 0 - 8-bit mode. 1 - 16-bit mode. The Echo Back bit controls whether the echo back function is enabled in slave mode. This bit must be written only when the Microwire interface is idle (MWSTAT.BSY=0). The ECHO bit is ignored in master mode. The MWDAT register is valid from the time the register has been written until the end of the transfer. In the echo back mode, MDODI is transmitted (echoed back) on MDIDO if the MWDAT register does not contain any valid data. With the echo back function disabled, the data held in the MWDAT register is transmitted on MDIDO, whether or not the data is valid. 0 - Echo back disabled. 1 - Echo back enabled. The Enable Interrupt on Overrun bit enables or disables the overrun error interrupt. When set, an interrupt is generated when the Receive Overrun Error bit (MWSTAT.OVR) is set. Otherwise, no interrupt is generated when an overrun error occurs. This bit must only be enabled in master mode. 0 - Disable overrun error interrupts. 1 - Enable overrun error interrupts.
The MWCTL1 register is a word-wide, read/write register used to control the Microwire module. To avoid clock glitches, the MWEN bit must be clear while changing the states of any other bits in the register. At reset, all non-reserved bits are cleared. The register format is shown below. 7 SCM 6 EIW 5 EIR 4 EIO 3 2 1 0
MOD
ECHO MOD
MNS MWEN
15 SCIDV
9
8 SCIDL ECHO
MWEN
The Microwire Enable bit controls whether the Microwire interface module is enabled. 0 - Microwire module disabled. 1 - Microwire module enabled. Clearing this bit disables the module, clears the status bits in the Microwire status register (the BSY, RBF, and OVR bits in MWSTAT), and places the Microwire interface pins in the states described below. Pin MSK MWCS MDIDO MDODI State When Disabled Master - SCIDL Bit Slave - Input Input Master - Input Slave - TRI-STATE Master - Known value Slave - Input EIO
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EIR
EIW
SCM
SCIDL
SCIDV
The Enable Interrupt for Read bit controls whether an interrupt is generated when the read buffer becomes full. When set, an interrupt is generated when the Read Buffer Full bit (MWSTAT.RBF) is set. Otherwise, no interrupt is generated when the read buffer is full. 0 - No read buffer full interrupt. 1 - Interrupt when read buffer becomes full. The Enable Interrupt for Write bit controls whether an interrupt is generated when the Busy bit (MWSTAT.BSY) is cleared, which indicates that a data transfer sequence has been completed and the read buffer is ready to receive the new data. Otherwise, no interrupt is generated when the Busy bit is cleared. 0 - No interrupt on data transfer complete. 1 - Interrupt on data transfer complete. The Shift Clock Mode bit selects between the normal clocking mode and the alternate clocking mode. In the normal mode, the output data is clocked out on the falling edge of MSK and the input data is sampled on the rising edge of MSK. In the alternate mode, the output data is clocked out on the rising edge of MSK and the input data is sampled on the falling edge of MSK. 0 - Normal clocking mode. 1 - Alternate clocking mode. The Shift Clock Idle bit controls the value of the MSK output when the Microwire module is idle. This bit must be changed only when the Microwire module is disabled (MWEN = 0) or when no bus transaction is in progress (MWSTAT.BSY = 0). 0 - MSK is low when idle. 1 - MSK is high when idle The Shift Clock Divider Value field specifies the divisor used for generating the MSK shift clock from the System Clock. The divisor is 2 x (MCDV[6:0] + 1). This allows selection of a division ratio from 2 to 256. This field is ignored in slave mode (MWCTL1.MMNS=0).
19.5.3
Microwire Status Register (MWSTAT)
The MWSTAT register is a word-wide, read-only register that shows the current status of the Microwire interface module. At reset, all non-reserved bits are clear. The register format is shown below. 15 Reserved 3 2 OVR 1 RBF 0 BSY
BSY
RBF
OVR
The Busy bit, when set, indicates that the Microwire shifter is busy. In master mode, the BSY bit is set when the MWDAT register is written. In slave mode, the bit is set on the first leading edge of MSK when MWCS is asserted or when the MWDAT register is written, whichever occurs first. In both master and slave modes, this bit is cleared when the Microwire data transfer sequence is completed and the read buffer is ready to receive the new data; in other words, when the previous data held in the read buffer has already been read. If the previous data in the read buffer has not been read and new data has been received into the shift register, the BSY bit will not be cleared, as the transfer could not be completed because the contents of the shift register could not be transferred into the read buffer. 0 - Microwire shifter is not busy. 1 - Microwire shifter is busy. The Read Buffer Full bit, when set, indicates that the Microwire read buffer is full and ready to be read by software. It is set when the shifter loads the read buffer, which occurs upon completion of a transfer sequence if the read buffer is empty. The RBF bit is updated when the MWDAT register is read. At that time, the RBF bit is cleared if the shifter does not contain any new data (in other words, the shifter is not receiving data or has not yet received a full byte of data). The RBF bit remains set if the shifter already holds new data at the time that MWDAT is read. In that case, MWDAT is immediately reloaded with the new data and is ready to be read by software. 0 - Microwire read buffer is not full. 1 - Microwire read buffer is full. The Receive Overrun Error bit, when set in master mode, indicates that a receive overrun error has occurred. This error occurs when the read buffer is full, the 8-bit shifter is full, and a new data transfer sequence starts. This bit is undefined in slave mode. The OVR bit, once set, remains set until cleared by software. Software clears this bit by writing a 1 to its bit position. Writing a 0 to this bit position has no effect. No other bits in the MWSTAT register are affected by a write operation to the register. 0 - No receive overrun error has occurred. 1 - Receive overrun error has occurred. www.national.com
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20.0 ACCESS.bus Interface
The ACCESS.bus interface module (ACB) is a two-wire se- mand/control information and data using the synchronous rial interface compatible with the ACCESS.bus physical lay- serial clock. er. It permits easy interfacing to a wide range of low-cost memories and I/O devices, including: EEPROMs, SRAMs, timers, A/D converters, D/A converters, clock chips, and peSDA ripheral drivers. It is compatible with Intel's SMBus and Philips' I2C bus. The module can be configured as a bus master or slave, and can maintain bidirectional communications SCL with both multiple master and slave devices. This section presents an overview of the bus protocol, and its implementation by the module. ACCESS.bus master and slave Supports polling and interrupt-controlled operation Generate a wake-up signal on detection of a Start Condition, while in power-down mode Optional internal pull-up on SDA and SCL pins
Data Line Stable: Data Valid Change of Data Allowed DS075
Figure 39. Bit Transfer
Each data transaction is composed of a Start Condition, a number of byte transfers (programmed by software), and a Stop Condition to terminate the transaction. Each byte is 20.1 ACB PROTOCOL OVERVIEW transferred with the most significant bit first, and after each The ACCESS.bus protocol uses a two-wire interface for bi- byte, an Acknowledge signal must follow. directional communication between the devices connected At each clock cycle, the slave can stall the master while it to the bus. The two interface signals are the Serial Data Line handles the previous data, or prepares new data. This can (SDA) and the Serial Clock Line (SCL). These signals be performed for each bit transferred or on a byte boundary should be connected to the positive supply, through pull-up by the slave holding SCL low to extend the clock-low period. resistors, to keep the signals high when the bus is idle. Typically, slaves extend the first clock cycle of a transfer if a The ACCESS.bus protocol supports multiple master and slave transmitters and receivers. Each bus device has a unique address and can operate as a transmitter or a receiver (though some peripherals are only receivers). During data transactions, the master device initiates the transaction, generates the clock signal, and terminates the transaction. For example, when the ACB initiates a data transaction with an ACCESS.bus peripheral, the ACB becomes the master. When the peripheral responds and transmits data to the ACB, their master/slave (data transaction initiator and clock generator) relationship is unchanged, even though their transmitter/receiver functions are reversed. 20.1.1 Data Transactions
SDA
byte read has not yet been stored, or if the next byte to be transmitted is not yet ready. Some microcontrollers with limited hardware support for ACCESS.bus extend the access after each bit, to allow software time to handle this bit. Start and Stop The ACCESS.bus master generates Start and Stop Conditions (control codes). After a Start Condition is generated, the bus is considered busy and it retains this status until a certain time after a Stop Condition is generated. A high-tolow transition of the data line (SDA) while the clock (SCL) is high indicates a Start Condition. A low-to-high transition of the SDA line while the SCL is high indicates a Stop Condition (Figure 40).
One data bit is transferred during each clock period. Data is sampled during the high phase of the serial clock (SCL). Consequently, throughout the clock high phase, the data must remain stable (see Figure 39). Any change on the SDA signal during the high phase of the SCL clock and in the middle of a transaction aborts the current transaction. New data must be driven during the low phase of the SCL clock. This protocol permits a single data line to transfer both com-
SCL S Start Condition P Stop Condition DS076
Figure 40. Start and Stop Conditions In addition to the first Start Condition, a repeated Start Condition can be generated in the middle of a transaction. This allows another device to be accessed, or a change in the direction of the data transfer.
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Acknowledge Cycle The Acknowledge Cycle consists of two signals: the acknowledge clock pulse the master sends with each byte transferred, and the acknowledge signal sent by the receiving device (Figure 41).
Acknowledgment Signal from Receiver SDA MSB
Addressing Transfer Formats Each device on the bus has a unique address. Before any data is transmitted, the master transmits the address of the slave being addressed. The slave device should send an acknowledge signal on the SDA signal, once it recognizes its address. The address is the first seven bits after a Start Condition. The direction of the data transfer (R/W) depends on the bit sent after the address (the eighth bit). A low-to-high transition during a SCL high period indicates the Stop Condition, and ends the transaction (Figure 43).
9 ACK P Stop Condition SDA DS077 SCL S 1-7 Address 8 9 1-7 Data 8 9 ACK 1-7 Data 8 9 P R/W ACK ACK
SCL S Start Condition
1
2
3-6
7
8
9 ACK
1
2
3-8
Byte Complete Interrupt Within Receiver
Clock Line Held Low by Receiver While Interrupt is Serviced
Figure 41.
ACCESS.bus Data Transaction
Start Stop The master generates the acknowledge clock pulse on the Condition Condition ninth clock pulse of the byte transfer. The transmitter releasDS079 es the SDA line (permits it to go high) to allow the receiver to send the acknowledge signal. The receiver must pull down the SDA line during the acknowledge clock pulse, which signals the correct reception of the last data byte, and Figure 43. A Complete ACCESS.bus Data Transaction its readiness to receive the next byte. Figure 42 illustrates When the address is sent, each device in the system comthe acknowledge cycle. pares this address with its own. If there is a match, the device considers itself addressed and sends an acknowledge Data Output signal. Depending upon the state of the R/W bit (1 = read, by Transmitter Transmitter Stays Off 0 = write), the device acts as a transmitter or a receiver. the Bus During the Acknowledgment Clock Data Output by Receiver Acknowledgment Signal from Receiver SCL S Start Condition 1 2 3-6 7 8 9
DS078
The ACCESS.bus protocol allows sending a general call address to all slaves connected to the bus. The first byte sent specifies the general call address (00h) and the second byte specifies the meaning of the general call (for example, "Write slave address by software only"). Those slaves that require the data acknowledge the call and become slave receivers; the other slaves ignore the call. Arbitration on the Bus Arbitration is required when multiple master devices attempt to gain control of the bus simultaneously. Control of the bus is initially determined according to address bits and clock cycle. If the masters are trying to address the same bus device, data comparisons determine the outcome of this arbitration. In master mode, the device immediately aborts a transaction if the value sampled on the SDA lines differs from the value driven by the device. (Exceptions to this rule are SDA while receiving data; in these cases the lines may be driven low by the slave without causing an abort.) The SCL signal is monitored for clock synchronization and allows the slave to stall the bus. The actual clock period will be the one set by the master with the longest clock period or by the slave stall period. The clock high period is determined by the master with the shortest clock high period. When an abort occurs during the address transmission, the master that identifies the conflict should give up the bus, switch to slave mode, and continue to sample SDA to see if it is being addressed by the winning master on the ACCESS.bus.
Figure 42. ACCESS.bus Acknowledge Cycle The master generates an acknowledge clock pulse after each byte transfer. The receiver sends an acknowledge signal after every byte received. There are two exceptions to the "acknowledge after every byte" rule. When the master is the receiver, it must indicate to the transmitter an end-of-data condition by not-acknowledging ("negative acknowledge") the last byte clocked out of the slave. This "negative acknowledge" still includes the acknowledge clock pulse (generated by the master), but the SDA line is not pulled down. When the receiver is full, otherwise occupied, or a problem has occurred, it sends a negative acknowledge to indicate that it cannot accept additional data bytes.
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20.2
ACB FUNCTIONAL DESCRIPTION
The ACB module provides the physical layer for an ACCESS.bus compliant serial interface. The module is configurable as either a master or slave device. As a slave, the ACB module may issue a request to become the bus master. 20.2.1 Master Mode
An ACCESS.bus transaction starts with a master device requesting bus mastership. It sends a Start Condition, followed by the address of the device it wants to access. If this transaction is successfully completed, software can assume that the device has become the bus master. For a device to become the bus master, software should perform the following steps: 1. Set the ACBCTL1.START bit, and configure the ACBCTL1.INTEN bit to the desired operation mode (Polling or Interrupt). This causes the ACB to issue a Start Condition on the ACCESS.bus, as soon as the ACCESS.bus is free (ACBCST.BB=0). It then stalls the bus by holding SCL low. 2. If a bus conflict is detected, (i.e., some other device pulls down the SCL signal before this device does), the ACBST.BER bit is set. 3. If there is no bus conflict, the ACBST.MASTER and ACBST.SDAST bits are set. 4. If the ACBCTL1.INTEN bit is set, and either the ACBST.BER bit or the ACBST.SDAST bit is set, an interrupt is sent to the ICU. Sending the Address Byte
4. If the requested direction is transmit, and the start transaction was completed successfully (i.e., neither the ACBST.NEGACK nor ACBST.BER bit is set, and no other master has accessed the device), the ACBST.SDAST bit is set to indicate that the module is waiting for service. 5. If the requested direction is receive, the start transaction was completed successfully, and the ACBCTL1.STASTRE bit is clear, the module starts receiving the first byte automatically. 6. Check that both the ACBST.BER and ACBST.NEGACK bits are clear. If the ACBCTL1.INTEN bit is set, an interrupt is generated when either the ACBST.BER or ACBST.NEGACK bit is set. Master Transmit After becoming the bus master, the device can start transmitting data on the ACCESS.bus. To transmit a byte, software must: 1. Check that the BER and NEGACK bits in the ACBST register are clear and the ACBST.SDAST bit is set. Also, if the ACBCTL1.STASTRE bit is set, check that the ACBST.STASTR bit is clear. 2. Write the data byte to be transmitted to the ACBSDA register. When the slave responds with a negative acknowledge, the ACBST.NEGACK bit is set and the ACBST.SDAST bit remains cleared. In this case, if the ACBCTL1.INTEN bit is set, an interrupt is sent to the core. Master Receive
After becoming the bus master, the device can start receivOnce this device is the active master of the ACCESS.bus ing data on the ACCESS.bus. To receive a byte, software (ACBST.MASTER = 1), it can send the address on the bus. must: The address should not be this device's own address as specified in the ACBADDR.ADDR field if the ACBAD- 1. Check that the ACBST.SDAST bit is set and the ACBST.BER bit is clear. Also, if the ACBCTL1.STASTRE bit DR.SAEN bit is set or the ACBADDR2.ADDR field if the is set, check that the ACBST.STASTR bit is clear. ACBADDR2.SAEN bit is set, nor should it be the global call 2. Set the ACBCTL1.ACK bit, if the next byte is the last address if the ACBST.GCMTCH bit is set. byte that should be read. This causes a negative acTo send the address byte use the following sequence: knowledge to be sent. 1. Configure the ACBCTL1.INTEN bit according to the de- 3. Read the data byte from the ACBSDA register. sired operation mode. For a receive transaction where software wants only one byte of data, it should set the Master Stop ACBCTL1.ACK bit. If only an address needs to be sent, A Stop Condition may be issued only when this device is the set the ACBCTL1.STASTRE bit. active bus master (ACBST.MASTRER = 1). To end a trans2. Write the address byte (7-bit target device address), action, set the ACBCTL1.STOP bit before clearing the curand the direction bit, to the ACBSDA register. This rent stall bit (i.e., the ACBST.SDAST, ACBST.NEGACK, or causes the module to generate a transaction. At the ACBST.STASTR bit). This causes the module to send a end of this transaction, the acknowledge bit received is Stop Condition immediately, and clear the ACBCTL1.STOP copied to the ACBST.NEGACK bit. During the transac- bit. tion, the SDA and SCL signals are continuously checked for conflict with other devices. If a conflict is Master Bus Stall detected, the transaction is aborted, the ACBST.BER bit is set, and the ACBST.MASTER bit is cleared. 3. If the ACBCTL1.STASTRE bit is set, and the transaction was successfully completed (i.e., both the ACBST.BER and ACBST.NEGACK bits are cleared), the ACBST.STASTR bit is set. In this case, the ACB stalls any further ACCESS.bus operations (i.e., holds SCL low). If the ACBCTL1.INTE bit is set, it also sends an interrupt to the ICU. www.national.com The ACB module can stall the ACCESS.bus between transfers while waiting for the core's response. The ACCESS.bus is stalled by holding the SCL signal low after the acknowledge cycle. Note that this is interpreted as the beginning of the following bus operation. Software must make sure that the next operation is prepared before the bit that causes the bus stall is cleared.
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The bits that can cause a stall in master mode are:
20.2.2
Slave Mode
Negative acknowledge after sending a byte A slave device waits in Idle mode for a master to initiate a (ACBSTNEGACK = 1). bus transaction. Whenever the ACB is enabled, and it is not ACBST.SDAST bit is set. acting as a master (i.e., ACBST.MASTER = 0), it acts as a If the ACBCTL1.STASTRE bit is set, after a successful slave device. start (ACBST.STASTR = 1). Once a Start Condition on the bus is detected, this device checks whether the address sent by the current master Repeated Start matches either: A repeated start is performed when this device is already The ACBADDR.ADDR value if the ACBADDR.SAEN bit the bus master (ACBST.MASTER = 1). In this case, the ACis set. CESS.bus is stalled and the ACB waits for the core handling The ACBADDR2.ADDR value if the ACBADDR2.SAEN due to: negative acknowledge (ACBST.NEGACK = 1), empbit is set. ty buffer (ACBST.SDAST = 1), or a stop-after-start (ACBThe general call address if the ACBCTL1.GCM bit is set. ST.STASTR = 1). This match is checked even when the ACBST.MASTER bit For a repeated start: is set. If a bus conflict (on SDA or SCL) is detected, the 1. Set the ACBCTL1.START bit. ACBST.BER bit is set, the ACBST.MASTER bit is cleared, 2. In master receive mode, read the last data item from and this device continues to search the received message the ACBSDA register. for a match. If an address match, or a global match, is de3. Follow the address send sequence, as described in tected: "Sending the Address Byte" on page 124. 4. If the ACB was waiting for handling due to ACB- 1. This device asserts its data pin during the acknowledge cycle. ST.STASTR = 1, clear it only after writing the requested 2. The ACBCST.MATCH, ACBCST.MATCHAF (or address and direction to the ACBSDA register. ACBCST.GCMTCH if it is a global call address match, Master Error Detections or ACBCST.ARPMATCH if it is an ARP address) and ACBST.NMATCH in the ACBCST register are set. If the The ACB detects illegal Start or Stop Conditions (i.e., a ACBST.XMIT bit is set (i.e., slave transmit mode), the Start or Stop Condition within the data transfer, or the acACBST.SDAST bit is set to indicate that the buffer is knowledge cycle) and a conflict on the data lines of the ACempty. CESS.bus. If an illegal action is detected, the BER bit is set, and the MASTER mode is exited (the MASTER bit is 3. If the ACBCTL1.INTEN bit is set, an interrupt is generated if both the INTEN and NMINTE bits in the cleared). ACBCTL1 register are set. Bus Idle Error Recovery 4. Software then reads the ACBST.XMIT bit to identify the When a request to become the active bus master or a redirection requested by the master device. It clears the start operation fails, the ACBST.BER bit is set to indicate the ACBST.NMATCH bit so future byte transfers are identierror. In some cases, both this device and the other device fied as data bytes. may identify the failure and leave the bus idle. In this case, Slave Receive and Transmit the start sequence may not be completed and the ACSlave Receive and Transmit are performed after a match is CESS.bus may remain deadlocked. detected and the data transfer direction is identified. After a To recover from deadlock, use the following sequence: byte transfer, the ACB extends the acknowledge clock until 1. Clear the ACBST.BER and ACBCST.BB bits. software reads or writes the ACBSDA register. The receive 2. Wait for a time-out period to check that there is no other and transmit sequence are identical to those used in the active master on the bus (i.e., the ACBCST.BB bit re- master routine. mains clear). 3. Disable, and re-enable the ACB to put it in the non-ad- Slave Bus Stall dressed slave mode. When operating as a slave, this device stalls the AC4. At this point, some of the slaves may not identify the CESS.bus by extending the first clock cycle of a transaction bus error. To recover, the ACB becomes the bus master in the following cases: by issuing a Start Condition and sends an address -- The ACBST.SDAST bit is set. field; then issue a Stop Condition to synchronize all the -- The ACBST.NMATCH, and ACBCTL1.NMINTE bits slaves. are set. Slave Error Detections The ACB detects illegal Start and Stop Conditions on the ACCESS.bus (i.e., a Start or Stop Condition within the data transfer or the acknowledge cycle). When an illegal Start or Stop Condition is detected, the BER bit is set and the MATCH and GMATCH bits are cleared, causing the module to be an unaddressed slave.
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Power Down
20.3
ACCESS.BUS INTERFACE REGISTERS
When this device is in Power Save, Idle, or Halt mode, the The ACCESS.bus interface uses the registers listed in ACB module is not active but retains its status. If the ACB is Table 46. enabled (ACBCTL2.ENABLE = 1) on detection of a Start Table 46 ACCESS.bus Interface Registers Condition, a wake-up signal is issued to the MIWU module (see Section 13.0). Use this signal to switch this device to Name Address Description Active mode. The ACB module cannot check the address byte for a match following the start condition that caused the wake-up event for this device. The ACB responds with a negative acknowledge, and the device should resend both the Start Condition and the address after this device has had time to wake up. Check that the ACBCST.BUSY bit is inactive before entering Power Save, Idle, or Halt mode. This guarantees that the device does not acknowledge an address sent and stop responding later. 20.2.3 SDA and SCL Pins Configuration ACBSDA ACBST ACBCST ACBCTL1 ACBCTL2 ACBCTL3 FF FEC0h FF FEC2h FF FEC4h FF FEC6h FF FECAh FF FECEh ACB Serial Data Register ACB Status Register ACB Control Status Register ACB Control Register 1 ACB Control Register 2 ACB Control Register 3
The SDA and SCL pins are driven as open-drain signals. For more information, see the I/O configuration section. 20.2.4
ACB Clock Frequency Configuration ACB Own Address The ACB module permits software to set the clock frequenACBADDR1 FF FEC8h Register 1 cy used for the ACCESS.bus clock. The clock is set by the ACBCTL2.SCLFRQ field. This field determines the SCL ACB Own Address ACBADDR2 FF FECCh clock period used by this device. This clock low period may Register 2 be extended by stall periods initiated by the ACB module or by another ACCESS.bus device. In case of a conflict with 20.3.1 ACB Serial Data Register (ACBSDA) another bus master, a shorter clock high period may be forced by the other bus master until the conflict is resolved. The ACBSDA register is a byte-wide, read/write shift register used to transmit and receive data. The most significant bit is transmitted (received) first and the least significant bit is transmitted (received) last. Reading or writing to the ACBSDA register is allowed when ACBST.SDAST is set; or for repeated starts after setting the START bit. An attempt to access the register in other cases produces unpredictable results. 7 DATA 0
20.3.2
ACB Status Register (ACBST)
The ACBST register is a byte-wide, read-only register that maintains current ACB status. At reset, and when the module is disabled, ACBST is cleared. 7 6 5 4 3 2 1 0
SLVSTP SDAST BER NEGACK STASTR NMATCH MASTER XMIT
XMIT
The Direction Bit bit is set when the ACB module is currently in master/slave transmit mode. Otherwise it is cleared. 0 - Receive mode. 1 - Transmit mode.
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MASTER
NMATCH
STASTR
NEGACK
BER
The Master bit indicates that the module is currently in master mode. It is set when a request for bus mastership succeeds. It is cleared upon arbitration loss (BER is set) or the recognition of a Stop Condition. 0 - Slave mode. 1 - Master mode. The New match bit is set when the address byte following a Start Condition, or repeated starts, causes a match or a global-call match. The NMATCH bit is cleared when written with 1. Writing 0 to NMATCH is ignored. If the ACBCTL1.INTEN bit is set, an interrupt is sent when this bit is set. 0 - No match. 1 - Match or global-call match. The Stall After Start bit is set by the successful completion of an address sending (i.e., a Start Condition sent without a bus error, or negative acknowledge), if the ACBCTL1.STASTRE bit is set. This bit is ignored in slave mode. When the STASTR bit is set, it stalls the bus by pulling down the SCL line, and suspends any other action on the bus (e.g., receives first byte in master receive mode). In addition, if the ACBCTL1.INTEN bit is set, it also sends an interrupt to the ICU. Writing 1 to the STASTR bit clears it. It is also cleared when the module is disabled. Writing 0 to the STASTR bit has no effect. 0 - No stall after start condition. 1 - Stall after successful start. The Negative Acknowledge bit is set by hardware when a transmission is not acknowledged on the ninth clock. (In this case, the SDAST bit is not set.) Writing 1 to NEGACK clears it. It is also cleared when the module is disabled. Writing 0 to the NEGACK bit is ignored. 0 - No transmission not acknowledged condition. 1 - Transmission not acknowledged. The Bus Error bit is set by the hardware when a Start or Stop Condition is detected during data transfer (i.e., Start or Stop Condition during the transfer of bits 2 through 8 and acknowledge cycle), or when an arbitration problem is detected. Writing 1 to the BER bit clears it. It is also cleared when the module is disabled. Writing 0 to the BER bit is ignored. 0 - No bus error occurred. 1 - Bus error occurred.
SDAST
SLVSTP
The SDA Status bit indicates that the SDA data register is waiting for data (transmit, as master or slave) or holds data that should be read (receive, as master or slave). This bit is cleared when reading from the ACBSDA register during a receive, or when written to during a transmit. When the ACBCTL1.START bit is set, reading the ACBSDA register does not clear the SDAST bit. This enables the ACB to send a repeated start in master receive mode. 0 - ACB module is not waiting for data transfer. 1 - ACB module is waiting for data to be loaded or unloaded. The Slave Stop bit indicates that a Stop Condition was detected after a slave transfer (i.e., after a slave transfer in which MATCH or GCMATCH is set). Writing 1 to SLVSTP clears it. It is also cleared when the module is disabled. Writing 0 to SLVSTP is ignored. 0 - No stop condition after slave transfer occurred. 1 - Stop condition after slave transfer occurred. ACB Control Status Register (ACBCST)
20.3.3
The ACBCST register is a byte-wide, read/write register that maintains current ACB status. At reset and when the module is disabled, the non-reserved bits of ACBCST are cleared. 7 6 5 4 3 2 1 0
Reserved TGSCL TSDA GCMTCH MATCH BB BUSY
BUSY
The BUSY bit indicates that the ACB module is: Generating a Start Condition In Master mode (ACBST.MASTER is set) In Slave mode (ACBCST.MATCH or ACBCST.GCMTCH is set) In the period between detecting a Start and completing the reception of the address byte. After this, the ACB either becomes not busy or enters slave mode. The BUSY bit is cleared by the completion of any of the above states, and by disabling the module. BUSY is a read only bit. It must always be written with 0. 0 - ACB module is not busy. 1 - ACB module is busy.
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BB
MATCH
GCMTCH
TSDA
TGSCL
The Bus Busy bit indicates the bus is busy. It is set when the bus is active (i.e., a low level on either SDA or SCL) or by a Start Condition. It is cleared when the module is disabled, on detection of a Stop Condition, or when writing 1 to this bit. See "Usage Hints" on page 130 for a description of the use of this bit. This bit should be set when either the SDA or SCL signals are low. This is done by sampling the SDA and SCL signals continuously and setting the bit if one of them is low. The bit remains set until cleared by a STOP condition or written with 1. 0 - Bus is not busy. 1 - Bus is busy. The Address Match bit indicates in slave mode when ACBADDR.SAEN is set and the first seven bits of the address byte (the first byte transferred after a Start Condition) matches the 7-bit address in the ACBADDR register, or when ACBADDR2.SAEN is set and the first seven bits of the address byte matches the 7-bit address in the ACBADDR2 register. It is cleared by Start Condition or repeated Start and Stop Condition (including illegal Start or Stop Condition). 0 - No address match occurred. 1 - Address match occurred. The Global Call Match bit is set in slave mode when the ACBCTL1.GCMEN bit is set and the address byte (the first byte transferred after a Start Condition) is 00h. It is cleared by a Start Condition or repeated Start and Stop Condition (including illegal Start or Stop Condition). 0 - No global call match occurred. 1 - Global call match occurred. The Test SDA bit samples the state of the SDA signal. This bit can be used while recovering from an error condition in which the SDA signal is constantly pulled low by a slave that went out of sync. This bit is a read-only bit. Data written to it is ignored. The Toggle SCL bit enables toggling the SCL signal during error recovery. When the SDA signal is low, writing 1 to this bit drives the SCL signal high for one cycle. Writing 1 to TGSCL when the SDA signal is high is ignored. The bit is cleared when the clock toggle is completed. 0 - Writing 0 has no effect. 1 - Writing 1 toggles the SDA signal high for one cycle.
20.3.4
ACB Control Register 1 (ACBCTL1)
The ACBCTL1 register is a byte-wide, read/write register that configures and controls the ACB module. At reset and while the module is disabled (ACBCTL2.ENABLE = 0), the ACBCTL1 register is cleared. 7 6 5 4 3 2 1 0
STASTRE NMINTE GCMEN ACK Res. INTEN STOP START
START
STOP
The Start bit is set to generate a Start Condition on the ACCESS.bus. The START bit is cleared when the Start Condition is sent, or upon detection of a Bus Error (ACBST.BER = 1). This bit should be set only when in Master mode, or when requesting Master mode. If this device is not the active master of the bus (ACBST.MASTER = 0), setting the START bit generates a Start Condition as soon as the ACCESS.bus is free (ACBCST.BB = 0). An address send sequence should then be performed. If this device is the active master of the bus (ACBST.MASTER = 1), when the START bit is set, a write to the ACBSDA register generates a Start Condition, then the ACBSDA data is transmitted as the slave's address and the requested transfer direction. This case is a repeated Start Condition. It may be used to switch the direction of the data flow between the master and the slave, or to choose another slave device without using a Stop Condition in between. 0 - Writing 0 has no effect. 1 - Writing 1 generates a Start condition. The Stop bit in master mode generates a Stop Condition that completes or aborts the current message transfer. This bit clears itself after the the Stop condition is issued. 0 - Writing 0 has no effect. 1 - Writing 1 generates a Stop condition.
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INTEN
ACK
GCMEN
NMINTE
STASTRE
The Interrupt Enable bit controls generating ACB interrupts. When the INTEN bit is cleared ACB interrupt is disabled. When the INTEN bit is set, interrupts are enabled. 0 - ACB interrupts disabled. 1 - ACB interrupts enabled. An interrupt is generated (the interrupt signal to the ICU is high) on any of the following events: An address MATCH is detected (ACBST.NMATCH = 1) and the NMINTE bit is set. A Bus Error occurs (ACBST.BERR = 1). Negative acknowledge after sending a byte (ACBST.NEGACK = 1). An interrupt is generated on acknowledge of each transaction (same as hardware setting the ACBST.SDAST bit). If ACBCTL1.STASTRE = 1, in master mode after a successful start (ACBST.STASTR = 1). Detection of a Stop Condition while in slave receive mode (ACBST.SLVSTP = 1). The Acknowledge bit holds the value this device sends in master or slave mode during the next acknowledge cycle. Setting this bit to 1 instructs the transmitting device to stop sending data, since the receiver either does not need, or cannot receive, any more data. This bit is cleared after the first acknowledge cycle. This bit is ignored when in transmit mode. The Global Call Match Enable bit enables the match of an incoming address byte to the general call address (Start Condition followed by address byte of 00h) while the ACB is in slave mode. When cleared, the ACB does not respond to a global call. 0 - Global call matching disabled. 1 - Global call matching enabled. The New Match Interrupt Enable controls whether ACB interrupts are generated on new matches. Set the NMINTE bit to enable the interrupt on a new match (i.e., when ACBST.NMATCH is set). The interrupt is issued only if the ACBCTL1.INTEN bit is set. 0 - New match interrupts disabled. 1 - New match interrupts enabled. The Stall After Start Enable bit enables the stall after start mechanism. When enabled, the ACB is stalled after the address byte. When the STASTRE bit is clear, the ACBST.STASTR bit is always clear. 0 - No stall after start. 1 - Stall-after-start enabled.
20.3.5
ACB Control Register 2 (ACBCTL2)
The ACBCTL2 register is a byte-wide, read/write register that controls the module and selects the ACB clock rate. At reset, the ACBCTL2 register is cleared. 7 SCLFRQ6:0 1 0 ENABLE
ENABLE
SCLFRQ
The Enable bit controls the ACB module. When this bit is set, the ACB module is enabled. When the Enable bit is clear, the ACB module is disabled, the ACBCTL1, ACBST, and ACBCST registers are cleared, and the clocks are halted. 0 - ACB module disabled. 1 - ACB module enabled. The SCL Frequency field specifies the SCL period (low time and high time) in master mode. The clock low time and high time are defined as follows: tSCLl = tSCLh = 2 x SCLFRQ x tCLK Where tCLK is this device's clock period when in Active mode. The SCLFRQ field may be programmed to values in the range of 0001000b through 1111111b. Using any other value has unpredictable results. ACB Control Register 3 (ACBCTL3)
20.3.6
The ACBCTL3 register is a byte-wide, read/write register that expands the clock prescaler field and enables ARP matches. At reset, the ACBCTL3 register is cleared. 7 Reserved 3 2 ARPMEN 1 0
SCLFRQ8:7
ARPMEN
SCLFRQ
The ARP Match Enable bit enables the matching of an incoming address byte to the SMBus ARP address 110 0001b general call address (Start condition followed by address byte of 00h), while the ACB is in slave mode. 0 - ACB does not respond to ARP addresses. 1 - ARP address matching enabled. The SCL Frequency field specifies the SCL period (low time and high time) in master mode. The ACBCTL3 register provides a 2-bit expansion of this field, with the remaining 7 bits being held in the ACBCTL2 register.
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20.3.7
ACB Own Address Register 1 (ACBADDR1)
20.4
USAGE HINTS
The ACBADDR1 register is a byte-wide, read/write register that holds the module's first ACCESS.bus address. After reset, its value is undefined. 7 SAEN 6 ADDR 0
ADDR
SAEN
The Own Address field holds the first 7-bit ACCESS.bus address of this device. When in slave mode, the first 7 bits received after a Start Condition are compared to this field (first bit received to bit 6, and the last to bit 0). If the address field matches the received data and the SAEN bit is set, a match is detected. The Slave Address Enable bit controls whether address matching is performed in slave mode. When set, the SAEN bit indicates that the ADDR field holds a valid address and enables the match of ADDR to an incoming address byte. When cleared, the ACB does not check for an address match. 0 - Address matching disabled. 1 - Address matching enabled. ACB Own Address Register 2 (ACBADDR2)
20.3.8
The ACBADDR2 register is a byte-wide, read/write register that holds the module's second ACCESS.bus address. After reset, its value is undefined. 7 SAEN 6 ADDR 0
ADDR
SAEN
The Own Address field holds the second 7-bit ACCESS.bus address of this device. When in slave mode, the first 7 bits received after a Start Condition are compared to this field (first bit received to bit 6, and the last to bit 0). If the address field matches the received data and the SAEN bit is set, a match is detected. The Slave Address Enable bit controls whether address matching is performed in slave mode. When set, the SAEN bit indicates that the ADDR field holds a valid address and enables the match of ADDR to an incoming address byte. When cleared, the ACB does not check for an address match. 0 - Address matching disabled. 1 - Address matching enabled.
When the ACB module is disabled, the ACBCST.BB bit is cleared. After enabling the ACB (ACBCTL2.ENABLE = 1) in systems with more than one master, the bus may be in the middle of a transaction with another device, which is not reflected in the BB bit. There is a need to allow the ACB to synchronize to the bus activity status before issuing a request to become the bus master, to prevent bus errors. Therefore, before issuing a request to become the bus master for the first time, software should check that there is no activity on the bus by checking the BB bit after the bus allowed time-out period. When waking up from power down, before checking the ACBCST.MATCH bit, test the ACBCST.BUSY bit to make sure that the address transaction has finished. The BB bit is intended to solve a deadlock in which two, or more, devices detect a usage conflict on the bus and both devices cease being bus masters at the same time. In this situation, the BB bits of both devices are active (because each deduces that there is another master currently performing a transaction, while in fact no device is executing a transaction), and the bus would stay locked until some device sends a ACBCTL1.STOP condition. The ACBCST.BB bit allows software to monitor bus usage, so it can avoid sending a STOP signal in the middle of the transaction of some other device on the bus. This bit detects whether the bus remains unused over a certain period, while the BB bit is set. In some cases, the bus may get stuck with the SCL or SDA lines active. A possible cause is an erroneous Start or Stop Condition that occurs in the middle of a slave receive session. When the SCL signal is stuck active, there is nothing that can be done, and it is the responsibility of the module that holds the bus to release it. When the SDA signal is stuck active, the ACB module enables the release of the bus by using the following sequence. Note that in normal cases, the SCL signal may be toggled only by the bus master. This protocol is a recovery scheme which is an exception that should be used only in the case when there is no other master on the bus. The recovery scheme is as follows: 1. Disable and re-enable the module to set it into the not addressed slave mode. 2. Set the ACBCTL1.START bit to make an attempt to issue a Start Condition. 3. Check if the SDA signal is active (low) by reading ACBCST.TSDA bit. If it is active, issue a single SCL cycle by writing 1 to ACBCST.TGSCL bit. If the SDA line is not active, continue from step 5. 4. Check if the ACBST.MASTER bit is set, which indicates that the Start Condition was sent. If not, repeat step 3 and 4 until the SDA signal is released. 5. Clear the BB bit. This enables the START bit to be executed. Continue according to "Bus Idle Error Recovery" on page 125.
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21.0 Timing and Watchdog Module
The Timing and Watchdog Module (TWM) generates the clocks and interrupts used for timing periodic functions in the system; it also provides Watchdog protection over software execution. The TWM is designed to provide flexibility in system design by configuring various clock ratios and by selecting the Watchdog clock source. After setting the TWM configuration, software can lock it for a higher level of protection against erroneous software action. Once the TWM is locked, only reset can release it. Slow Clock period. The prescaled clock signal is called T0IN.
21.2
TIMER T0 OPERATION
Timer T0 is a programmable 16-bit down counter that can be used as the time base for real-time operations such as a periodic audible tick. It can also be used to drive the Watchdog circuit. The timer starts counting from the value loaded into the TWMT0 register and counts down on each rising edge of T0IN. When the timer reaches zero, it is automatically reloaded from the TWMT0 register and continues counting down from that value. Therefore, the frequency of the timer is: fSLCLK / [(TWMT0 + 1) x prescaler] When an external crystal oscillator is used as the SLCLK source or when the fast clock is divided accordingly, fSLCLK is 32.768 kHz. The value stored in TWMT0 can range from 0001h to FFFFh.
21.1
TWM STRUCTURE
Figure 44 is a block diagram showing the internal structure of the Timing and Watchdog module. There are two main sections: the Real-Time Timer (T0) section at the top and the Watchdog section on the bottom. All counting activities of the module are based on the Slow Clock (SLCLK). A prescaler counter divides this clock to make a slower clock. The prescaler factor is defined by a 3bit field in the Timer and Watchdog Prescaler register, which selects either 1, 2, 4, 8, 16, or 32 as the divisor. Therefore, the prescaled clock period can be 2, 4, 8, 16, or 32 times the
REAL TIME TIMER (T0) Slow Clock 5-Bit Prescaler Counter (TWCP) T0IN
TWW/MT0 Register
T0CSR Contrl. Reg.
T0LINT (to ICU)
Restart 16-Bit Timer (Timer0) Underflow T0OUT (to Multi-InputWake-Up)
WATCHDOG Timer
Underflow
Restart
WATCHDOG Service Logic
WDSDM WDCNT
Watchdog Error WATCHDOG
WDERR DS080
Figure 44. Timing and Watchdog Module Block Diagram When the counter reaches zero, an internal timer signal called T0OUT is set for one T0IN clock cycle. This signal sets the TC bit in the TWMT0 Control and Status Register (T0CSR). It also generates an interrupt (IRQ14), when enabled by the T0CSR.T0INTE bit. T0OUT is also an input to the MIWU (see Section 13.0), so an edge-triggered interrupt is also available through this alternative mechanism. If software loads the TWMT0 register with a new value, the timer uses that value the next time that it reloads the 16-bit timer register (in other words, after reaching zero). Software can restart the timer at any time (on the very next edge of the T0IN clock) by setting the Restart (RST) bit in the T0CSR register. The T0CSR.RST bit is cleared automatically upon restart of the 16-bit timer. Note: If software wishes to switch to Power Save or Idle mode after setting the T0CSR.RST bit, software must wait for the reset operation to complete before performing the switch. www.national.com
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21.3
WATCHDOG OPERATION
21.3.2
Power Save Mode Operation
The Watchdog is an 8-bit down counter that operates on the rising edge of a specified clock source. At reset, the Watchdog is disabled; it does not count and no Watchdog signal is generated. A write to either the Watchdog Count (WDCNT) register or the Watchdog Service Data Match (WDSDM) register starts the counter. The Watchdog counter counts down from the value programmed in the WDCNT register. Once started, only a reset can stop the Watchdog from operating. The Watchdog can be programmed to use either T0OUT or T0IN as its clock source (the output and input of Timer T0, respectively). The TWCFG.WDCT0I bit controls this clock selection. Software must periodically "service" the Watchdog. There are two ways to service the Watchdog, the choice depending on the programmed value of the WDSDME bit in the Timer and Watchdog Configuration (TWCFG) register. If the TWCFG.WDSDME bit is clear, the Watchdog is serviced by writing a value to the WDCNT register. The value written to the register is reloaded into the Watchdog counter. The counter then continues counting down from that value. If the TWCFG.WDSDME bit is set, the Watchdog is serviced by writing the value 5Ch to the Watchdog Service Data Match (WDSDM) register. This reloads the Watchdog counter with the value previously programmed into the WDCNT register. The counter then continues counting down from that value. A Watchdog error signal is generated by any of the following events: The Watchdog serviced too late. The Watchdog serviced too often. The WDSDM register is written with a value other than 5Ch when WDSDM type servicing is enabled (TWCFG.WDSDME = 1). A Watchdog error condition resets the device. 21.3.1 Register Locking
The Timer and Watchdog Module is active in both the Power Save and Idle modes. The clocks and counters continue to operate normally in these modes. The WDSDM register is accessible in the Power Save and Idle modes, but the other TWM registers are accessible only in the Active mode. Therefore, Watchdog servicing must be carried out using the WDSDM register in the Power Save or Idle mode. In the Halt mode, the entire device is frozen, including the Timer and Watchdog Module. On return to Active mode, operation of the module resumes at the point at which it was stopped. Note: After a restart or Watchdog service through WDCNT, do not enter Power Save mode for a period equivalent to 5 Slow Clock cycles.
21.4
TWM REGISTERS
The TWM registers controls the operation of the Timing and Watchdog Module. There are six such registers: Table 47 TWM Registers Name TWCFG Address FF FF20h Description Timer and Watchdog Configuration Register Timer and Watchdog Clock Prescaler Register TWM Timer 0 Register TWMT0 Control and Status Register Watchdog Count Register Watchdog Service Data Match Register
TWCP TWMT0 T0CSR WDCNT WDSDM
FF FF22h FF FF24h FF FF26h FF FF28h FF FF2Ah
The Timer and Watchdog Configuration (TWCFG) register is used to set the Watchdog configuration. It controls the The WDSDM register is accessible in both Active and PowWatchdog clock source (T0IN or T0OUT), the type of er Save mode. The other TWM registers are accessible only Watchdog servicing (using WDCNT or WDSDM), and the in Active mode. locking state of the TWCFG, TWCPR, TIMER0, T0CSR, and WDCNT registers. A register that is locked cannot be read or written. A write operation is ignored and a read operation returns unpredictable results. If the TWCFG register is itself locked, it remains locked until the device is reset. Any other locked registers also remain locked until the device is reset. This feature prevents a runaway program from tampering with the programmed Watchdog function.
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21.4.1
Timer and Watchdog Configuration Register (TWCFG)
21.4.2
Timer and Watchdog Clock Prescaler Register (TWCP)
The TWCFG register is a byte-wide, read/write register that selects the Watchdog clock input and service method, and also allows the Watchdog registers to be selectively locked. A locked register cannot be read or written; a read operation returns unpredictable values and a write operation is ignored. Once a lock bit is set, that bit cannot be cleared until the device is reset. At reset, the non-reserved bits of the register are cleared. The register format is shown below. 76 5 4 3 2 1 0
The TWCP register is a byte-wide, read/write register that specifies the prescaler value used for dividing the low-frequency clock to generate the T0IN clock. At reset, the nonreserved bits of the register are cleared. The register format is shown below. 7 Reserved 3 2 MDIV 0
Res. WDSDME WDCT0I LWDCNT LTWMT0 LTWCP LTWCFG
MDIV
LTWCFG
LTWCP
LTWMT0
LWDCNT
WDCT0I
WDSDME
The Lock TWCFG Register bit controls access to the TWCFG register. When clear, access to the TWCFG register is allowed. When set, the TWCFG register is locked. 0 - TWCFG register unlocked. 1 - TWCFG register locked. The Lock TWCP Register bit controls access to the TWCP register. When clear, access to the TWCP register is allowed. When set, the TWCP register is locked. 0 - TWCP register unlocked. 1 - TWCP register locked. The Lock TWMT0 Register bit controls access to the TWMT0 register. When clear, access to the TWMT0 and T0CSR registers are allowed. When set, the TWMT0 and T0CSR registers are locked. 0 - TWMT0 register unlocked. 1 - TWMT0 register locked. The Lock LDWCNT Register bit controls access to the LDWCNT register. When clear, access to the LDWCNT register is allowed. When set, the LDWCNT register is locked. 0 - LDWCNT register unlocked. 1 - LDWCNT register locked. The Watchdog Clock from T0IN bit selects the clock source for the Watchdog timer. When clear, the T0OUT signal (the output of Timer T0) is used as the Watchdog clock. When set, the T0IN signal (the prescaled Slow Clock) is used as the Watchdog clock. 0 - Watchdog timer is clocked by T0OUT. 1 - Watchdog timer is clocked by T0IN. The Watchdog Service Data Match Enable bit controls which method is used to service the Watchdog timer. When clear, Watchdog servicing is accomplished by writing a count value to the WDCNT register; write operations to the Watchdog Service Data Match (WDSDM) register are ignored. When set, Watchdog servicing is accomplished by writing the value 5Ch to the WDSDM register. 0 - Write a count value to the WDCNT register to service the Watchdog timer. 1 - Write 5Ch to the WDSDM register to service the Watchdog timer.
Main Clock Divide. This 3-bit field defines the prescaler factor used for dividing the low speed device clock to create the T0IN clock. The allowed 3-bit values and the corresponding clock divisors and clock rates are listed below. MDIV 000 001 010 011 100 101 Other Clock Divisor (fSCLK = 32.768 kHz) 1 2 4 8 16 32 Reserved T0IN Frequency 32.768 kHz 16.384 kHz 8.192 kHz 4.096 kHz 2.056 kHz 1.024 kHz N/A
21.4.3
TWM Timer 0 Register (TWMT0)
The TWMT0 register is a word-wide, read/write register that defines the T0OUT interrupt rate. At reset, TWMT0 register is initialized to FFFFh. The register format is shown below. 15 PRESET 0
PRESET
The Timer T0 Preset field holds the value used to reload Timer T0 on each underflow. Therefore, the frequency of the Timer T0 interrupt is the frequency of T0IN divided by (PRESET+1). The allowed values of PRESET are 0001h through FFFFh.
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21.4.4
TWMT0 Control and Status Register (T0CSR)
21.4.5
Watchdog Count Register (WDCNT)
The T0CSR register is a byte-wide, read/write register that controls Timer T0 and shows its current status. At reset, the non-reserved bits of the register are cleared. The register format is shown below. 7 5 4 3 2 T0INTE 1 TC 0 RST
The WDCNT register is a byte-wide, write-only register that holds the value that is loaded into the Watchdog counter each time the Watchdog is serviced. The Watchdog is started by the first write to this register. Each successive write to this register restarts the Watchdog count with the written value. At reset, this register is initialized to 0Fh. 7 PRESET 0
Reserved
FRZT0E WDLTD
RST
TC
T0INTE
WDLTD
FRZT0E
The Restart bit is used to reset Timer T0. When this bit is set, it forces the timer to reload the value in the TWMT0 register on the next rising edge of the selected input clock. The RST bit is reset automatically by the hardware on the same rising edge of the selected input clock. Writing a 0 to this bit position has no effect. At reset, the non-reserved bits of the register are cleared. 0 - Writing 0 has no effect. 1 - Writing 1 resets Timer T0. The Terminal Count bit is set by hardware when the Timer T0 count reaches zero and is cleared when software reads the T0CSR register. It is a read-only bit. Any data written to this bit position is ignored. The TC bit is not cleared if FREEZE mode is asserted by an external debugging system. 0 - Timer T0 did not count down to 0. 1 - Timer T0 counted down to 0. The Timer T0 Interrupt Enable bit enables an interrupt to the CPU each time the Timer T0 count reaches zero. When this bit is clear, Timer T0 interrupts are disabled. 0 - Timer T0 interrupts disabled. 1 - Timer T0 interrupts enabled. The Watchdog Last Touch Delay bit is set when either WDCNT or WDSDM is written and the data transfer to the Watchdog is in progress (see WDCNT and WDSDM register description). When clear, it is safe to switch to Power Save mode. 0 - No data transfer to the Watchdog is in progress, safe to enter Power Save mode. 1 - Data transfer to the Watchdog in progress. The Freeze Timer0 Enable bit controls whether TImer 0 is stopped in FREEZE mode. If this bit is set, the Timer 0 is frozen (stopped) when the FREEZE input to the TWM is asserted. If the FRZT0E bit is clear, only the Watchdog timer is frozen by asserting the FREEZE input signal. After reset, this bit is clear. 0 - Timer T0 unaffected by FREEZE mode. 1 - Timer T0 stopped in FREEZE mode.
21.4.6
Watchdog Service Data Match Register (WDSDM)
The WSDSM register is a byte-wide, write-only register used for servicing the Watchdog. When this type of servicing is enabled (TWCFG.WDSDME = 1), the Watchdog is serviced by writing the value 5Ch to the WSDSM register. Each such servicing reloads the Watchdog counter with the value previously written to the WDCNT register. Writing any data other than 5Ch triggers a Watchdog error. Writing to the register more than once in one Watchdog clock cycle also triggers a Watchdog error signal. If this type of servicing is disabled (TWCFG.WDSDME = 0), any write to the WSDSM register is ignored. 7 RSTDATA 0
21.5
WATCHDOG PROGRAMMING PROCEDURE
The highest level of protection against software errors is achieved by programming and then locking the Watchdog registers and using the WDSDM register for servicing. This is the procedure: 1. Write the desired values into the TWM Clock Prescaler register (TWCP) and the TWM Timer 0 register (TWMT0) to control the T0IN and T0OUT clock rates. The frequency of T0IN can be programmed to any of six frequencies ranging from 1/32 x fSLCLK to fSLCLK. The frequency of T0OUT is equal to the frequency of T0IN divided by (1+ PRESET), in which PRESET is the value written to the TWMT0 register. 2. Configure the Watchdog clock to use either T0IN or T0OUT by setting or clearing the TWCFG.WDCT0I bit. 3. Write the initial value into the WDCNT register. This starts operation of the Watchdog and specifies the maximum allowed number of Watchdog clock cycles between service operations. 4. Set the T0CSR.RST bit to restart the TWMT0 timer. 5. Lock the Watchdog registers and enable the Watchdog Service Data Match Enable function by setting bits 0, 1, 2, 3, and 5 in the TWCFG register. 6. Service the Watchdog by periodically writing the value 5Ch to the WDSDM register at an appropriate rate. Servicing must occur at least once per period programmed into the WDCNT register, but no more than once in a single Watchdog input clock cycle.
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22.0 Multi-Function Timer
The Multi-Function Timer module contains a pair of 16-bit timer/counters. Each timer/counter unit offers a choice of clock sources for operation and can be configured to operate in any of the following modes: Processor-Independent Pulse Width Modulation (PWM) mode, which generates pulses of a specified width and duty cycle, and which also provides a general-purpose timer/counter. Input Capture mode, which measures the elapsed time between occurrences of external events, and which also provides a general-purpose timer/counter. Dual Independent Timer mode, which generates system timing signals. The timer unit uses an I/O pin called TA, which is an alternate function of the PI7 port pin.
22.1
TIMER STRUCTURE
Figure 45 is a block diagram showing the internal structure of the MFT. There are two main functional blocks: a Timer/ Counter and Action block and a Clock Source block. The Timer/Counter and Action block contains two separate timer/counter units, called Timer/Counter 1 and Timer/Counter 2.
Clock Source Clock Prescaler/Selector
Timer/Counter Reload/Capture A TCRA Timer/Counter 1 TCNT1 Reload/Capture B TCRB Timer/Counter 2 TCNT2
Action
Toggle/Capture/Interrupt
TA Interrupt A Interrupt B
System Clock
External Event
PWM/Capture/Counter Mode Select + Control
DS165
Figure 45. Multi-Function Timer Block Diagram 22.1.1 Timer/Counter Block In a power-saving mode that uses the low-frequency (32.768 kHz) clock as the System Clock, the synchronization circuit requires that the Slow Clock operate at no more than one-fourth the speed of the 32.768 kHz System Clock. 22.1.2 Clock Source Block
The Timer/Counter block contains the following functional blocks: Two 16-bit counters, Timer/Counter 1 (TCNT1) and Timer/Counter 2 (TCNT2) Two 16-bit reload/capture registers, TCRA and TCRB Control logic necessary to configure the timer to operate in any of the four operating modes Interrupt control and I/O control logic
The Clock Source block generates the signals used to clock the two timer/counter registers. The internal structure of the Clock Source block is shown in Figure 46.
No Clock Prescaler Register TPRSC
Counter 1 Clock Select
Counter 1 Clock
Reset System Clock
5-Bit Prescaler Counter
Prescaled Clock
Counter 2 Clock Select
Counter 2 Clock DS164
Figure 46.
Multi-Function Timer Clock Source
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Counter Clock Source Select
22.2
TIMER OPERATING MODES
There are two clock source selectors that allow software to Each timer/counter unit can be configured to operate in any independently select the clock source for each of the two of the following modes: 16-bit counters from any one of the following sources: Processor-Independent Pulse Width Modulation (PWM) No clock (which stops the counter) mode Prescaled System Clock Input Capture mode Slow Clock (derived from the low-frequency oscillator or Dual Independent Timer mode divided from the high-speed oscillator) At reset, the timers are disabled. To configure and start the timers, software must write a set of values to the registers Prescaler that control the timers. The registers are described in The 5-bit clock prescaler allows software to run the timer Section 22.5. with a prescaled clock signal. The prescaler consists of a 5bit read/write prescaler register (TPRSC) and a 5-bit down counter. The System Clock is divided by the value contained in the prescaler register plus 1. Therefore, the timer clock period can be set to any value from 1 to 32 divisions of the System Clock period. The prescaler register and down counter are both cleared upon reset. Slow Clock The Slow Clock is generated by the Triple Clock and Reset module. The clock source is either the divided fast clock or the external 32.768 kHz crystal oscillator (if available and selected). The Slow Clock can be used as the clock source for the two 16-bit counters. Because the Slow Clock can be asynchronous to the System Clock, a circuit is provided to synchronize the clock signal to the high-frequency System Clock before it is used for clocking the counters. The synchronization circuit requires that the Slow Clock operate at no more than one-fourth the speed of the System Clock. Limitations in Low-Power Modes The Power Save mode uses the Slow Clock as the System Clock. In this mode, the Slow Clock cannot be used as a clock source for the timers because that would drive both clocks at the same frequency, and the clock ratio needed for synchronization to the System Clock would not be maintained. However, the External Event Clock and Pulse Accumulate Mode will still work, as long as the external event pulses are at least the size of the whole slow-clock period. Using the prescaled System Clock will also work, but at a much slower rate than the original System Clock. Idle and Halt modes stop the System Clock (the high-frequency and/or low-frequency clock) completely. If the System Clock is stopped, the timer stops counting until the System Clock resumes operation. In the Idle or Halt mode, the System Clock stops completely, which stops the operation of the timers. In that case, the timers stop counting until the System Clock resumes operation.
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22.2.1
functions as the time base for the PWM timer. It counts Mode 1 is the Processor-Independent Pulse Width Modula- down at the clock rate selected for the counter. When an untion (PWM) mode, which generates pulses of a specified derflow occurs, the timer register is reloaded alternately width and duty cycle, and which also provides a separate from the TCRA and TCRB registers, and counting proceeds downward from the loaded value. general-purpose timer/counter. Figure 47 is a block diagram of the Multi-Function Timer configured to operate in Mode 1. Timer/Counter 1 (TCNT1)
Reload A = Time 1 TCRA
Mode 1: Processor-Independent PWM
TAPND
Underflow TAIEN Timer 1 Clock Timer/Counter 1 TCNT1 TAEN Underflow TBIEN Reload B = Time 2 TCRB TBPND
Timer Interrupt A
TA
Timer Interrupt B
Timer 2 Clock
Timer/Counter 2 TCNT2 TDIEN TDPND
Timer Interrupt D
DS166
Figure 47.
Processor-Independent PWM Mode The timer can be configured to generate separate interrupts upon reload from the TCRA and TCRB registers. The interrupts can be enabled or disabled under software control. The CPU can determine the cause of each interrupt by looking at the TAPND and TBPND bits, which are updated by the hardware on each occurrence of a timer reload. In Mode 1, Timer/Counter 2 (TCNT2) can be used either as a simple system timer, an external event counter, or a pulseaccumulate counter. The clock counts down using the clock selected with the Timer/Counter 2 clock selector. It generates an interrupt upon each underflow if the interrupt is enabled with the TDIEN bit.
On the first underflow, the timer is loaded from the TCRA register, then from the TCRB register on the next underflow, then from the TCRA register again on the next underflow, and so on. Every time the counter is stopped and restarted, it always obtains its first reload value from the TCRA register. This is true whether the timer is restarted upon reset, after entering Mode 1 from another mode, or after stopping and restarting the clock with the Timer/Counter 1 clock selector. The timer can be configured to toggle the TA output bit on each underflow. This generates a clock signal on the TA output with the width and duty cycle determined by the values stored in the TCRA and TCRB registers. This is a "processor-independent" PWM clock because once the timer is set up, no more action is required from the CPU to generate a continuous PWM signal.
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22.2.2
Mode 2: Input Capture
Mode 2 is the Input Capture mode, which measures the elapsed time between occurrences of external events, and which also provides a separate general-purpose timer/ counter. Figure 48 is a block diagram of the Multi-Function Timer configured to operate in Mode 2. The time base of the cap-
ture timer depends on Timer/Counter 1, which counts down using the clock selected with the Timer/Counter 1 clock selector. The TA pin functions as a capture input. A transition received on the TA pin transfers the timer contents to the TCRA register. The TA pin can be configured to sense either rising or falling edges.
Timer Interrupt 1 TAIEN TAPND Capture A TCRA Preset TAEN Timer 1 Clock Timer/Counter 1 TCNT1 Underflow TCIEN TA
TCPND Timer Interrupt 1
TDPND Timer 2 Clock Timer/Counter 2 TnCNT2 Underflow TDIEN Timer Interrupt 2 DS167
Figure 48. Input Capture Mode The TA input can be configured to preset the counter to FFFFh on reception of a valid capture event. In this case, the current value of the counter is transferred to the corresponding capture register and then the counter is preset to FFFFh. Using this approach allows software to determine the on-time and off-time and period of an external signal with a minimum of CPU overhead. The values captured in the TCRA register at different times reflect the elapsed time between transitions on the TA pin. The input signal on the TA pin must have a pulse width equal to or greater than one System Clock cycle. There are two separate interrupts associated with the capture timer, each with its own enable bit and pending bit. The interrupt events are reception of a transition on the TA pin and underflow of the TCNT1 counter. The enable bits for these events are TAIEN and TCIEN, respectively. In Mode 2, Timer/Counter 2 (TCNT2) can be used as a simple system timer. The clock counts down using the clock selected with the Timer/Counter 2 clock selector. It generates an interrupt upon each underflow if the interrupt is enabled with the TDIEN bit.
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22.2.3
Mode 3: Dual Independent Timer/Counter
Mode 3 is the Dual Independent Timer mode, which generates system timing signals or counts occurrences of external events.
Figure 49 is a block diagram of the Multi-Function Timer configured to operate in Mode 3. The timer is configured to operate as a dual independent system timer or dual external event counter. In addition, Timer/Counter 1 can generate a 50% duty cycle PWM signal on the TA pin.
Reload A TCRA
TAPND
Underflow TAIEN Timer 1 Clock Timer/Counter 1 TCNT1 TAEN Reload B TCRB
Timer Interrupt 1
TA
Underflow TDIEN Timer 2 Clock Timer/Counter 2 TCNT2 TDPND
Timer Interrupt 2
DS168
Figure 49. Dual-Independent Timer/Counter Mode Timer/Counter 1 (TCNT1) counts down at the rate of the selected clock. On underflow, it is reloaded from the TCRA register and counting proceeds down from the reloaded value. In addition, the TA pin is toggled on each underflow if this function is enabled by the TAEN bit. The initial state of the TA pin is software-programmable. When the TA pin is toggled from low to high, it sets the TCPND interrupt pending bit and also generates an interrupt if enabled by the TAIEN bit. Because the TA pin toggles on every underflow, a 50% duty cycle PWM signal can be generated on the TA pin without any further action from the CPU. Timer/Counter 2 (TCNT2) counts down at the rate of the selected clock. On underflow, it is reloaded from the TCRB register and counting proceeds down from the reloaded value. In addition, each underflow sets the TDPND interrupt pending bit and generates an interrupt if the interrupt is enabled by the TDIEN bit.
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22.3
TIMER INTERRUPTS
22.4
TIMER I/O FUNCTIONS
Each Multi-Function Timer unit has four interrupt sources, designated A, B, C, and D. Interrupt sources A, B, and C are mapped into a single system interrupt called Timer Interrupt 1, while interrupt source D is mapped into a system interrupt called Timer Interrupt 2. Each of the four interrupt sources has its own enable bit and pending bit. The enable bits are named TAIEN, TBIEN, TCIEN, and TDIEN. The pending bits are named TAPND, TBPND, TCPND, and TDPND. Timer Interrupts 1 and 2 are system interrupts TA and TB (IRQ14 and IRQ13), respectively. Table 48 shows the events that trigger interrupts A, B, C, and D in each of the four operating modes. Note that some interrupt sources are not used in some operating modes.
Table 49 shows the functions of the the TA pin in each operating mode, and for each combination of enable bit settings. When the TA pin is configured to operate as a PWM output (TAEN = 1), the state of the pin is toggled on each underflow of the TCNT1 counter. In this case, the initial value on the pin is determined by the TAOUT bit. For example, to start with TA high, software must set the TAOUT bit before enabling the timer clock. This option is available only when the timer is configured to operate in Mode 1 or 3 (in other words, when TCRA is not used in Capture mode).
Table 48 Timer Interrupts Overview Interrupt Pending Bit TAPND TBPND TCPND Timer Int. 2 (TB Int.) TDPND Mode 1 PWM + Counter Mode 2 Dual Input Capture + Counter Mode 3 Dual Counter
Sys. Int.
Timer Int. 1 (TA Int.)
TCNT1 reload from TCRA Input capture on TA transition TCNT1 reload from TCRA TCNT1 reload from TCRB Input Capture on TB transition N/A TCNT2 underflow TCNT1 underflow TCNT2 underflow N/A N/A TCNT2 reload from TCRB
Table 49 Timer I/O Functions Mode 1 I/O TAEN TBEN TAEN = 0 TBEN = X TAEN = 1 TBEN = X PWM + Counter No Output Toggle Output on Underflow of TCNT1 Mode 2 Dual Input Capture + counter Capture TCNT1 into TCRA Capture TCNT1 into TCRA and Preset TCNT1 Mode 3 Dual Counter No Output Toggle Toggle Output on Underflow of TCNT1
TA
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22.5
TIMER REGISTERS
22.5.2
Clock Unit Control Register (TCKC)
Table 50 lists the CPU-accessible registers used to control the Multi-Function Timers. Table 50 Multi-Function Timer Registers Name TPRSC TCKC TCNT1 TCNT2 TCRA TCRB TCTRL TICTL TICLR 22.5.1 Address FF FF48h FF FF4Ah FF FF40h FF FF46h FF FF42h FF FF44h FF FF4Ch FF FF4Eh FF FF50h Description Clock Prescaler Register Clock Unit Control Register
The TCKC register is a byte-wide, read/write register that selects the clock source for each timer/counter. Selecting the clock source also starts the counter. This register is cleared on reset, which disables the timer/counters. The register format is shown below. 7 6 5 C2CSEL 3 2 C1CSEL 0
Reserved
C1CSEL Timer/Counter 1 Register Timer/Counter 2 Register Reload/Capture A Register Reload/Capture B Register Timer Mode Control Register Timer Interrupt Control Register Timer Interrupt Clear Register C2CSEL
Clock Prescaler Register (TPRSC)
The TPRSC register is a byte-wide, read/write register that holds the current value of the 5-bit clock prescaler (CLKPS). This register is cleared on reset. The register format is shown below. 7 Reserved 5 4 CLKPS 0
The Counter 1 Clock Select field specifies the clock mode for Timer/Counter 1 as follows: 000 - No clock (Timer/Counter 1 stopped, modes 1, 2, and 3 only). 001 - Prescaled System Clock. 010 - Reserved. 011 - Reserved. 100 - Slow Clock.* 101 - Reserved. 110 - Reserved. 111 - Reserved. The Counter 2 Clock Select field specifies the clock mode for Timer/Counter 2 as follows: 000 - No clock (Timer/Counter 2 stopped, modes 1, 2, and 3 only). 001 - Prescaled System Clock. 010 - Reserved. 011 - Reserved. 100 - Slow Clock* 101 - Reserved. 110 - Reserved. 111 - Reserved.
* Operation of the Slow Clock is determined by the CRCTRL.SCLK control bit, as described in Section 11.9.1. 22.5.3 Timer/Counter 1 Register (TCNT1)
The TCNT1 register is a word-wide, read/write register that holds the current count value for Timer/Counter 1. The register contents are not affected by a reset and are unknown after power-up. 15 TCNT1 0
CLKPS
The Clock Prescaler field specifies the divisor used to generate the Timer Clock from the System Clock. When the timer is configured to use the prescaled clock, the System Clock is divided by (CLKPS + 1) to produce the timer clock. Therefore, the System Clock divisor can range from 1 to 32.
22.5.4
Timer/Counter 2 Register (TCNT2)
The TCNT2 register is a word-wide, read/write register that holds the current count value for Timer/Counter 2. The register contents are not affected by a reset and are unknown after power-up. 15 TCNT2 0
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22.5.5
Reload/Capture A Register (TCRA)
TAEN
The TCRA register is a word-wide, read/write register that holds the reload or capture value for Timer/Counter 1. The register contents are not affected by a reset and are unknown after power-up. 15 TCRA 0
22.5.6
Reload B Register (TCRB)
TAOUT
The TCRB register is a word-wide, read/write register that holds the reload value for Timer/Counter 2. The register contents are not affected by a reset and are unknown after power-up. 15 TCRB TEN 0
22.5.7
Timer Mode Control Register (TCTRL)
The TCTRL register is a byte-wide, read/write register that sets the operating mode of the timer/counter and the TA pin. This register is cleared at reset. The register format is shown below. 7 6 5 4 TAEN 3 Res. 2 1 0
TEN TAOUT Res.
TAEDG MDSEL
MDSEL
TAEDG
The Mode Select field sets the operating mode of the timer/counter as follows: 00 - Mode 1: PWM plus system timer. 01 - Mode 2: Input Capture plus system timer. 10 - Mode 3: Dual Timer/Counter. 11 - Reserved. The TA Edge Polarity bit selects the polarity of the edges that trigger the TA input. 0 - TA input is sensitive to falling edges (high to low transitions). 1 - TA input is sensitive to rising edges (low to high transitions).
The TA Enable bit controls whether the TA pin is enabled to operate as a preset input or as a PWM output, depending on the timer operating mode. In Mode 2 (Dual Input Capture), a transition on the TA pin presets the TCNT1 counter to FFFFh. In the other modes, TA functions as a PWM output. When this bit is clear, operation of the pin for the timer/counter is disabled. 0 - TA input disabled. 1 - TA input enabled. The TA Output Data bit indicates the current state of the TA pin when the pin is used as a PWM output. The hardware sets and clears this bit, but software can also read or write this bit at any time and therefore control the state of the output pin. In case of conflict, a software write has precedence over a hardware update. This bit setting has no effect when the TA pin is used as an input. 0 - TA pin is low. 1 - TA pin is high. The Timer Enable bit controls whether the Multi-Function Timer is enabled. When the module is disabled all clocks to the counter unit are stopped to minimize power consumption. For that reason, the timer/counter registers (TCNT1 and TCNT2), the capture/reload registers (TCRA and TCRB), and the interrupt pending bits (TXPND) cannot be written in this mode. Also, the 5-bit clock prescaler and the interrupt pending bits are cleared, and the TA I/O pin becomes an input. 0 - Multi-Function Timer is disabled. 1 - Multi-Function Timer is enabled. Timer Interrupt Control Register (TICTL)
22.5.8
The TICTL register is a byte-wide, read/write register that contains the interrupt enable bits and interrupt pending bits for the four timer interrupt sources, designated A, B, C, and D. The condition that causes each type of interrupt depends on the operating mode, as shown in Table 48. This register is cleared upon reset. The register format is shown below. 7 6 5 4 3 2 1 0
TDIEN TCIEN TBIEN TAIEN TDPND TCPND TBPND TAPND
TAPND
The Timer Interrupt Source A Pending bit indicates that timer interrupt condition A has occurred. For an explanation of interrupt conditions A, B, C, and D, see Table 48. This bit can be set by hardware or by software. To clear this bit, software must use the Timer Interrupt Clear Register (TICLR). Any attempt by software to directly write a 0 to this bit is ignored. 0 - Interrupt source A has not triggered. 1 - Interrupt source A has triggered.
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TBPND
TCPND
TDPND
TAIEN
TBIEN
TCIEN
TDIEN
The Timer Interrupt Source B Pending bit indicates that timer interrupt condition B has occurred. For an explanation of interrupt conditions A, B, C, and D, see Table 48. This bit can be set by hardware or by software. To clear this bit, software must use the Timer Interrupt Clear Register (TICLR). Any attempt by software to directly write a 0 to this bit is ignored. 0 - Interrupt source B has not triggered. 1 - Interrupt source B has triggered. The Timer Interrupt Source C Pending bit indicates that timer interrupt condition C has occurred. For an explanation of interrupt conditions A, B, C, and D, see Table 48. This bit can be set by hardware or by software. To clear this bit, software must use the Timer Interrupt Clear Register (TICLR). Any attempt by software to directly write a 0 to this bit is ignored. 0 - Interrupt source C has not triggered. 1 - Interrupt source C has triggered. The Timer Interrupt Source D Pending bit indicates that timer interrupt condition D has occurred. For an explanation of interrupt conditions A, B, C, and D, see Table 48. This bit can be set by hardware or by software. To clear this bit, software must use the Timer Interrupt Clear Register (TICLR). Any attempt by software to directly write a 0 to this bit is ignored. 0 - Interrupt source D has not triggered. 1 - Interrupt source D has triggered. The Timer Interrupt A Enable bit controls whether an interrupt is generated on each occurrence of interrupt condition A. For an explanation of interrupt conditions A, B, C, and D, see Table 48. 0 - Condition A interrupts disabled. 1 - Condition A interrupts enabled. The Timer Interrupt B Enable bit controls whether an interrupt is generated on each occurrence of interrupt condition B. For an explanation of interrupt conditions A, B, C, and D, see Table 48. 0 - Condition B interrupts disabled. 1 - Condition B interrupts enabled. The Timer Interrupt C Enable bit controls whether an interrupt is generated on each occurrence of interrupt condition C. For an explanation of interrupt conditions A, B, C, and D, see Table 48. 0 - Condition C interrupts disabled. 1 - Condition C interrupts enabled. The Timer Interrupt D Enable bit controls whether an interrupt is generated on each occurrence of interrupt condition D. For an explanation of interrupt conditions A, B, C, and D, see Table 48. 0 - Condition D interrupts disabled. 1 - Condition D interrupts enabled.
22.5.9
Timer Interrupt Clear Register (TICLR)
The TICLR register is a byte-wide, write-only register that allows software to clear the TAPND, TBPND, TCPND, and TDPND bits in the Timer Interrupt Control (TICTRL) register. Do not modify this register with instructions that access the register as a read-modify-write operand, such as the bit manipulation instructions. The register reads as FFh. The register format is shown below. 7 Reserved 4 3 2 1 0
TDCLR TCCLR TBCLR TACLR
TACLR
TBCLR
TCCLR
TDCLR
The Timer Pending A Clear bit is used to clear the Timer Interrupt Source A Pending bit (TAPND) in the Timer Interrupt Control register (TICTL). 0 - Writing a 0 has no effect. 1 - Writing a 1 clears the TAPND bit. The Timer Pending A Clear bit is used to clear the Timer Interrupt Source B Pending bit (TBPND) in the Timer Interrupt Control register (TICTL). 0 - Writing a 0 has no effect. 1 - Writing a 1 clears the TBPND bit. The Timer Pending C Clear bit is used to clear the Timer Interrupt Source C Pending bit (TCPND) in the Timer Interrupt Control register (TICTL). 0 - Writing a 0 has no effect. 1 - Writing a 1 clears the TCPND bit. The Timer Pending D Clear bit is used to clear the Timer Interrupt Source D Pending bit (TDPND) in the Timer Interrupt Control register (TICTL). 0 - Writing a 0 has no effect. 1 - Writing a 1 clears the TDPND bit.
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23.0 Versatile Timer Unit (VTU)
The VTU contains four fully independent 16-bit timer subsystems. Each timer subsystem can operate either as dual 8-bit PWM timers, as a single 16-bit PWM timer, or as a 16bit counter with 2 input capture channels. These timer subsystems offers an 8-bit clock prescaler to accommodate a wide range of system frequencies. The VTU offers the following features: The VTU can be configured to provide: -- Eight fully independent 8-bit PWM channels -- Four fully independent 16-bit PWM channels -- Eight 16-bit input capture channels The VTU consists of four timer subsystems, each of which contains: -- A 16-bit counter -- Two 16-bit capture / compare registers -- An 8-bit fully programmable clock prescaler Each of the four timer subsystems can operate in the following modes: -- Low power mode, i.e. all clocks are stopped -- Dual 8-bit PWM mode -- 16-bit PWM mode -- Dual 16-bit input capture mode The VTU controls a total of eight I/O pins, each of which can function as either: -- PWM output with programmable output polarity -- Capture input with programmable event detection and timer reset A flexible interrupt scheme with -- Four separate system level interrupt requests -- A total of 16 interrupt sources each with a separate interrupt pending bit and interrupt enable bit
23.1
VTU FUNCTIONAL DESCRIPTION
The VTU is comprised of four timer subsystems. Each timer subsystem contains an 8-bit clock prescaler, a 16-bit upcounter, and two 16-bit registers. Each timer subsystem controls two I/O pins which either function as PWM outputs or capture inputs depending on the mode of operation. There are four system-level interrupt requests, one for each timer subsystem. Each system-level interrupt request is controlled by four interrupt pending bits with associated enable/disable bits. All four timer subsystems are fully independent, and each may operate as a dual 8-bit PWM timer, a 16-bit PWM timer, or as a dual 16-bit capture timer. Figure 50 shows the main elements of the VTU.
15 MODE
0
15 INTCTL 15 INTPND
0
15 IO1CTL
0
0
15 IO2CTL
0
Timer Subsystem 1 7 C1 PRSC == Prescaler Counter 15 Count1 Compare - Capture PERCAP1 Compare - Capture DTYCAP1 0 15 7
Timer Subsystem 2 7 C2 PRSC == Prescaler Counter 0 Count2 Compare - Capture PERCAP2 Compare - Capture DTYCAP2 15
Timer Subsystem 3 7 C3 PRSC == Prescaler Counter 0 Count3 Compare - Capture PERCAP3 Compare - Capture DTYCAP3 15
Timer Subsystem 4 C4RSC == Prescaler Counter 0 Count4 Compare - Capture PERCAP4 Compare - Capture DTYCAP4
I/O Control
I/O Control
I/O Control
I/O Control
I/O Control
I/O Control
I/O Control
I/O Control
TIO1
TIO2
TIO3
TIO4
TIO5
TIO6
TIO7
TIO8 DS088
Figure 50. Versatile Timer Unit Block Diagram
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23.1.1
The period of the PWM output waveform is determined by Each timer subsystem may be configured to generate two the value of the PERCAPx register. The TIOx output starts fully independent PWM waveforms on the respective TIOx at the default value as programmed in the IOxCTL.PxPOL pins. In this mode, the counter COUNTx is split and oper- bit. Once the counter value reaches the value of the period ates as two independent 8-bit counters. Each counter incre- register PERCAPx, the counter is cleared on the next counter increment. On the following increment from 00h to ments at the rate determined by the clock prescaler. 01h, the TIOx output will change to the opposite of the deEach of the two 8-bit counters may be started and stopped fault value. separately using the corresponding TxRUN bits. Once either of the two 8-bit timers is running, the clock prescaler The duty cycle of the PWM output waveform is controlled by starts counting. Once the clock prescaler counter value the DTYCAPx register value. Once the counter value reachmatches the value of the associated CxPRSC register field, es the value of the duty cycle register DTYCAPx, the PWM output TIOx changes back to its default value on the next COUNTx is incremented. counter increment. Figure 51 illustrates this concept.
COUNTx PERCAPx 09 08 07 06 05 DTYCAPx 03 02 01 00 TxRUN = 1 00 01 02 04 03 04 05 06 07 08 0A 09 0A
Dual 8-bit PWM Mode
TIOx (PxPOL = 0)
TIOx (PxPOL = 1)
DS089
Figure 51. The period time is determined by the following formula:
VTU PWM Generation Reading the PERCAPx or DTYCAPx register will always return the most recent value written to it. The counter registers can be written if both 8-bit counters are stopped. This allows software to preset the counters before starting, which can be used to generate PWM output waveforms with a phase shift relative to each other. If the counter is written with a value other than 00h, it will start incrementing from that value. The TIOx output will remain at its default value until the first 00h to 01h transition of the counter value occurs. If the counter is preset to values which are less than or equal to the value held in the period register (PERCAPx) the counter will count up until a match between the counter value and the PERCAPx register value occurs. The counter will then be cleared and continue counting up. Alternatively, the counter may be written with a value which is greater than the value held in the period register. In that case the counter will count up to FFh, then roll over to 00h. In any case, the TIOx pin always changes its state at the 00h to 01h transition of the counter.
PWM Period = (PERCAPx + 1) x (CxPRSC + 1) x TCLK The duty cycle in percent is calculated as follows: Duty Cycle = (DTYCAPx / (PERCAPx + 1)) x 100 If the duty cycle register (DTYCAPx) holds a value which is greater than the value held in the period register (PERCAPx) the TIOx output will remain at the opposite of its default value which corresponds to a duty cycle of 100%. If the duty cycle register (DTYCAPx) register holds a value of 00h, the TIOx output will remain at the default value which corresponds to a duty cycle of 0%, in which case the value in the PERCAPx register is irrelevant. This scheme allows the duty cycle to be programmed in a range from 0% to 100%.
In order to allow fully synchronized updates of the period and duty cycle compare values, the PERCAPx and DTYCAPx registers are double buffered when operating in PWM mode. Therefore, if software writes to either the period or duty cycle register while either of the two PWM channels is enabled, the new value will not take effect until the counter Software may only write to the COUNTx register if both value matches the previous period value or the timer is TxRUN bits of a timer subsystem are clear. Any writes to the counter register while either timer is running will be ignored. stopped.
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The two I/O pins associated with a timer subsystem function as independent PWM outputs in the dual 8-bit PWM mode. If a PWM timer is stopped using its associated MODE.TxRUN bit the following actions result: The associated TIOx pin will return to its default value as defined by the IOxCTL.PxPOL bit. The counter will stop and will retain its last value. Any pending updates of the PERCAPx and DTYCAPx register will be completed. The prescaler counter will be stopped and reset if both MODE.TxRUN bits are cleared. Figure 52 illustrates the configuration of a timer subsystem while operating in dual 8-bit PWM mode. The numbering in Figure 52 refers to timer subsystem 1 but equally applies to the other three timer subsystems.
7 C1PRSC == Prescaler Counter 0
Figure 53 illustrates the configuration of a timer subsystem while operating in 16-bit PWM mode. The numbering in Figure 53 refers to timer subsystem 1 but equally applies to the other three timer subsystems.
7 C1PRSC == Prescaler Counter 0 TMOD1 = 10
T1RUN
15 Restart Count1[15:0] Compare PERCAP1[15:0]
0 [15:0]
TMOD1 = 01 Compare DTYCAP1[15:0]
T2RUN
T1RUN R S Q R S Q
15 Res COUNT1[15:8] Compare PERCAP1[15:8] Compare DTYCAP1[15:8]
0 [15:8]
7 Res COUNT1[7:0] Compare PERCAP1[7:0]
0 [7:0] P2POL TIO2 P1POL TIO1 DS091
Figure 53. VTU 16-bit PWM Mode
Compare DTYCAP1[7:0]
23.1.3
Dual 16-Bit Capture Mode
R S
Q
R S
Q
In addition to the two PWM modes, each timer subsystem may be configured to operate in an input capture mode which provides two 16-bit capture channels. The input capture mode can be used to precisely measure the period and duty cycle of external signals.
TIO1 DS090
P2POL TIO2
P1POL
Figure 52. VTU Dual 8-Bit PWM Mode 23.1.2 16-Bit PWM Mode
In capture mode the counter COUNTx operates as a 16-bit up-counter while the two TIOx pins associated with a timer subsystem operate as capture inputs. A capture event on the TIOx pins causes the contents of the counter register (COUNTx) to be copied to the PERCAPx or DTYCAPx registers respectively. Starting the counter is identical to the 16-bit PWM mode, i.e. setting the lower of the two MODE.TxRUN bits will start the counter and the clock prescaler. In addition, the capture event inputs are enabled once the MODE.TxRUN bit is set. The TIOx capture inputs can be independently configured to detect a capture event on either a positive transition, a negative transition or both a positive and a negative transition. In addition, any capture event may be used to reset the counter COUNTx and the clock prescaler counter. This avoids the need for software to keep track of timer overflow conditions and greatly simplifies the direct frequency and duty cycle measurement of an external signal.
Each of the four timer subsystems may be independently configured to provide a single 16-bit PWM channel. In this case the lower and upper bytes of the counter are concatenated to form a single 16-bit counter. Operation in 16-bit PWM mode is conceptually identical to the dual 8-bit PWM operation as outlined under Dual 8-bit PWM Mode on page 145. The 16-bit timer may be started or stopped with the lower MODE.TxRUN bit, i.e. T1RUN for timer subsystem 1. The two TIOx outputs associated with a timer subsystem can be used to produce either two identical PWM waveforms or two PWM waveforms of opposite polarities. This can be accomplished by setting the two PxPOL bits of the respective timer subsystem to either identical or opposite values. www.national.com
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Figure 54 illustrates the configuration of a timer subsystem while operating in capture mode. The numbering in Figure 54 refers to timer subsystem 1 but equally applies to the other three timer subsystems.
7 C1PRSC == Prescaler Counter 0 TMOD1=11
23.1.5
Interrupts
The VTU has a total of 16 interrupt sources, four for each of the four timer subsystems. All interrupt sources have a pending bit and an enable bit associated with them. All interrupt pending bits are denoted IxAPD through IxDPD where "x" relates to the specific timer subsystem. There is one system level interrupt request for each of the four timer subsystems. Figure 55 illustrates the interrupt structure of the versatile timer module.
I1AEN
T1RUN
15 Restart Count1[15:0] Compare PERCAP1[15:0]
0 15:0
I1BEN I1CEN I1DEN
I1APD Compare DTYCAP1[15:0] I1BPD I1CPD I1DPD cap rst 2 C1EDG TIO1 0 cap rst 2 C2EDG TIO2 DS092 0 I4AEN I4BEN I4CEN I4DEN
System Interrupt Request 1
Figure 54. 23.1.4
VTU Dual 16-bit Capture Mode
I4APD I4BPD I4CPD I4DPD
Low Power Mode
System Interrupt Request 4
In case a timer subsystem is not used, software can place it in a low-power mode. All clocks to a timer subsystem are stopped and the counter and prescaler contents are frozen once low-power mode is entered. Software may continue to write to the MODE, INTCTL, IOxCTL, and CLKxPS registers. Write operations to the INTPND register are allowed; but if a timer subsystem is in low-power mode, its associated interrupt pending bits cannot be cleared. Software cannot write to the COUNTx, PERCAPx, and DTYCAPx registers of a timer subsystem while it is in low-power mode. All registers can be read at any time.
DS093
Figure 55. VTU Interrupt Request Structure Each of the timer pending bits - IxAPD through IxDPD - is set by a specific hardware event depending on the mode of operation, i.e., PWM or Capture mode. Table 51 outlines the specific hardware events relative to the operation mode which cause an interrupt pending bit to be set.
Table 51
Pending Flag IxAPD IxBPD IxCPD IxDPD 23.1.6
VTU Interrupt Sources
16-bit PWM Mode Duty Cycle match Period match N/A N/A Capture Mode Capture to PERCAPx Capture to DTYCAPx Counter Overflow N/A
Dual 8-bit PWM Mode Low Byte Duty Cycle match Low Byte Period match High Byte Duty Cycle match High Byte Period match
isters will be frozen; in capture mode, all further capture The VTU supports breakpoint operation of the In-System- events are disabled. Once FREEZE becomes inactive, Emulator (ISE). If FREEZE is asserted, all timer counter counting will resume from the previous value and the capclocks will be inhibited and the current value of the timer reg- ture input events are re-enabled.
ISE Mode operation
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23.2
VTU REGISTERS
23.2.1
Mode Control Register (MODE)
The VTU contains a total of 19 user accessible registers, as The MODE register is a word-wide read/write register which listed in Table 52. All registers are word-wide and are initial- controls the mode selection of all four timer subsystems. ized to a known value upon reset. All software accesses to The register is clear after reset. the VTU registers must be word accesses. Table 52 VTU Registers Name MODE IO1CTL IO2CTL INTCTL INTPND CLK1PS CLK2PS COUNT1 PERCAP1 DTYCAP1 COUNT2 PERCAP2 DTYCAP2 COUNT3 PERCAP3 DTYCAP3 COUNT4 PERCAP4 DTYCAP4 Address FF FF80h FF FF82h FF FF84h FF FF86h FF FF88h FF FF8Ah FF FF98h FF FF8Ch FF FF8Eh FF FF90h FF FF92h FF FF94h FF FF96h FF FF9Ah FF FF9Ch FF FF9Eh FF FFA0h FF FFA2h FF FFA4h Description Mode Control Register I/O Control Register 1 I/O Control Register 2 Interrupt Control Register Interrupt Pending Register Clock Prescaler Register 1 Clock Prescaler Register 2 Counter 1 Register Period/Capture 1 Register Duty Cycle/Capture 1 Register Counter 2 Register Period/Capture 2 Register Duty Cycle/Capture 2 Register Counter 3 Register Period/Capture 3 Register Duty Cycle/Capture 3 Register Counter 4 Register Period/Capture 4 Register Duty Cycle/Capture 4 Register TMODx TxRUN The Timer Run bit controls whether the corresponding timer is stopped or running. If set, the associated counter and clock prescaler is started depending on the mode of operation. Once set, the clock to the clock prescaler and the counter are enabled and the counter will increment each time the clock prescaler counter value matches the value defined in the associated clock prescaler field (CxPRSC). 0 - Timer stopped. 1 - Timer running. The Timer System Operating Mode field enables or disables the Timer Subsystem and defines its operating mode. 00 - Low-Power Mode. All clocks to the counter subsystem are stopped. The counter is stopped regardless of the value of the TxRUN bits. Read operations to the Timer Subsystem will return the last value; software must not perform any write operations to the Timer Subsystem while it is disabled since those will be ignored. 01 - Dual 8-bit PWM mode. Each 8-bit counter may individually be started or stopped via its associated TxRUN bit. The TIOx pins will function as PWM outputs. 10 - 16-bit PWM mode. The two 8-bit counters are concatenated to form a single 16-bit counter. The counter may be started or stopped with the lower of the two TxRUN bits, i.e. T1RUN, T3RUN, T5RUN, and T7RUN. The TIOx pins will function as PWM outputs. 11 - Capture Mode. Both 8-bit counters are concatenated and operate as a single 16-bit counter. The counter may be started or stopped with the lower of the two TxRUN bits, i.e., T1RUN, T3RUN, T5RUN, and T7RUN. The TIOx pins will function as capture inputs. 7 6 5 4 3 2 1 0 TMOD2 T4RUN T3RUN TMOD1 T2RUN T1RUN
15
14
13
12
11
10
9
8
TMOD4 T8RUN T7RUN TMOD3 T6RUN T5RUN
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23.2.2
I/O Control Register 1 (IO1CTL)
23.2.3
I/O Control Register 2 (IO2CTL)
The I/O Control Register 1 (IO1CTL) is a word-wide read/ write register. The register controls the function of the I/O pins TIO1 through TIO4 depending on the selected mode of operation. The register is clear after reset. 7 P2POL 6 C2EDG 4 3 P1POL 2 C1EDG 0
The IO2CTL register is a word-wide read/write register. The register controls the functionality of the I/O pins TIO5 through TIO8 depending on the selected mode of operation. The register is cleared at reset. 7 P6POL 6 C6EDG 4 3 P5POL 2 C5EDG 0
15 P4POL
14 C4EDG
12
11 P3POL
10 C3EDG
8
15 P8POL
14 C8EDG
12
11 P7POL
10 C7EDG
8
CxEDG
The Capture Edge Control field specifies the The functionality of the bit fields of the IO2CTL register is polarity of a capture event and the reset of the identical to the ones described in the IO1CTL register seccounter. The value of this three bit field has no tion. effect while operating in PWM mode. 23.2.4 Interrupt Control Register (INTCTL) CxEDG Capture Counter Reset The INTCTL register is a word-wide read/write register. It 000 001 010 011 100 101 110 111 Rising edge Falling edge Rising edge Falling edge Both edges Both edges Both edges Both edges No No Yes Yes No Rising edge Falling edge Both edges 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I2DEN I2CEN I2BEN I2AEN I1DEN I1CEN I1BEN I1AEN contains the interrupt enable bits for all 16 interrupt sources of the VTU. Each interrupt enable bit corresponds to an interrupt pending bit located in the Interrupt Pending Register (INTPND). All INTCTL register bits are solely under software control. The register is clear after reset.
I4DEN I4CEN I4BEN I4AEN I3DEN I3CEN I3BEN I3AEN
PxPOL
The PWM Polarity bit selects the output polarity. While operating in PWM mode the bit specifies the polarity of the corresponding IxAEN PWM output (TIOx). Once a counter is stopped, the output will assume the value of PxPOL, i.e., its initial value. The PxPOL bit has no effect while operating in capture mode. 0 - The PWM output goes high at the 00h to 01h transition of the counter and will go low once the counter value matches the duty cycle value. 1 - The PWM output goes low at the 00h to IxBEN 01h transition of the counter and will go high once the counter value matches the duty cycle value.
The Timer x Interrupt A Enable bit controls interrupt requests triggered on the corresponding IxAPD bit being set. The associated IxAPD bit will be updated regardless of the value of the IxAEN bit. 0 - Disable system interrupt request for the IxAPD pending bit. 1 - Enable system interrupt request for the IxAPD pending bit. The Timer x Interrupt B Enable bit controls interrupt requests triggered on the corresponding IxBPD bit being set. The associated IxBPD bit will be updated regardless of the value of the IxBEN bit. 0 - Disable system interrupt request for the IxBPD pending bit. 1 - Enable system interrupt request for the IxBPD pending bit.
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IxCEN
IxDEN
The Timer x Interrupt C Enable bit controls interrupt requests triggered on the corresponding IxCPD bit being set. The associated IxCPD bit will be updated regardless of the value of the IxCEN bit. 0 - Disable system interrupt request for the IxCPD pending bit. 1 - Enable system interrupt request for the IxCPD pending bit. Timer x Interrupt D Enable bit controls interrupt requests triggered on the corresponding IxDPD bit being set. The associated IxDPD bit will be updated regardless of the value of the IxDEN bit. 0 - Disable system interrupt request for the IxDPD pending bit. 1 - Enable system interrupt request for the IxDPD pending bit. Interrupt Pending Register (INTPND)
IxDPD
The Timer x Interrupt D Pending bit indicates that an interrupt condition for the related timer subsystem has occurred. Table 51 on page 147 lists the hardware condition which causes this bit to be set. 0 - No interrupt pending. 1 - Timer interrupt condition occurred. Clock Prescaler Register 1 (CLK1PS)
23.2.6
The CLK1PS register is a word-wide read/write register. The register is split into two 8-bit fields called C1PRSC and C2PRSC. Each field holds the 8-bit clock prescaler compare value for timer subsystems 1 and 2 respectively. The register is cleared at reset. 15 C2PRSC 8 7 C1PRSC 0
23.2.5
The INTPND register is a word-wide read/write register which contains all 16 interrupt pending bits. There are four interrupt pending bits called IxAPD through IxDPD for each timer subsystem. Each interrupt pending bit is set by a hardware event and can be cleared if software writes a 1 to the bit position. The value will remain unchanged if a 0 is written to the bit position. All interrupt pending bits are cleared (0) upon reset. 7 6 5 4 3 2 1 0
C1PRSC
C2PRSC
I2DPD I2CPD I2BPD I2APD I1DPD I1CPD I1BPD I1APD
15
14
13
12
11
10
9
8 23.2.7
The Clock Prescaler 1 Compare Value field holds the 8-bit prescaler value for timer subsystem 1. The counter of timer subsystem is incremented each time when the clock prescaler compare value matches the value of the clock prescaler counter. The division ratio is equal to (C1PRSC + 1). For example, 00h is a ratio of 1, and FFh is a ratio of 256. The Clock Prescaler 2 Compare Value field holds the 8-bit prescaler value for timer subsystem 2. The counter of timer subsystem is incremented each time when the clock prescaler compare value matches the value of the clock prescaler counter. The division ratio is equal to (C2PRSC + 1). Clock Prescaler Register 2 (CLK2PS)
I4DPD I4CPD I4BPD I4APD I3DPD I3CPD I3BPD I3APD
IxAPD
IxBPD
IxCPD
The Timer x Interrupt A Pending bit indicates that an interrupt condition for the related timer subsystem has occurred. Table 51 on page 147 lists the hardware condition which causes this bit to be set. 0 - No interrupt pending. 1 - Timer interrupt condition occurred. The Timer x Interrupt B Pending bit indicates that an interrupt condition for the related timer subsystem has occurred. Table 51 on page 147 lists the hardware condition which causes this bit to be set. 0 - No interrupt pending. 1 - Timer interrupt condition occurred. The Timer x Interrupt C Pending bit indicates that an interrupt condition for the related timer subsystem has occurred. Table 51 on page 147 lists the hardware condition which causes this bit to be set. 0 - No interrupt pending. 1 - Timer interrupt condition occurred.
The Clock Prescaler Register 2 (CLK2PS) is a word-wide read/write register. The register is split into two 8-bit fields called C3PRSC and C4PRSC. Each field holds the 8-bit clock prescaler compare value for timer subsystems 3 and 4 respectively. The register is cleared at reset. 15 C4PRSC 8 7 C3PRSC 0
C3PRSC
C4PRSC
The Clock Prescaler 3 Compare Value field holds the 8-bit prescaler value for timer subsystem 3. The counter of timer subsystem is incremented each time when the clock prescaler compare value matches the value of the clock prescaler counter. The division ratio is equal to (C3PRSC + 1). The Clock Prescaler 4 Compare Value field holds the 8-bit prescaler value for timer subsystem 4. The counter of timer subsystem is incremented each time when the clock prescaler compare value matches the value of the clock prescaler counter. The division ratio is equal to (C4PRSC + 1).
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23.2.8
Counter Register n (COUNTx)
23.2.10 Duty Cycle/Capture Register n (DTYCAPx) The Duty Cycle/Capture (DTYCAPx) registers are wordwide read/write registers. There are a total of four registers called DTYCAP1 through DTYCAP4, one for each timer subsystem. The registers hold the period compare value in PWM mode or the counter value at the time the last associated capture event occurred. In PWM mode, the register is double buffered. If a new duty cycle compare value is written while the counter is running, the write will not take effect until the counter value matches the previous period compare value or until the counter is stopped. The update takes effect on period boundaries only. Reading may take place at any time and will return the most recent value which was written. The DTYCAPx registers are cleared at reset. 15 DCAPx 0
The Counter (COUNTx) registers are word-wide read/write registers. There are a total of four registers called COUNT1 through COUNT4, one for each of the four timer subsystems. Software may read the registers at any time. Reading the register will return the current value of the counter. The register may only be written if the counter is stopped (i.e. if both TxRUN bits associated with a timer subsystem are clear). The registers are cleared at reset. 15 CNTx 0
23.2.9
Period/Capture Register n (PERCAPx)
The PERCAPx registers are word-wide read/write registers. There are a total of four registers called PERCAP1 through PERCAP4, one for each timer subsystem. The registers hold the period compare value in PWM mode of the counter value at the time the last associated capture event occurred. In PWM mode the register is double buffered. If a new period compare value is written while the counter is running, the write will not take effect until counter value matches the previous period compare value or until the counter is stopped. Reading may take place at any time and will return the most recent value which was written. The PERCAPx registers are cleared at reset. 15 PCAPx 0
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24.0 Register Map
Table 53 is a detailed memory map showing the specific memory address of the memory, I/O ports, and registers. The table shows the starting address, the size, and a brief description of each memory block and register. For detailed information on using these memory locations, see the applicable sections in the data sheet. All addresses not listed in the table are reserved and must not be read or written. An attempt to access an unlisted address will have unpredictable results. the byte-wide and word-wide registers reside at word boundaries (even addresses). Therefore, each byte-wide register uses only the lowest eight bits of the internal data bus. Most device registers are read/write registers. However, some registers are read-only or write-only, as indicated in the table. An attempt to read a write-only register or to write a read-only register will have unpredictable results.
When software writes to a register in which one or more bits Each byte-wide register occupies a single address and can are reserved, it must write a zero to each reserved bit unless be accessed only in a byte-wide transaction. Each word- indicated otherwise in the description of the register. Readwide register occupies two consecutive memory addresses ing a reserved bit returns an undefined value. and can be accessed only in a word-wide transaction. Both Table 53 Detailed Device Mapping Register Name Size Address Access Type Value After Reset Comments
USB Node Registers MCNTRL FAR NFSR MAEV MAMSK ALTEV ALTMSK TXEV TXMSK RXEV RXMSK NAKEV NAKMSK FWEV FWMSK FNH FNL DMACNTRL DMAEV DMAMSK MIR DMACNT DMAERR Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte FF FD80h FF FD88h FF FD8Ah FF FD8Ch FF FD8Eh FF FD90h FF FD92h FF FD94h FF FD96h FF FD98h FF FD9Ah FF FD9Ch FF FD9Eh FF FDA0h FF FDA2h FF FDA4h FF FDA6h FF FDA8h FF FDAAh FF FDACh FF FDAEh FF FDB0h FF FDB2h Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h C0h 00h 00h 00h 00h 1Fh 00h 00h
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Register Name EPC0 TXD0 TXS0 TXC0 RXD0 RXS0 RXC0 EPC1 TXD1 TXS1 TXC1 EPC2 RXD1 RXS1 RXC1 EPC3 TXD2 TXS2 TXC2 EPC4 RXD2 RXS2 RXC2 EPC5 TXD3 TXS3 TXC3 EPC6 RXD3 RXS3 RXC3
Size Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte
Address FF FDC0h FF FDC2h FF FDC4h FF FDC6h FF FDCAh FF FDCCh FF FDCEh FF FDD0h FF FDD2h FF FDD4h FF FDD6h FF FDD8h FF FDDAh FF FDDCh FF FDDEh FF FDE0h FF FDE2h FF FDE4h FF FDE6h FF FDE8h FF FDEAh FF FDECh FF FDEEh FF FDF0h FF FDF2h FF FDF4h FF FDF6h FF FDF8h FF FDFAh FF FDFCh FF FDFEh DMA Controller
Access Type Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write
Value After Reset 00h
Comments
08h 00h XXh 00h 00h 00h XXh 1Fh 00h 00h XXh 00h 00h 00h XXh 1Fh 00h 00h XXh 00h 00h 00h XXh 1Fh 00h 00h XXh 00h 00h
ADCA0
Double Word
FF F800h
Read/Write
0000 0000h
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Register Name
Size Double Word Double Word Double Word Word Word Word Byte Double Word Double Word Double Word Double Word Word Word Word Byte Double Word Double Word Double Word Double Word Word Word Word Byte Double Word Double Word Double Word Double Word
Address
Access Type Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write
Value After Reset 0000 0000h 0000 0000h 0000 0000h 0000h 0000h 0000h 00h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000h 0000h 0000h 00h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000h 0000h 0000h 00h 0000 0000h 0000 0000h 0000 0000h 0000 0000h
Comments
ADRA0 ADCB0 ADRB0 BLTC0 BLTR0 DMACNTL0 DMASTAT0 ADCA1 ADRA1 ADCB1 ADRB1 BLTC1 BLTR1 DMACNTL1 DMASTAT1 ADCA2 ADRA2 ADCB2 ADRB2 BLTC2 BLTR2 DMACNTL2 DMASTAT2 ADCA3 ADRA3 ADCB3 ADRB3 www.national.com
FF F804h FF F808h FF F80Ch FF F810h FF F814h FF F81Ch FF F81Eh FF F820h FF F824h FF F828h FF F82Ch FF F830h FF F834h FF F83Ch FF F83Eh FF F840h FF F844h FF F848h FF F84Ch FF F850h FF F854h FF F85Ch FF F85Eh FF F860h FF F864h FF F868h FF F86Ch 154
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Register Name BLTC3 BLTR3 DMACNTL3 DMASTAT3
Size Word Word Word Byte
Address FF F870h FF F874h FF F87Ch FF F87Eh Bus Interface Unit
Access Type Read/Write Read/Write Read/Write Read/Write
Value After Reset 0000h 0000h 0000h 00h
Comments
BCFG IOCFG SZCFG0 SZCFG1 SZCFG2
Byte Word Word Word Word
FF F900h FF F902h FF F904h FF F906h FF F908h
Read/Write Read/Write Read/Write Read/Write Read/Write
07h 069Fh 069Fh 069Fh 069Fh
System Configuration MCFG DBGCFG MSTAT Byte Byte Byte FF F910h FF F912h FF F914h Read/Write Read/Write Read Only 00h 00h ENV2:0 pins
Flash Program Memory Interface FMIBAR FMIBDR FM0WER FM1WER FMCTRL FMSTAT FMPSR FMSTART FMTRAN FMPROG FMPERASE FMMERASE0 FMEND FMMEND FMRCV FMAR0 FMAR1 Word Word Word Word Word Word Byte Byte Byte Byte Byte Byte Byte Byte Byte Word Word FF F940h FF F942h FF F944h FF F946h FF F94Ch FF F94Eh FF F950h FF F952h FF F954h FF F956h FF F958h FF F95Ah FF F95Eh FF F960h FF F962h FF F964h FF F966h Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read Only Read Only 0000h 0000h 0000h 0000h 0000h 0000h 04h 18h 30h 16h 04h EAh 18h 3Ch 04h
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Register Name FMAR2
Size Word
Address FF F968h
Access Type Read Only
Value After Reset
Comments
Flash Data Memory Interface FSMIBAR FSMIBDR FSM0WER FSMCTRL FSMSTAT FSMPSR FSMSTART FSMTRAN FSMPROG FSMPERASE FSMMERASE0 FSMEND FSMMEND FSMRCV FSMAR0 FSMAR1 FSMAR2 Word Word Word Word Word Byte Byte Byte Byte Byte Byte Byte Byte Byte Word Word Word FF F740h FF F742h FF F744h FF F74Ch FF F74Eh FF F750h FF F752h FF F754h FF F756h FF F758h FF F75Ah FF F75Eh FF F760h FF F762h FF F764h FF F766h FF F768h Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read Only Read Only Read Only 0000h 0000h 0000h 0000h 0000h 04h 18h 30h 16h 04h EAh 18h 3Ch 04h
CVSD/PCM Converter CVSDIN CVSDOUT PCMIN PCMOUT LOGIN LOGOUT LINEARIN LINEAROUT CVCTRL CVSTAT CVTEST CVRADD CVRDAT Word Word Word Word Byte Byte Word Word Word Word Word Word Word FF FC20h FF FC22h FF FC24h FF FC26h FF FC28h FF FC2Ah FF FC2Ch FF FC2Eh FF FC30h FF FC32h FF FC34h FF FC36h FF FC38h Write Only Read Only Write Only Read Only Write Only Read Only Write Only Read Only Read/Write Read Only Read/Write Read/Write Read/Write 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
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Register Name CVDECOUT CVENCIN CVENCPR
Size Word Word Word
Address FF FC3Ah FF FC3Ch FF FC3Eh
Access Type Read Only Read Only Read Only
Value After Reset 0000h 0000h 0000h
Comments
Triple Clock + Reset CRCTRL PRSFC PRSSC PRSAC Byte Byte Byte Byte FF FC40h FF FC42h FF FC44h FF FC46h Read/Write Read/Write Read/Write Read/Write 00X0 0110b 4Fh B6h FFh
Power Management PMMCR PMMSR Byte Byte FF FC60h FF FC62h Read/Write Read/Write 00h 0000 0XXXb
Multi-Input Wake-Up WKEDG WKENA WKICTL1 WKICTL2 WKPND WKPCL WKIENA Word Word Word Word Word Word Word FF FC80h FF FC82h FF FC84h FF FC86h FF FC88h FF FC8Ah FF FC8Ch Read/Write Read/Write Read/Write Read/Write Read/Write Write Only Read/Write 00h 00h 00h 00h 00h XXh 00h Bits may only be set; writing 0 has no effect.
General-Purpose I/O ports PBALT PBDIR PBDIN PBDOUT PBWPU PBHDRV PBALTS PCALT PCDIR PCDIN PCDOUT Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte FF FB00h FF FB02h FF FB04h FF FB06h FF FB08h FF FB0Ah FF FB0Ch FF FB10h FF FB12h FF FB14h FF FB16h Read/Write Read/Write Read Only Read/Write Read/Write Read/Write Read/Write Read/Write Read Only Read/Write Read/Write 00h 00h XXh XXh 00h 00h 00h 00h 00h XXh XXh www.national.com
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Register Name PCWPU PCHDRV PCALTS
Size Byte Byte Byte
Address FF FB18h FF FB1Ah FF FB1Ch
Access Type Read/Write Read/Write Read/Write
Value After Reset 00h 00h 00h
Comments
I/O ports with Alternate Functions PGALT PGDIR PGDIN PGDOUT PGWPU PGHDRV PGALTS PHALT PHDIR PHDIN PHDOUT PHWPU PHHDRV PHALTS PIALT PIDIR PIDIN PIDOUT PIWPU PIHDRV PIALTS Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte FF FCA0h FF FCA2h FF FCA4h FF FCA6h FF FCA8h FF FCAAh FF FCACh FF FCC0h FF FCC2h FF FCC4h FF FCC6h FF FCC8h FF FCCAh FF FCCCh FF FEE0h FF FEE2h FF FEE4h FF FEE6h FF FEE8h FF FEEAh FF FEECh Read/Write Read/Write Read Only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read Only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read Only Read/Write Read/Write Read/Write Read/Write 00h 00h XXh XXh 00h 00h 00h 00h 00h XXh XXh 00h 00h 00h 00h 00h XXh XXh 00h 00h 00h
Advanced Audio Interface ARFR ARDR0 ARDR1 ARDR2 ARDR3 ATFR ATDR0 Word Word Word Word Word Word Word FF FD40h FF FD42h FF FD44h FF FD46h FF FD48h FF FD4Ah FF FD4Ch Read Only Read Only Read Only Read Only Read Only Write Only Write Only 0000h 0000h 0000h 0000h 0000h XXXXh 0000h
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Register Name ATDR1 ATDR2 ATDR3 AGCR AISCR ARSCR ATSCR ACCR ADMACR
Size Word Word Word Word Word Word Word Word Word
Address FF FD4Eh FF FD50h FF FD52h FF FD54h FF FD56h FF FD58h FF FD5Ah FF FD5Ch FF FD5Eh
Access Type Write Only Write Only Write Only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write
Value After Reset 0000h 0000h 0000h 0000h 0000h 0004h F003h 0000h 0000h
Comments
Interrupt Control Unit IVCT NMISTAT EXNMI ISTAT0 ISTAT1 IENAM0 IENAM1 Byte Byte Byte Word Word Word Word FF FE00h FF FE02h FF FE04h FF FE0Ah FF FE0Ch FF FE0Eh FF FE10h UART UTBUF URBUF UICTRL USTAT UFRS UMDSL1 UBAUD UPSR UOVR UMDSL2 USPOS Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte FF FE40h FF FE42h FF FE44h FF FE46h FF FE48h FF FE4Ah FF FE4Ch FF FE4Eh FF FE50h FF FE52h FF FE54h Read/Write Read Only Read/Write Read only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write XXh XXh 01h 00h 00h 00h 00h 00h 00h 00h 06h Bits 0:1 read only Read Only Read Only Read/Write Read Only Read Only Read/Write Read/Write 10h 00h XXXX 00X0b 0000h 0000h 0000h 0000h Fixed Addr.
Microwire/SPI interface MWDAT MWCTL1 Word Word FF FE60h FF FE62h Read/Write Read/Write XXXXh 0000h
159
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CP3UB17
Register Name
Size
Address
Access Type
Value After Reset All implemented bits are 0
Comments
MWSTAT
Word
FF FE64h
Read Only
ACCESS.bus
ACBSDA ACBST ACBCST ACBCTL1 ACBADDR ACBCTL2 ACBADDR2 ACBCTL3
Byte Byte Byte Byte Byte Byte Byte Byte
FF FEC0h FF FEC2h FF FEC4h FF FEC6h FF FEC8h FF FECAh FF FECCh FF FECEh
Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write
XXh 00h 00h 00h XXh 00h XXh 00h
Timing and Watchdog TWCFG TWCP TWMT0 T0CSR WDCNT WDSDM Byte Byte Word Byte Byte Byte FF FF20h FF FF22h FF FF24h FF FF26h FF FF28h FF FF2Ah Read/Write Read/Write Read/Write Read/Write Write Only Write Only 00h 00h FFFFh 00h 0Fh 5Fh
Multi-Function Timer TCNT1 TCRA TCRB TCNT2 TPRSC TCKC TCTRL TICTL TICLR Word Word Word Word Byte Byte Byte Byte Byte FF FF40h FF FF42h FF FF44h FF FF46h FF FF48h FF FF4Ah FF FF4Ch FF FF4Eh FF FF50h Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write XXh XXh XXh XXh 00h 00h 00h 00h 00h
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160
CP3UB17
Register Name
Size
Address
Access Type
Value After Reset
Comments
Versatile Timer Unit MODE IO1CTL IO2CTL INTCTL INTPND CLK1PS COUNT1 PERCAP1 DTYCAP1 COUNT2 PERCAP2 DTYCAP2 CLK2PS COUNT3 PERCAP3 DTYCAP3 COUNT4 PERCAP4 DTYCAP4 Word Word Word Word Word Word Word Word Word Word Word Word Word Word Word Word Word Word Word FF FF80h FF FF82h FF FF84h FF FF86h FF FF88h FF FF8Ah FF FF8Ch FF FF8Eh FF FF90h FF FF92h FF FF94h FF FF96h FF FF98h FF FF9Ah FF FF9Ch FF FF9Eh FF FFA0h FF FFA2h FF FFA4h Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
161
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CP3UB17
25.0 Register Bit Fields
The following tables show the functions of the bit fields of the device registers. For more information on using these registers, see the detailed description of the applicable function elsewhere in this data sheet.
USB Registers MCNTRL FAR NFSR MAEV MAMSK ALTEV ALTMSK TXEV TXMSK RXEV RXMSK NAKEV NAKMSK FWEV FWMSK FNH FNL DMACNTRL DMAEV DMAMSK MIR DMACNT DMAERR EPC0 TXD0 TXS0 TXC0 RXD0 RXS0 RXC0 EPC1 TXD1 www.national.com
7
6 Reserved
5
4 HOS
3 NAT AD[6:0]
2 HALT
1 Reserved
0 USBEN
AD_EN Reserved INTR INTR RESUME RESUME RX_EV RX_EV RESET RESET ULD ULD SD5 SD5 NAK NAK SD3 SD3
NSF[1:0] FRAME FRAME EOP EOP TX_EV TX_EV DMA DMA ALT ALT CLKSTB CLKSTB WARN WARN Reserved Reserved
TXUDRRUN[3:0] TXUDRRUN[3:0] RXOVRRUN[3:0] RXOVRRUN[3:0] OUT[3:0] OUT[3:0] RXWARN[3:1] RXWARN[3:1] MF UL RFC Reserved Reserved Reserved FN[7:0] DEN IGNRXTGL DTGL NTGL Reserved ADMA ARDY DMOD DSIZ DSIZ STAT[7:0] DCOUNT[7:0] AEH STALL DEF Reserved TXFD[7:0] Reserved ACK_STAT TX_DONE Red IGN_IN FLUSH DMAERRCNT[6:0]
TXFIFO[3:0] TXFIFO[3:0] RXFIFO[3:0] RXFIFO[3:0] IN[3:0] IN[3:0] TXWARN[3:1] TXWARN[3:1] FN[10:8] Reserved Reserved
DSRC[2:0] DCNT DCNT DERR DERR DSHLT DSHLT
Reserved
EP[3:0]
TCOUNT[4:0] TOGGLE Reserved TX_EN
RXFD[7:0] Res. SETUP TOGGLE RX_LAST FLUSH EP_EN TXFD[7:0] 162 RCOUNT[3:0] IGN_ SETUP IGN_OUT EP[3:0] RX_EN
Reserved STALL Reserved ISO
CP3UB17
USB Registers TXS1 TXC1 EPC2 RXD1 RXS1 RXC1 EPC3 TXD2 TXS2 TXC2 EPC4 RXD2 RXS2 RXC2 EPC5 TXD3 TXS3 TXC3 EPC6 RXD3 RXS3 RXC3
7
6
5
4
3
2 TCOUNT[4:0]
1
0
TX_URUN ACK_STAT TX_DONE IGN_ ISOMSK STALL TFWL[1:0] Reserved ISO RFF EP_EN RXFD[7:0] RX_ERR Reserved STALL SETUP TOGGLE RX_LAST Res. EP_EN TXFD[7:0] TX_URUN ACK_STAT TX_DONE IGN_ ISOMSK STALL TFWL[1:0] Reserved ISO RFF EP_EN RXFD[7:0] RX_ERR Reserved STALL SETUP TOGGLE RX_LAST Reserved EP_EN TXFD[7:0] TX_URUN ACK_STAT TX_DONE IGN_ ISOMSK STALL TFWL[1:0] Reserved ISO RFF EP_EN RXFD[7:0] RX_ERR Reserved SETUP TOGGLE RX_LAST Reserved FLUSH FLUSH FLUSH FLUSH FLUSH FLUSH
TOGGLE
LAST
TX_EN
EP[3:0]
RCOUNT[4:0] IGN_ SETUP Reserved EP[3:0] RX_EN
RFWL[1:0] Reserved ISO
TCOUNT[4:0] TOGGLE LAST TX_EN
EP[3:0]
RCOUNT[4:0] IGN_ SETUP Reserved EP[3:0] RX_EN
RFWL[1:0] Reserved ISO
TCOUNT[4:0] TOGGLE LAST TX_EN
EP[3:0]
RCOUNT[4:0] IGN_ SETUP Reserved RX_EN
RFWL[1:0]
DMAC Registers ADCA ADRA ADCB ADRB BLTC
20..1 6
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Device A Address Counter Device A Address Device B Address Counter Device B Address N/A Block Length Counter
163
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BLTR DMACNTL DMASTAT
N/A N/A Res. INCB ADB N/A INCA ADA
Block Length SW Res. RQ OT DIR IND TCS VLD EO VR ETC CH EN TC
Reserved
CH OVR AC
System Configuration Registers MCFG DBGCFG MSTAT
7
6
5
4 USB_ ENABLE
3
2
1
0
Reserved
MEM_IO_ MISC_IO_ SPEED SPEED
SCLKOE
MCLKOE PLLCLKOE FREEZE
EXIOE ON OENV0
Reserved Reserved DPGM BUSY PGMBUSY OENV2
OENV1
BIU Registers BCFG IOCFG SZCFG0 SZCFG1 SZCFG2
15
12
11
10
9
8
7
6
5
4
3
2
1
0 EWR
Reserved Reserved Reserved Reserved Reserved IPST Res. BW BW BW BW Reserved WBR RBE WBR RBE WBR RBE HOLD HOLD HOLD HOLD WAIT WAIT WAIT WAIT
FRE IPRE IPST Res. FRE IPRE IPST Res. FRE IPRE IPST Res.
TBI Register TMODE
7
6 Reserved
5
4 TSTEN
3 ENMEM
2
1 TMSEL
0
Flash Program Memory Interface Registers FMIBAR FMIBDR FM0WER FM1WER FM2WER FM3WER FMCTRL
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved IBD FM0WE[15:0] FM1WE[15:0] FM2WE[15:0] FM3WE[15:0] Reserved MER PER PE
IBA
IENP DIS LOW Res. CWD ROG VRF PRW
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164
CP3UB17
Flash Program Memory Interface Registers FMSTAT FMPSR FMSTART FMTRAN FMPROG FMPERASE FMMERASE0 FMEND FMMEND FMRCV FMAR0 FMAR1 FMAR2
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved WRPROT RDPROT ISPE CADR15:0 EMPTY
DE FM FM PERR EERR RR FULL BUSY FTDIV[4:0] FTSTART[7:0] FTTRAN[7:0] FTPROG[7:0] FTPER[7:0] FTMER[7:0] FTEND[7:0] FTMEND[7:0] FTRCV[7:0] Res. BOOTAREA
Flash Data Memory Interface Registers FSMIBAR FSMIBDR FSM0WER FSM1WER FSM2WER FSM3WER FSMCTRL FSMSTAT FSMPSR FSMSTART FSMTRAN FSMPROG FSMPERASE FSMMERASE0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved IBD FM0WE[15:0] FM1WE[15:0] FM2WE[15:0] FM3WE[15:0] Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved MER PER PE
IBA
IENP DIS LOW Res. CWD ROG VRF PRW DE FM FM PE RR FULL BUSY RR FTDIV[3:0] FTSTART[7:0] FTTRAN[7:0] FTPROG[7:0] FTPER[7:0] FTMER[7:0] EE RR
165
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Flash Data Memory Interface Registers FSMEND FSMMEND FSMRCV FSMAR0 FSMAR1 FSMAR2
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved Reserved Reserved Reserved WRPROT RDPROT ISPE CADR15:0
FTEND[7:0] FTMEND[7:0] FTRCV[7:0] Res. EMPTY BOOTAREA
CVSD/PCM Registers CVSDIN CVSDOUT PCMIN PCMOUT LOGIN LOGOUT LINEARIN LINEAROUT CVCTRL
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CVSDIN CVSDOUT PCMIN PCMOUT Reserved Reserved LINEARIN LINEAROUT Reserved PCM CO NV CVSD CONV CVS DMA DMA DMA DMA CVS PCM CLK DER PI PO CI CO DINT INT EN RINT CVINST CVF CVE PCM CVN INT F RT CV EN CV NE TB LOGIN LOGOUT
CVSTAT CVTEST CVRADD CVRDAT CVDECOUT CVENCIN CVENCPR
Reserved
CVOUTST Reserved Reserved
TEST ENC DEC _VAL _IN _EN CVRADD[6:0] CVRDAT[15:0] CVDECOUT[15:0] CVENCIN[15:0] CVENCPRT[15:0]
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166
CP3UB17
CLK3RES Registers CRCTRL PRSFC PRSSC PRSAC
7 Reserved Reserved
6
5 POR MODE
4 ACE2
3 ACE1
2 PLLPWD
1 FCLK
0 SCLK
FCDIV SCDIV
ACDIV2
ACDIV1
PMM Register PMMCR PMMSR
7 HCCH
6 HCCM
5 DHC Reserved
4 DMC
3 WBPSM
2 HALT OHC
1 IDLE OMC
0 PSM OLC
MIWU16 Registers WKEDG WKENA WKICTL1 WKICTL2 WKPND WKPCL WKIENA
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WKED WKEN WKINTR7 WKINTR6 WKINTR5 WKINTR4 WKINTR3 WKINTR2 WKINTR1 WKINTR9 WKINTR0 WKINTR8
WKINTR15 WKINTR14 WKINTR13 WKINTR12 WKINTR11 WKINTR10 WKPD WKCL WKIEN
GPIO Registers PxALT PxDIR PxDIN PxDOUT PxWPU PxHDRV PxALTS
7
6
5
4
3
2
1
0
Px Pins Alternate Function Enable Px Port Direction Px Port Output Data Px Port Input Data Px Port Weak Pull-Up Enable Px Port High Drive Strength Enable Px Pins Alternate Function Source Selection
167
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AAI Registers ARSR ATSR ARFR ARDR0 ARDR1 ARDR2 ARDR3 ATFR ATDR0 ATDR1 ATDR2 ATDR3 AGCR AISCR ARSCR ATSCR ACCR ADMACR
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ARSH ATSH ARFH ARDH ARDH ARDH ARDH ATFH ATDH ATDH ATDH ATDH CLK EN AAI IOM2 IFS EN Reserved RXFWM[3:0] TXFWM[3:0] BCPRS[7:0] Reserved ACO[1:0] ACD{2:0] FSL[1:0] TX EIC TX IC CTF CRF IEBC FSS IEFS RX EIC RX IC TX EIP TX IP RX EIP
ARSL ATSL ARFL ARDL ARDL ARDL ARDL ARFL ATDL ATDL ATDL ATDL SCS[1:0] RX IP TX EIE LPB DWL ASS TX IE RX EIE RX IE RX AF
RXDSA[3:0] TXDSA[3:0]
RXSA[3:0] TXSA[3:0]
RXO RXE RXF
TXU TXF TXE TXAE CSS RMD[3:0]
FCPRS[6:0] TMD[3:0]
ICU Registers IVCT ISTAT0 ISTAT1 IENAM0 IENAM1
15 . . . 12 11 . . . 8 Reserved
7 0
6 0
5
4
3
2
1
0
INTVECT[5:0] IST(15:0) IST(31:16) IENA(15:0) IENA(31:16)
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168
CP3UB17
UART Registers UTBUF URBUF UICTRL USTAT UFRS UMDSL1 UBAUD UPSR UOVR UMDSL2 USPOS
7
6
5
4 UTBUF URBUF
3
2
1
0
UEEI Reserved Reserved URTS
UERI UXMIP UPEN UFCE
UETI URB9
UEFCI UBKD
UCTS UERR UXB9 UCKS
UDCTS UDOE USTP UBRK
URBF UFE
UTBE UPE
UPSEL UERD UETD
UCHAR UATN UMOD
UDIV[7:0] UPSC[4:0] Reserved Reserved Reserved USAMP[3:0] UDIV[10:8] UOVSR[3:0] USMD
MWSPI16 Registers MWDAT MWCTL1 MWSTAT
15 . . . 9
8
7
6
5 MWDAT
4
3
2
1
0
SCDV
SCIDL
SCM
EIW
EIR
EIO
ECHO
MOD OVR
MNS RBF
MWEN BSY
Reserved
ACB Registers ACBSDA ACBST ACBCST ACBCTL1 ACBADDR ACBCTL2 ACBADDR2 ACBCTL3
7
6
5
4 DATA
3
2
1
0
SLVSTP
SDAST
BER TGSCL GCMEN
NEGACK TSDA ACK
STASTR GMATCH Reserved ADDR
NMATCH MATCH INTEN
MASTER BB STOP
XMIT BUSY START
ARPMATCH MATCHAF STASTRE SAEN NMINTE
SCLFRQ[6:0] SAEN Reserved ADDR ARPEN
ENABLE
SCLFRQ[8:7]
169
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TWM Registers TWCFG TWCP TWMT0 T0CSR WDCNT WDSDM
15 . . . 8 Reserved Reserved
7
6
5
4
3
2
1
0
Reserved
WDSDME WDCT0I LWDCNT LTWMT0 LTWCP LTWCFG Reserved PRESET MDIV
Reserved Reserved Reserved
Reserved
FRZT0E WDTLD PRESET RSTDATA
T0INTE
TC
RST
MFT16 Registers TCNT1 TCRA TCRB TCNT2 TPRSC TCKC TCTRL TICTL TICLR
15 . . . 8
7
6
5
4 TCNT1 TCRA TCRB TCNT2
3
2
1
0
Reserved Reserved Reserved Reserved Reserved
Reserved Reserved TEN TDIEN TAOUT TCIEN TBEN TBIEN C2CSEL TAEN TAIEN TBEDG TDPND TDCLR
CLKPS C1CSEL TAEDG TCPND TCCLR TMDSEL TBPND TBCLR TAPND TACLR
Reserved
VTU Registers MODE IO1CTL IO2CTL INTCTL INTPND CLK1PS COUNT1 PERCAP1 DTYCAP1 COUNT2 PERCAP2
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TMOD4 P4 POL P7 POL
T8 T7 RUN RUN C4EDG C7EDG
TMOD3 P3 POL P6 POL
T6 T5 RUN RUN C3EDG C6EDG
TMOD2 P2 POL P5 POL
T4 T3 RUN RUN C2EDG C5EDG
TMOD1 P1 POL P5 POL
T2 T1 RUN RUN C1EDG C5EDG
I4DEN I4CEN I4BEN I4AEN I3DEN I3CEN I3BEN I3AEN I2DEN I2CEN I2BEN I2AEN I1DEN I1CEN I1BEN I1AEN I4DPD I4CPD I4BPD I4APD I3DPD I3CPD I3BPD I3APD I2DPD I2CPD I2BPD I2APD I1DPD I1CPD I1BPD I1APD C2PRSC CNT1 PCAP1 DCAP1 CNT2 PCAP2 C1PRSC
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170
CP3UB17
VTU Registers DTYCAP2 CLK2PS COUNT3 PERCAP3 DTYCAP3 COUNT4 PERCAP4 DTYCAP4
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DCAP2 C4PRSC CNT3 PCAP3 DCAP3 CNT4 PCAP4 DCAP4 C3PRSC
171
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CP3UB17
26.0 Electrical Characteristics
26.1 ABSOLUTE MAXIMUM RATINGS
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply voltage (VCC) All input and output voltages with respect to GND* ESD protection level Allowable sink/source current per signal pin TBD -0.5V to +TBDV 2 kV (Human Body Model) 10 mA Total current into IOVCC pins Total current into VCC pins (source) Total current out of GND pins (sink) Latch-up immunity Storage temperature range 200 mA 200 mA 200 mA 200 mA -65C to +150C
Note: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings. * The latch-up tolerance on Access Bus pins 14 and 15 exceeds 150mA.
26.2
DC ELECTRICAL CHARACTERISTICS (Temperature: -40C TA +85C)
Symbol Vcc IOVcc AVcc UVcc VIH VIL Vxl1 Vxh1 Vxl2 Vxh2 Vhys IOH IOL IOLACB IOHW IIL IL IO(Off) Icca1 Icca2
Parameter Digital Logic Supply Voltage I/O Supply Voltage Analog PLL Supply Voltage USB Transceiver Power Supply Logical 1 Input Voltage (except X2CKI) Logical 0 Input Voltage (except X2CKI) X1CKI Low Level Input Voltage X1CKI High Level Input Voltage OSC X2CKI Logical 0 Input Voltage X2CKI Logical 1 Input Voltage Hysteresis Loop Width
a
Conditions
Min 2.25 2.25 2.25 2.97 0.7 IOVcc -0.5
Max 2.75 3.63 2.75 3.63 IOVcc + 0.5 0.3 Vcc 0.3 Vcc Vcc + 0.5 0.3 Vcc Vcc + 0.5
Units V V V V V V V V V V V mA mA mA A
External X1 clock External X1 clock External X2 clock External X2 clock
-0.5 0.7 Vcc -0.5 0.7 Vcc 0.1 IOVcc
Logical 1 Output Current Logical 0 Output Current SDA, SCL Logical 0 Output Current Weak Pull-up Current RESET pin Weak Pull-down Current High Impedance Input Leakage Current Output Leakage Current (I/O pins in input mode) Digital Supply Current Active Mode b Digital Supply Current Active Mode c
VOH = 1.8V, IOVcc = 2.25V VOL = 0.45V, IOVcc = 2.25V VOL = 0.4V, IOVcc = 2.25V VOH = 1.8V, IOVcc =2.25V VIL = 0.45V, IOVcc = 2.25V 0V Vin IOVcc 0V Vout Vcc Vcc = 2.75V, IOVcc=3.63V Vcc = 2.75V, IOVcc=3.63V 172
-1.6 1.6 3.0 -10 0.4 -2.0 -2.0 2.0 2.0 12 8
A A A mA mA
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CP3UB17
Symbol Iccprog Iccps Iccid Iccq
Parameter Digital Supply Current Active Mode d Digital Supply Current Power Save Mode e Digital Supply Current Idle Mode f Digital Supply Current Halt Mode g
Conditions Vcc = 2.75V, IOVcc = 3.63V Vcc = 2.75V, IOVcc =3.63V Vcc = 2.75V, IOVcc = 3.63V Vcc = 2.75V, IOVcc = 3.63V
Min 15 4.0 900 300
Max
Units mA mA A A
a. Guaranteed by design b. Run from internal memory (RAM), Iout = 0 mA, X1CKI = 12 MHz, PLL enabled (4x), internal system clock is 24 MHz, not programming Flash memory c. Waiting for interrupt on executing WAIT instruction, Iout = 0 mA, X1CKI = 12 MHz, PLL enabled (4x), internal system clock is 24 MHz, not programming Flash memory d. Same conditions as Icca1, but programming or erasing Flash memory page e. Running from internal memory (RAM), Iout = 0 mA, XCKI1 = 12 MHz, PLL disabled, X2CKI = 32.768 kHz, device put in power-save mode, Slow Clock derived from XCKI1 f. Iout = 0 mA, XCKI1 = off, X2CKI = 32.768 kHz g. USB switched off (suspend)
26.3
USB TRANSCEIVER ELECTRICAL CHARACTERISTICS (Temperature: -40C TA +85C)
Symbol VDI VCM VSE VOL VOH VOZ CTRN
Parameter Differential Input Sensitivity Differential Common Mode Range Single-Ended Receiver Threshold Output Low Voltage Output High Voltage TRI-STATE Data Line Leakage Transceiver Capacitance
Conditions (D+) - (D-)
Min -0.2 0.8 0.8
Max 0.2 2.5 2.0 0.3
Units V V V V V
RL = 1.5K ohm to 3.6V 2.8 0V < VIN < 3.3V -10
10 20
A pF
173
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26.4
Symbol tSTART tTRAN tPROG tPERASE tMERASE tEND tMEND tRCV tHV tHV
FLASH MEMORY ON-CHIP PROGRAMMING
Parameter Program/Erase to NVSTR Setup Time (NVSTR = Non-Volatile Storage NVSTR to Program Setup Timeb Programming Pulse Width Page Erase Pulse Width
f g d e c a
Conditions
Min 5 10 20 20 200 5 100 1
Max 40 8 4 -
Units s s s ms ms s s s ms ms cycles years
Module Erase Pulse Width NVSTR Hold Time
h
NVSTR Hold Time (Module Erase) Recovery Time
Cumulative Program High Voltage Period For Each Row After Erasei Write/Erase Endurance Data Retention
128K program blocks 8K data block
20,000
25C
100
a. Program erase to NVSTR Setup Time is determined by the following equation: tSTART = Tclk x (FTDIV + 1) x (FTSTART + 1), where Tclk is the System Clock period, FTDIV is the contents of the FMPSR or FSMPSR register, and FTSTART is the contents of the FMSTART or FSMSTART register b. NVSTR to Program Setup Time is determined by the following equation: tTRAN = Tclk x (FTDIV + 1) x (FTTRAN + 1), where Tclk is the System Clock period, FTDIV is the contents of the FMPSR or FSMPSR register, and FTTRAN is the contents of the FMTRAN or FSMTRAN register c. Programming Pulse Width is determined by the following equation: tPROG = Tclk x (FTDIV + 1) x 8 x (FTPROG + 1), where Tclk is the System Clock period, FTDIV is the contents of the FMPSR or FSMPSR register, and FTPROG is the contents of the FMPROG or FSMPROG register d. Page Erase Pulse Width is determined by the following equation: tPERASE = Tclk x (FTDIV + 1) x 4096 x (FTPER + 1), where Tclk is the System Clock period, FTDIV is the contents of the FMPSR or FSMPSR register, and FTPER is the contents of the FMPERASE or FSMPERASE register e. Module Erase Pulse Width is determined by the following equation: tMERASE = Tclk x (FTDIV + 1) x 4096 x (FTMER + 1), where Tclk is the System Clock period, FTDIV is the contents of the FMPSR or FSMPSR register, and FTMER is the contents of the FMMERASE0 or FSMMERASE0 register f. NVSTR Hold Time is determined by the following equation: tEND = Tclk x (FTDIV + 1) x (FTEND + 1), where Tclk is the System Clock period, FTDIV is the contents of the FMPSR or FSMPSR register, and FTEND is the contents of the FMEND or FSMEND register g. NVSTR Hold Time (Module Erase) is determined by the following equation: tMEND = Tclk x (FTDIV + 1) x 8 x (FTMEND + 1), where Tclk is the System Clock period, FTDIV is the contents of the FMPSR or FSMPSR register, and FTMEND is the contents of the FMMEND or FSMMEND register h. Recovery Time is determined by the following equation: tRCV = Tclk x (FTDIV + 1) x (FTRCV + 1), where Tclk is the System Clock period, FTDIV is the contents of the FMPSR or FSMPSR register, and FTRCV is the contents of the FMRCV or FSMRCV register i. Cumulative program high voltage period for each row after erase tHV is the accumulated duration a flash cell is exposed to the programming voltage after the last erase cycle.
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26.5
The RESET and NMI input pins are active during the Power Save mode. In order to guarantee that the Power Save curAll output signals are powered by the digital supply (VCC). rent not exceed 1 mA, these inputs must be driven to a voltTable 54 summarizes the states of the output signals during age lower than 0.5V or higher than VCC - 0.5V. An input the reset state (when VCC power exists in the reset state) voltage between 0.5V and (VCC - 0.5V) may result in power and during the Power Save mode. consumption exceeding 1 mA. Table 54 Output Pins During Reset and Power-Save Signals on a Pin PB7:0 PC7:0 PG5, PG3:0 PH7:0 PI7:0 Reset State (with Vcc) TRI-STATE TRI-STATE TRI-STATE TRI-STATE TRI-STATE Power Save Mode Previous state Previous state Previous state Previous state Previous state Comments I/O ports will maintain their values when entering power-save mode
OUTPUT SIGNAL LEVELS
26.6
CLOCK AND RESET TIMING
Table 55 Clock and Reset Signals
Symbol Figure
Description
Reference Clock Input Signals
Min (ns)
Max (ns)
tX1p tX1h tX1l tX2p tX2h tX2l tIH
56 56 56 56 56 56 57
X1 period X1 high time, external clock X1 low time, external clock X2 perioda X2 high time, external clock X2 low time, external clock Input hold time (NMI, RXD1, RXD2)
Rising Edge (RE) on X1 to next RE on X1 At 2V level (Both Edges) At 0.8V level (Both Edges) RE on X2 to next RE on X2 At 2V level (both edges) At 0.8V level (both edges) After RE on CLK
83.33 (0.5 Tclk) - 5 (0.5 Tclk) - 5 10,000 (0.5 Tclk) - 500 (0.5 Tclk) - 500 0
83.33
Reset and NMI Input Signals tIW tRST tR 57 58 58 NMI Pulse Width RESET Pulse Width Vcc Rise Time NMI Falling Edge (FE) to RE RESET FE to RE 0.1 Vcc to 0.9 Vcc 20 100
a. Only when operating with an external square wave on X2CKI; otherwise a 32 kHz crystal network must be used between X2CKI and X2CKO. If Slow Clock is internally generated from Main Clock, it may not exceed this given limit.
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tX1p
X1CKI
tX1h
tX1l
tX2p
X2CKI
tX2h
tX2l DS095
Figure 56.
Clock Timing
CLK
tlS NMI
tIW
tlH
DS096
Figure 57.
NMI Signal Timing
CLK
tRST RESET
DS097
Figure 58. Non-Power-On Reset
0.9 VCC VCC 0.1 VCC
tR
DS115
Figure 59.
Power-On Reset
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26.7
UART TIMING
Table 56 UART Signals
Symbol Figure
Description
Reference UART Input Signals
Min (ns)
Max (ns)
tIs tIh
60 60
Input setup time RXD (asynchronous mode) Input hold time RXD (asynchronous mode)
Before Rising Edge (RE) on CLK After RE on CLK UART Output Signals
-
tCOv1 tTXD
60 60
TXD output valid (all signals with propagation delay from CLK RE) TXD output valid
After RE on CLK After RE on CLK
40
1 CLK
2
1
2
1
2
1
2
1
2
1
2
tCOv1
tCOv1
TXD
tlS RXD tlH DS098
Figure 60. UART Asynchronous Mode Timing
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26.8
I/O PORT TIMING
Table 57 I/O Port Signals
Symbol Figure
Description
Reference I/O Port Input Signals
Min (ns)
Max (ns)
tIS tIH
61 61
Input Setup Time Input Hold Time
Before Rising Edge (RE) on System Clock After RE on System Clock I/O Port Output Signals
-
tCOv1 tOF
61 61
Output Valid Time Output Floating Time
After RE on System Clock After RE on System Clock
-
1 CLK
2
1
2
1
2
1
2
1
2
1
2
tIS PORTS B, C (input) tlH PORTS B, C (output) tCOv1 tCOv1 DS100 tOF
Figure 61. I/O Port Timing
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26.9
ADVANCED AUDIO INTERFACE (AAI) TIMING
Table 58 Advanced Audio Interface (AAI) Signals
Symbol Figure
Description
Reference AAI Input Signals
Min (ns)
Max (ns)
tRDS tRDH tFSS tFSH
62,64 Receive Data Setup Time 62,64 Receive Data Hold Time 62 62 Frame Sync Setup Time Frame Sync Hold Time
Before Falling Edge (FE) on SRCLK After FE on SRCLK Before Rising Edge (RE) on SRCLK After RE on SRCLK AAI Output Signals
20 20 20 20
-
tCP tCL tCH tFSVH tFSVL tTDV
62 62 62
Receive/Transmit Clock Period Receive/Transmit Low Time Receive/Transmit High Time
RE on SRCLK/SCK to RE on SRCLK/SCK FE on SRCLK/SCK to RE on SRCLK/SCK RE on SRCLK/SCK to FE on SRCLK/SCK RE on SRCLK/SCK to RE on SRFS/SFS RE on SRCLK/SCK to FE on SRFS/SFS RE on SCK to STD Valid
976.6 488.3 488.3 -
20 20 20
62,64 Frame Sync Valid High 62,64 Frame Sync Valid Low 63,65 Transmit Data Valid
tCP
SRCLK
0
1 tCH tCL
2
SRFS tFSVH tFSVL
SRD
0
1
tRDS
tRDH DS116
Figure 62.
ReceiveTiming, Short Frame Sync
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SCK
0
1
2
SFS
STD
0
1
tTDV DS117
Figure 63.
Transmit Timing, Short Frame Sync
SRCLK
0
1
2
N
SRFS tFSVH tFSVL
SRD
0
1
tRDS
tRDH DS118
Figure 64. Receive Timing, Long Frame Sync
SCK
0
1
2
N
SFS
STD
0
1
tTDV DS119
Figure 65.
Transmit Timing, Long Frame Sync
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26.10
MICROWIRE/SPI TIMING
Table 59 Microwire/SPI Signals
Symbol Figure
Description
Reference Microwire/SPI Input Signals
Min (ns)
Max (ns)
tMSKh tMSKl
66 66 66
Microwire Clock High Microwire Clock Low
At 2.0V (both edges) At 0.8V (both edges) SCIDL bit = 0; Rising Edge (RE) MSK to next RE MSK SCIDL bit = 1; Falling Edge (FE) MSK to next FE MSK After MWCS goes inactive Before MWCS goes active SCIDL bit = 0: After FE MSK SCIDL bit = 1: After RE MSK SCIDL bit = 0: Before RE MSK SCIDL bit = 1: Before FE MSK Normal Mode: After RE MSK Alternate Mode: After FE MSK Normal Mode: After RE MSK Alternate Mode: After FE MSK Normal Mode: Before RE MSK Alternate Mode: Before FE MSK Microwire/SPI Output Signals
80 80
-
tMSKp 67 tMSKh tMSKs 66 66 66 tMCSh 67 66 tMCSs 67 66
Microwire Clock Period
200 40 80 40 80 0 40 80 -
MSK Hold (slave only) MSK Setup (slave only)
MWCS Hold (slave only)
MWCS Setup (slave only)
Microwire Data In Hold (master) 68 tMDIh 66 Microwire Data In Hold (slave) 68 66 tMDIs 68 Microwire Data In Setup
tMSKh tMSKl
66 66 66
Microwire Clock High Microwire Clock Low
At 2.0V (both edges) At 0.8V (both edges) SCIDL bit = 0: Rising Edge (RE) MSK to next RE MSK SCIDL bit = 1: Falling Edge (FE) MSK to next FE MSK Data Out Bit #7 Valid After RE on MCSn Normal Mode: After FE MSK Alternate Mode: After RE MSK After FE on MWCS
40 40
-
tMSKp 67 tMSKd tMDOf 66 66 66 tMDOh 67 tMDOnf 70
Microwire Clock Period
100 0.5 tMSK 1.5 tMSK 25 0.0
MSK Leading Edge Delayed (master only) Microwire Data Float b (slave only)
Microwire Data Out Hold
Microwire Data No Float (slave only)
0
25
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Table 59 Microwire/SPI Signals Symbol Figure Description Reference Normal Mode: After FE on MSK Alternate Mode: After RE on MSK Propagation Time Value is the same in all clocking modes of the Microwire Min (ns) Max (ns)
tMDOv
66
Microwire Data Out Valid
25
tMITOp
70
MDODI to MDIDO (slave only)
25
tMSKp
MSK tMSKh tMSKl
tMSKs
tMSKhd
Data In
msb
lsb
tMDls
tMDlh
MDIDO (slave) tMDOf
msb tMDOv tMDOh
lsb
tMDOff
MDODI (master)
msb
lsb
tMSKd MCS (slave) tMCSs tMCSh
DS101
Figure 66.
Microwire Transaction Timing, Normal Mode, SCIDL = 0
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tMSKp
MSK tMSKh tMSKs tMSKh tMSKhd
Data In
msb
lsb
tMDls
tMDlh
MDIDO (slave) tMDOf
msb tMDOv tMDOh
lsb tMDOf
MDODO (master)
msb
lsb
MCS (slave)
tMCSs
tMCSh DS102
Figure 67.
Microwire Transaction Timing, Normal Mode, SCIDL = 1
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tMSKp
MSK tMSKs tMSKh tMSKl tMSKhd
Data In
msb
lsb
tMDls
tMDlh
MDIDO (slave) tMDOf
msb
lsb
tMDOv tMDOh
tMDOf
MDODO (master)
msb
lsb
MCS (slave) tMCSs tMCSh DS103
Figure 68. Microwire Transaction Timing, Alternate Mode, SCIDL = 0
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CP3UB17
tMSKp
MSK tMSKhd tMSKs tMSKh Data In msb tMSKh lsb
tMDls
tMDlh
MDIDO (slave) tMDOf
msb
lsb
tMDOv tMDOh tMDOff
MDODI (master)
msb
lsb
tSKd MCS (slave only)
tMCSs
tMCSh
DS104
Figure 69. Microwire Transaction Timing, Alternate Mode, SCIDL = 1
tMSKp
MSK
tMSKs
tMSKhd tMSKh tMSKl
MDODI (slave) tMDls tMITOp
Dl msb tMDlh
Dl lsb
tMITOp
MDIDO (slave) tMDOnf
DO msb
DO lsb
tMDOf
MCS
tMCSs
tMCSh
DS105
Figure 70. Microwire Transaction Timing, Data Echoed to Output, Normal Mode, SCIDL = 0, ECHO = 1, Slave Mode
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26.11
ACCESS.BUS TIMING
Table 60 ACCESS.bus Signals
Symbol Figure
Description
Reference ACCESS.bus Input Signals
Min (ns)
Max (ns)
tBUFi tCSTOsi tCSTRhi tCSTRsi tDHCsi tDLCsi tSCLfi tSCLri tSCLlowi tSCLhighi tSDAfl tSDAri tSDAhi tSDAsi
72 72 72 72 73 72 71 71 74 74 71 71 74 74
Bus free time between Stop and Start Condition SCL setup time SCL hold time SCL setup time Data High setup time Data Low setup time SCL signal Rise time SCL signal Fall time SCL low time SCL high time SDA signal Fall time SDA signal Rise time SDA hold time SDA setup time After SCL FE Before SCL RE ACCESS.bus Output Signals After SCL Falling Edge (FE) After SCL RE Before Stop Condition After Start Condition Before Start Condition Before SCL Rising Edge (RE) Before SCL RE
tSCLhigho (8 x tCLK) - tSCLri (8 x tCLK) - tSCLri (8 x tCLK) - tSCLri 2 x tCLK 2 x tCLK 16 x tCLK 16 x tCLK 0 2 x tCLK
300 1000 300 1000 -
tBUFo tCSTOso tCSTRho tCSTRso tDHCso tDLCso tSCLfo tSCLro tSCLlowo tSCLhigh
o
72 72 72 73 73 72 71 71 74 74 71 71 74 74
Bus free time between Stop and Start Condition SCL setup time SCL hold time SCL setup time Data High setup time Data Low setup time SCL signal Fall time SCL signal Rise time SCL low time SCL high time SDA signal Fall time SDA signal Rise time SDA hold time SDA valid time After SCL F.E. After SCL F.E. After SCL F.E. After SCL R.E. Before Stop Condition After Start Condition Before Start Condition Before SCL R.E. Before SCL R.E.
tSCLhigho tSCLhigho tSCLhigho tSCLhigho tSCLhigho -tSDAro tSCLhigho -tSDAfo 300c -d (K x tCLK) -1e (K x tCLK) -1e 300
-
tSDAfo tSDAro tSDAho tSDAvo
(7 x tCLK) - tSCLfo (7 x tCLK) + tRD
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0.7VCC SDA 0.3VCC
0.7VCC 0.3VCC
tSDAr
tSDAf
0.7VCC SCL 0.3VCC
0.7VCC 0.3VCC
tSCLr
tSCLf
Note: In the timing tables the parameter name is added with an "o" for output signal timing and "i" for input signal timing. DS106
Figure 71. ACB Signals (SDA and SCL) Timing
Stop Condition
Start Condition
SDA
tDLCs
SCL
tCSTOs
tBUF
tCSTRh
Note: In the timing tables the parameter name is added with an "o" for output signal timing and "i" for input signal timing.
DS107
Figure 72.
ACB Start and Stop Condition Timing
Start Condition
SDA
SCL
tCSTRs tDHCs
tCSTRh
Note: In the timing tables the parameter name is added with an "o" for output signal timing and "i" for input signal timing. DS108
Figure 73.
ACB Start Condition Timing
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SDA
tSDAsi SCL
tSCAvo tSDAh
tCSLlow
tSCLhigh
Note: In the timing tables the parameter name is added with an "o" for output signal timing and "i" for input signal timing. unless the parameter already includes the suffix. DS109
Figure 74. ACB Data Timing
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CP3UB17
26.12
USB PORT AC CHARACTERISTICS
Table 61 USB Port Signals
Symbol TR TF TRFM VCRS ZDRV Rise Time Fall Time
Description
Conditionsa CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF
Min 4 4 90 1.3 28
Typ
Max 20 20 110 2.0 43
Units ns ns % V ohms
Fall/Rise Time Matching (TR/TF) Output Signal Crossover Voltage Driver Output Impedance
a. Waveforms measured at 10% to 90%.
26.13
MULTI-FUNCTION TIMER (MFT) TIMING
Table 62 Multi-Function Timer Input Signals
Symbol tTAH tTAL
Figur e 75 75
Description TA High Time TA Low Time
Reference Rising Edge (RE) on CLK RE on CLK
Min (ns) TCLK + 5 TCLK + 5
Max (ns)
CLK tTAL /tTBL tTAL /tTBH
TA/TB
DS169
Figure 75.
Multi-Function Timer Input Timing
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26.14
VERSATILE TIMING UNIT (VTU) TIMING
Table 63 Versatile Timing Unit Input Signals
Symbol tTIOH tTIOL
Figur e 75 75
Description TIOx Input High Time TIOx Input Low Time
Reference Rising Edge (RE) on CLK RE on CLK
Min (ns) 1.5 x TCLK + 5ns 1.5 x TCLK + 5ns
Max (ns)
CLK tTIOL tTIOH
TIOx
DS110
Figure 76. Versatile Timing Unit Input Timing
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CP3UB17
26.15
EXTERNAL BUS TIMING
Table 64 External Bus Signals Reference External Bus Input Signals Min (ns) Max (ns)
Symbol Figure
Description
t1
77, Input Setup Time 79, D[15:0] 80, 81 77, Output Hold Time 79, D[15:0] 80, 81
Before Rising Edge (RE) on CLK
8
t2
After RE on CLK External Bus Output Signals
0
t3
77, 78
Output Valid Time D[15:0]
After RE on CLK
8
t4
77, Output Valid Time 78, A[21:0] (CP3BT10) 79, A[22:0] (CP3BT13) 80, 81 77, 78, 79, 80, 81 77, 78 79 77 77 Output Active/Inactive Time RD SEL[1:0] SELIO Output Active/Inactive Time WR[1:0] Minimum Inactive Time RD Output Float Time D[15:0] Minimum Delay Time
After RE on CLK
8
t5
After RE on CLK
8
t6 t7 t8 t9 t10 t11
After RE on CLK At 2.0V After RE on CLK From RD Trailing Edge (TE) to D[15:0] driven From RD TE to SELn Leading Edge (LE) From SELx TE to SELy LE Tclk - 4 0 0 Tclk - 4
0.5 Tclk + 8
8
77, 78 Minimum Delay Time 78 Minimum Delay Time
t12
Output Hold Time A22 (CP3BT13 only) 77, A[21:0] 78, D[15:0] 79, RD 80, 81 SEL[2:0] SELIO 77, 78 Output Hold Time WR[1:0]
After RE on CLK
0
t13
After RE on CLK
0.5 Tclk - 3
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Normal Read Bus State CLK t4 A[21:0] A22 ('13 only) T1 T2 T1
Early Write T2 T3 T1
Normal Read T2
t4, t12
SELx t5, t12 SELy (y x) t2 t3 D[15:0] t5, t12 RD t5, t12 t9 t6, t13 t6, t13 WR[1:0] In Out t8, t12 In t1 t5, t12 t5, t12 t5, t12
DS124
Figure 77. Early Write Between Normal Read Cycles (No Wait States)
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Normal Read
Late Write
Normal Read
Bus State CLK
T1
T2
T1
T2
T1
T2
t4, t12 A[21:0] A22 ('13 only) t5, t12 SELx (y x) t11 SELy (y x) t5, t12 t3 D[15:0] In Out
t4, t12
t5, t12
t5, t12
t8, t12 In
t10 RD t9 t6, t13 WR[1:0] t6, t13
t5, t12 t5, t12
DS125
Figure 78. Late Write Between Normal Read Cycles (No Wait States)
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Normal Read Bus State CLK t4, t12 t4, t12 T1 T2 T2B T1
Normal Read T2 T2B
t4 A[21:0] A22 ('13 only)
t5, t12 SELx (y x)
t5, t12
t5, t12 SELy (y x)
t5, t12
t2 t1 t2 t1 In In In In
D[15:0]
t5, t12 RD t5, t12 t7
WR[1:0]
DS126
Figure 79.
Consecutive Normal Read Cycles (Burst, No Wait States)
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CP3UB17
Bus State CLK
T1
TW
T2
TH
t4, t12 t4 A21:0 A22 ('13 only) t5, t12 t5, t12 SELn, SELIO t2 t1 D[15:0] t5, t12 t5, t12 RD
WR[1:0]
DS127
Figure 80. Normal Read Cycle (Wait Cycle Followed by Hold Cycle)
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Fast Read Bus State CLK t4, t12 Tidle T1-2 T1
Early Write T2 T3
Fast Read T1-2 T1
t4 A[21:0] A22 ('13 only)
SELx (y x)
t5, t12 t5, t12
SELy (y x)
t1 t2
D[15:0]
In
Out
In
RD t5, t12 t5, t12 WR[1:0]
DS128
Figure 81.
Early Write Between Fast Read Cycles
27.0 Revision History
Table 65 Revision History (Continued) Table 65 Revision History Date 10/14/02 10/16/02 Major Changes From Previous Version Original release of full CP3UB17 datasheet. Corrections to flash memory programming sequence and MFT block diagrams. Numerous minor corrections. Added more description to AAI section. Added external reset circuit. Fixed problems with figures. Converted to new data sheet format. Removed TB functionality from MFT section. 1/13/03 Date Major Changes From Previous Version Removed erroneous warning to always write the IOCFG register with bit 1 set. Alternate clock source for Advanced Audio Interface changed to Aux1 clock. Changed warning about clock glitches to say Microwire interface must be disabled when modifying bits in MWCTL1 register. Changed bit settings which occur in step 2 of the sequence of ACCESS.bus slave mode address match or global match. Timer Mode Control Register bit 3 is reserved and bit 2 is TAEDG. Bit 7 is the TEN bit (a bit description has been added). Polarity of all of the bits in the INTCTL register has been inverted. Updated DC specifications. Fixed errors in Microwire bit and pin names. Changed UART pin names to TXD and RXD. Added Section 11.6 "Auxiliary Clocks". Changed diagram of I/O Port Pin Logic (Section 14).
11/11/02
11/21/02
5/20/03
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28.0 Device Pinouts
PG3/CTS/WUI13 PG2/RTS/WUI12 PG5/SRFS/NMI
IOVCC
UGND
UVCC
ENV2
SEL0
GND
TMS
TDO
RDY
SDA
TCK
SCL
PC7
PC6
PC5
PC4
PC3
PC2
PC1
TDI
D+
D-
SEL1 SEL2 SELIO A21 A20 PH0/MSK/TIO1 PH1/MDIDO/TIO2 PH2/MDODO/TIO3 PH3/MWCS/TIO4 ENV0 IOVCC GND VCC GND RESET RD WR0 WR1 A19 A18 A17 A16 A15 PH4/SCK/TIO5 PH5/SFS/TIO6 1
PC0 PG1/TXD/WUI11 PG0/RXD/WUI10 PI7/TA PI6/WUI9 PI5 PI4 PI3 IOVCC GND PB7 PB6
CP3UB17
PB5 PB4 PB3 PB2 PB1 PB0 PI2/SRCLK PI1 PI0 A0 A1 A2 A3
PH6/STD/TIO7
PH7/SRD/TIO8
ENV1
A9
X2CKI
X2CKO
AVCC
AGND
IOVCC
X1CKO
X1CKI
A14
A13
A12
A11
A10
VCC
GND
GND
NC
A8
A7
A6
A5
A4
DS134
Figure 82. CP3UB17 in the 100-pin LQFP Package (Top View)
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PG3/CTS/WUI13
PG2/RTS/WUI12
PG5/SRFS/NMI
IOVCC
UGND
UVCC
GND
TMS
TDO
RDY
TCK
TDI
D+
D-
PH0/MSK/TIO1 PH1/MDIDO/TIO2 PH2/MDODI/TIO3 PH3/MWCS/TIO4 ENV0 VCC GND RESET PH4/SCK/TIO5 PH5/SFS/TIO6 1
PG1/TXD/WUI11 PG0/RXD/WUI10 PI7/TA PI6/WUI9 PI5 PI4 PI3 PI2/SRCLK PI1 PI0
CP3UB17
PH6/STD/TIO7
ENV1
X2CKI
X1CKI
VCC
AVCC
X2CKO
PH7/SRD/TIO8
X1CKO
GND
AGND
IOVCC
GND
NC
DS136
Figure 83. CP3UB17 in the 48-pin CSP Package (Top View)
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CP3UB17
29.0 Physical Dimensions (millimeters) unless otherwise noted
Figure 84.
100-Pin LQFP Package
Figure 85. 48-Pin CSP Package
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CP3UB17 Connectivity Processor with USB Interface
LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
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