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PIC14000
EPROM Memory Programming Specification
This document includes the programming specifications for the following devices:
* PIC14000
Pin Diagram
PDIP, SOIC, SSOP, Windowed CERDIP
RA1/AN1 *1 2 3 4 5 6 7 8 9 10 11 12 13 28 27 26 25 24 23 22 21 20 19 18 17 16 RA2/AN2 RA3/AN3 RD4/AN4 RD5/AN5 RD6/AN6 RD7/AN7 CDAC SUM VSS RC0/LDACA RC1/CMPA RC2 RC3/T0CKI
1.0
PROGRAMMING THE PIC14000
RA0/AN0 RD3/LDACB RD2/CMPB RD1/SDAB RD0/SCLB OSC2/CLKOUT OSC1/PBTN VDD VREG RC7/SDAA RC6/SCLA RC5 MCLR/VPP
PIC14000
The PIC14000 can be programmed using a serial method. In serial mode the PIC14000 can be programmed while in the users system. This allows for increased design flexibility. This programming specification applies to PIC14000 devices in all packages.
1.1
Hardware Requirements
The PIC14000 requires two programmable power supplies, one for VDD (2.0V to 6.5V recommended) and one for VPP (12V to 14V).
Note:
Peripheral pinout functions are not shown (see data sheets for full pinout information).
1.2
Programming Mode
The programming mode for the PIC14000 allows programming of user program memory, configuration word, and calibration memory.
PIN DESCRIPTIONS (DURING PROGRAMMING): PIC14000
During Programming Pin Name RC6 RC7 MCLR/VPP VDD VSS Pin Name CLOCK DATA VPP VDD VSS Pin Type I I/O P P P Pin Description Clock input Data input/output Programming Power Power Supply Ground
Legend: I = Input, O = Output, P = Power
(c) 1996 Microchip Technology Inc.
DS30555A-page 1
This document was created with FrameMaker 4 0 4
PIC14000
2.0
2.1
PROGRAM MODE ENTRY
User Program Memory Map
The program and calibration memory space extends from 0x000 to 0xFFF (4096 words). Table 2-1 shows actual implementation of program memory in the PIC14000.
TABLE 2-1:
IMPLEMENTATION OF PROGRAM AND CALIBRATION MEMORY IN THE PIC14000P
Memory Space 0x000-0xFBF 0xFC0 -0xFFF Access to Memory PC<12:0> PC<12:0>
In programming mode the program memory space extends from 0x0000 to 0x3FFF, with the first half (0x0000-0x1FFF) being user program memory and the second half (0x2000-0x3FFF) being configuration memory. The PC will increment from 0x0000 to 0x1FFF and wrap to 0x0000, or 0x2000 to 0x3FFF and wrap around to 0x2000 (not to 0x0000). Once in configuration memory, the highest bit of the PC stays a '1', thus always pointing to the configuration memory. The only way to point to user program memory is to reset the part and reenter program/verify mode, as described in Section 2.2. In the configuration memory space, 0x2000-0x20FF are utilized. When in configuration memory, as in the user memory, the 0x2000-0x2XFF segment is repeatedly accessed as PC exceeds 0x2XFF (see Figure 2-1). A user may store identification information (ID) in four ID locations. The ID locations are mapped in [0x2000 : 0x2003]. All other locations are reserved and should not be programmed. The ID locations read out normally, even after code protection. To understand how the devices behave, refer to Table 4-1. To understand the scrambling mechanism after code protection, refer to Section 4.1.
Area Program Calibration
When the PC reaches address 0xFFF, it will wrap around and address a location within the physically implemented memory (see Figure 2-1).
DS30555A-page 2
(c) 1996 Microchip Technology Inc.
EPROM Memory Programming Specification
FIGURE 2-1: PROGRAM MEMORY MAPPING
0
Program
2000 2001 2002 2003 2004 2005 2006
ID Location ID Location ID Location ID Location Reserved Reserved Reserved
0FBF 0FC0
Calibration
0FFF
Reserved
2007 Configuration Word
1FFF 2000
Test
20FF
Reserved
3FFF
(c) 1996 Microchip Technology Inc.
DS30555A-page 3
PIC14000
2.2 Program/Verify Mode
The program/verify mode is entered by holding pins RC6 and RC7 low while raising MCLR pin from VIL to VIHH (high voltage). Once in this mode the user program memory and the configuration memory can be accessed and programmed in serial fashion. The mode of operation is serial, and the memory that is accessed is the user program memory. RC6 and RC7 are both Schmitt Trigger inputs in this mode. The sequence that enters the device into the programming/verify mode places all other logic into the reset state (the MCLR pin was initially at VIL). This means that all I/O are in the reset state (High impedance inputs). Note: The MCLR pin should be raised as quickly as possible from VIL to VIHH. This is to ensure that the device does not have the PC incremented while in valid operation range. PROGRAM/VERIFY OPERATION and load) are specified to have a minimum delay of 1s between the command and the data. After this delay the clock pin is cycled 16 times with the first cycle being a start bit and the last cycle being a stop bit. Data is also input and output LSB first. Therefore, during a read operation the LSB will be transmitted onto pin RC7 on the rising edge of the second cycle, and during a load operation the LSB will be latched on the falling edge of the second cycle. A minimum 1s delay is also specified between consecutive commands. All commands are transmitted LSB first. Data words are also transmitted LSB first. The data is transmitted on the rising edge and latched on the falling edge of the clock. To allow for decoding of commands and reversal of data pin configuration, a time separation of at least 1s is required between a command and a data word (or another command). The commands in Table 2-2. 2.2.1.1 that are available are listed
LOAD CONFIGURATION
2.2.1
The RB6 pin is used as a clock input pin, and the RB7 pin is used for entering command bits and data input/output during serial operation. To input a command, the clock pin (RC6) is cycled six times. Each command bit is latched on the falling edge of the clock with the least significant bit (LSB) of the command being input first. The data on pin RC7 is required to have a minimum setup and hold time (see AC/DC specs) with respect to the falling edge of the clock. Commands that have data associated with them (read
After receiving this command, the program counter (PC) will be set to 0x2000. By then applying 16 cycles to the clock pin, the chip will load 14-bits a "data word" as described above, to be programmed into the configuration memory. A description of the memory mapping schemes for normal operation and configuration mode operation is shown in Figure 2-1. After the configuration memory is entered, the only way to get back to the user program memory is to exit the program/verify test mode by taking MCLR low (VIL).
TABLE 2-2:
COMMAND MAPPING
Command Mapping (MSB ... LSB) Data
0 0 0 0 0 0 Load Configuration 0, data(14), 0 0 0 0 0 1 0 Load Data 0, data(14), 0 0 0 0 1 0 0 Read Data 0, data(14), 0 0 0 0 1 1 0 Increment Address 0 0 1 0 0 0 Begin programming 0 0 1 1 1 0 End Programming Note: The CPU clock must be disabled during in-circuit programming (to avoid incrementing the PC).
DS30555A-page 4
(c) 1996 Microchip Technology Inc.
EPROM Memory Programming Specification
FIGURE 2-2: PROGRAM FLOW CHART - PIC14000 PROGRAM MEMORY AND CALIBRATION
Start
Set VDD = VDDP*
N=0 No Program Cycle N > 25 Yes Report Programming Failure
Read Data Command
N=N+1 N=# of Program Cycles No
Increment Address Command
Data Correct? Yes Apply 3N Additional Program Cycles
Program Cycle No Load Data Command
All Locations Done? Yes Verify all Locations @ VDD min.* VPP = VIHH2
Begin Programming Command
Wait 100 s Data Correct? Yes Verify all Locations @ VDD max. VPP = VIHH2 No Report Verify @ VDD min. Error End Programming Command
Data Correct? Yes Done
No
Report Verify @ VDD max. Error
* VDDP = VDD range for programming (typically 4.75V - 5.25V). VDDmin = Minimum VDD for device operation. VDDmax = Maximum VDD for device operation.
(c) 1996 Microchip Technology Inc.
DS30555A-page 5
PIC14000
FIGURE 2-3: PROGRAM FLOW CHART - PIC14000 CONFIGURATION WORD & ID LOCATIONS
Start
Load Configuration Command
N=0
No
Program ID Loc?
Yes Program Cycle
Read Data Command
Increment Address Command
N=N+1 N=# of Program Cycles
No Data Correct? Yes
No
Address = 2004 Yes
No
N > 25 Yes
Increment Address Command
Report ID Configuration Error
Apply 3N Program Cycles
Increment Address Command
Increment Address Command
Program Cycle 100 Cycles
Read Data Command
No
Data Correct? Yes
Report Program ID/Config. Error No Done Yes Data Correct?
No
Data Correct? Yes Set VDD = VDDmax VDDmax Read Data Command Set VPP = VIHH2
Set VDD = VDDmin VDDmin Read Data Command Set VPP = VIHH2
DS30555A-page 6
(c) 1996 Microchip Technology Inc.
EPROM Memory Programming Specification
2.2.1.2 LOAD DATA
2.3
After receiving this command, the chip will load in a 14-bit "data word" when 16 cycles are applied, as described previously. A timing diagram for the load data command is shown in Figure 5-1. 2.2.1.3 READ DATA
Programming Algorithm Requires Variable VDD
The PIC14000 uses an intelligent algorithm. The algorithm calls for program verification at VDDmin as well as VDDmax. Verification at VDDmin guarantees good "erase margin". Verification at VDDmax guarantees good "program margin". The actual programming must be done with VDD in the VDDP range (4.75 - 5.25V). VDDP = VCC range required during programming. VDDmin = minimum operating VDD spec for the part. VDDmax = maximum operating VDD spec for the part. Programmers must verify the PIC14000 at its specified VDDmax and VDDmin levels. Since Microchip may introduce future versions of the PIC14000 with a broader VDD range, it is best that these levels are user selectable (defaults are ok). Note: Any programmer not meeting these requirements may only be classified as "prototype" or "development" programmer but not a "production" quality programmer.
After receiving this command, the chip will transmit data bits out of the memory currently accessed starting with the second rising edge of the clock input. The RC7 pin will go into output mode on the second rising clock edge, and it will revert back to input mode (hi-impedance) after the 16th rising edge. A timing diagram of this command is shown in Figure 5-2. 2.2.1.4 INCREMENT ADDRESS
The PC is incremented when this command is received. A timing diagram of this command is shown in Figure 5-3. 2.2.1.5 BEGIN PROGRAMMING
A load command (load configuration or load data) must be given before every begin programming command. Programming of the appropriate memory (test program memory or user program memory) will begin after this command is received and decoded. Programming should be performed with a series of 100s programming pulses. A programming pulse is defined as the time between the begin programming command and the end programming command. 2.2.1.6 END PROGRAMMING
After receiving this command, the chip stops programming the memory (configuration program memory or user program memory) that it was programming at the time.
(c) 1996 Microchip Technology Inc.
DS30555A-page 7
PIC14000
3.0 CONFIGURATION WORD
The PIC14000 has several configuration bits. These bits can be programmed (reads '0') or left unprogrammed (reads '1') to select various device configurations. Figure 3-1 provides an overview of configuration bits.
FIGURE 3-1:
Bit Number:
CONFIGURATION WORD BIT MAP
13 12
CPP1
11
CPP0
10
CPP0
9
CPP1
8
CPC
7
CPC
6
F
5
CPP1
4
CPP0
3
PWRTE
2
WDTE
1
F
0
FOSC
PIC14000 CPC
CPP<1:0> 11: All Unprotected 10: N/A 01: N/A 00: All Protected bit 1,6: F Internal trim, factory programmed. DO NOT CHANGE! Program as `1'. Note 1. bit 3: PWRTE, Power Up Timer Enable Bit 0 = Power up timer enabled 1 = Power up timer disabled (unprogrammed) bit 2: WDTE, WDT Enable Bit 0 = WDT disabled 1 = WDT enabled (unprogrammed) FOSC<1:0>, Oscillator Selection Bit 0: HS oscillator (crystal/resonator) 1: Internal RC oscillator (unprogrammed)
bit 0:
Note 1: See Section 4.1.2 for cautions.
DS30555A-page 8
(c) 1996 Microchip Technology Inc.
EPROM Memory Programming Specification
4.0 CODE PROTECTION
The memory space in the PIC14000 is divided into two areas: program space (0-0xFBF) and calibration space (0xFC0-0xFFF). For program space or user space, once code protection is enabled, all protected segments read `0's (or "garbage values") and are prevented from further programming. All unprotected segments, including ID locations and configuration word, read normally. These locations can be programmed. If the CPC bits are set to `1', but the checksum of the calibration memory is 0x0000, the programmer should NOT program locations in the calibration memory space, even if requested to do so by the operator. This would be the case for a new JW device. If the CPC bits are set to `1', and the checksum of the calibration memory is NOT 0x0000, the programmer is allowed to program the calibration space as directed by the operator. The calibration space contains specially coded data values used for device parameter calibration. The programmer may wish to read these values and display them for the operator's convenience. For further information on these values and their coding, refer to AN621 (DS00621B). 4.1.2 REPROGRAMMING CALIBRATION SPACE
4.1
Calibration Space
The calibration space can contain factory-generated and programmed values. For non-JW devices, the CPC bits in the configuration word are set to `0' at the factory, and the calibration data values are write-protected; they may still be read out, but not programmed. JW devices contain the factory values, but DO NOT have the CPC bits set. Microchip does not recommend setting code protect bits in windowed devices to `0'. Once code-protected, the device cannot be reprogrammed. 4.1.1 CALIBRATION SPACE CHECKSUM
The operator should be allowed to read and store the data in the calibration space, for future reprogramming of the device. This procedure is necessary for reprogramming a windowed device, since the calibration data will be erased along with the rest of the memory. When saving this data, Configuration Word <1,6> must also be saved, and restored when the calibration data is reloaded.
The data in the calibration space has its own checksum. When properly programmed, the calibration memory will always checksum to 0x0000. When this checksum is 0x0000, and the checksum of memory [0x0000:0xFBF] is 0x2FBF, the part is effectively blank, and the programmer should indicate such.
4.2
Embedding Configuration Word and ID Information in the Hex File
To allow portability of code, the programmer is required to read the configuration word and ID locations from the hex file when loading the hex file. If configuration word information was not present in the hex file then a simple warning message may be issued. Similarly, while saving a hex file, configuration word and ID information must be included. An option to not include this information may be provided. Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer.
TABLE 4-1:
CODE PROTECT OPTIONS
* Protect calibration memory 0XXXX00XXXXXXX * Protect program memory X0000XXX00XXXX * No code protection 1111111X11XXXX Program Memory Segment Configuration Word (0x2007) Unprotected memory segment Protected memory segment Protected calibration memory ID Locations (0x2000 : 0x2003)
Legend: X = Don't care
R/W in Protected Mode Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Read All 0's, Write Disabled Read Unscrambled, Write Disabled Read Unscrambled, Write Enabled
R/W in Unprotected Mode Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled
(c) 1996 Microchip Technology Inc.
DS30555A-page 9
PIC14000
4.3
4.3.1
Checksum
CHECKSUM CALCULATIONS
The least significant 16 bits of this sum is the checksum. The following table describes how to calculate the checksum for each device. Note that the checksum calculation differs depending on the code protect setting. Since the program memory locations read out differently depending on the code protect setting, the table describes how to manipulate the actual program memory values to simulate the values that would be read from a protected device. When calculating a checksum by reading a device, the entire program memory can simply be read and summed. The configuration word and ID locations can always be read. Note that some older devices have an additional value added in the checksum. This is to maintain compatibility with older device programmer checksums.
Checksum is calculated by reading the contents of the PIC14000 memory locations and adding up the opcodes up to the maximum user addressable location, 0xFBF. Any carry bits exceeding 16-bits are neglected. Finally, the configuration word (appropriately masked) is added to the checksum. Checksum computation for the PIC14000 device is shown in Table 4-2: The checksum is calculated by summing the following: * The contents of all program memory locations * The configuration word, appropriately masked * Masked ID locations (when applicable)
TABLE 4-2:
CHECKSUM COMPUTATION
0x25E6 at 0 and max address
0xFBCB 0xDA4B 0xFBD8
Code Protect
OFF OFF OTP ON
Checksum*
Blank Value
0x2FFD 0x0E7D 0x300A
SUM[0000:0FBF] + CFGW & 0x3FBD SUM[0000:0FBF] + CFGW & 0x3FBD CFGW & 0x3FBD + SUM(IDs)
Legend: CFGW = Configuration Word SUM[A:B] = [Sum of locations a through b inclusive] SUM(ID) = ID locations masked by 0x7F then made into a 28-bit value with ID0 as the most significant byte *Checksum = [Sum of all the individual expressions] MODULO [0xFFFF] + = Addition & = Bitwise AND
DS30555A-page 10
(c) 1996 Microchip Technology Inc.
EPROM Memory Programming Specification
5.0 PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS
AC/DC CHARACTERISTICS AC/DC Timing Requirements for Program/Verify Mode TABLE 5-1:
Standard Operating Conditions Operating Temperature: +10C TA +40C, unless otherwise stated, (25C recommended) Operating Voltage: 4.5V VDD 5.5V, unless otherwise stated. Parameter No. General PD1 PD2 PD3 PD4 PD5 PD6 PD9 PD8 VDDP Supply voltage during programming IDDP Supply current (from VDD) during programming 4.75 - VDDmin 12.75 VDD + 4.0 - 0.8 VDD 0.2 VDD - - - - 5.0 - 5.25 20 VDDmax 13.25 13.5 50 - - mA V V Schmitt Trigger input Schmitt Trigger input V mA V V Note 1 Note 2 Sym. Characteristic Min. Typ. Max. Units Conditions
VDDV Supply voltage during verify VIHH1 Voltage on MCLR/VPP during programming VIHH2 Voltage on MCLR/VPP during verify IPP VIH1 VIL1 Programming supply current (from VPP) (RC6, RC7) input high level (RC6, RC7) input low level
Serial Program Verify P1 P2 P3 P4 P5 TR Tf MCLR/VPP rise time (VSS to VHH) for test mode entry MCLR Fall time - - 100 100 1.0 - - - - - 8.0 8.0 - - - s s ns ns s
Tset1 Data in setup time before clock Thld1 Data in hold time after clock Tdly1 Data input not driven to next clock input (delay required between command/data or command/command) Tdly2 Delay between clock to clock of next command or data Tdly3 Clock to date out valid (during read data) Thld0 Hold time after MCLR
P6 P7 P8
1.0 200 2
- - -
- - -
s ns s
Note 1: Program must be verified at the minimum and maximum VDD limits for the part. Note 2: VIHH must be greater than VDD + 4.5V to stay in programming/verify mode.
(c) 1996 Microchip Technology Inc.
DS30555A-page 11
PIC14000
FIGURE 5-1:
VIHH MCLR/VPP P8 RC6 (CLOCK) RC7 (DATA) 0 P3 P4 100ns min. Reset 1 100ns 0 0 1 100ns 2 3 4 5 6 P6 1s min. 1 2 3 4 5 15
LOAD DATA COMMAND (PROGRAM/VERIFY)
0
0 P5 1s min.
0 P3 P4
0
} }
} }
Program/Verify Test Mode
100ns min.
FIGURE 5-2:
VIHH MCLR/VPP
READ DATA COMMAND (PROGRAM/VERIFY)
100ns P8 1 2 3 4 5 6 P6 1s min. 1 2 3 4 5 15
RC6 (CLOCK) RC7 (DATA) 0 P3 0 P4 100ns 1 0
0
0 P5 1s min.
P7
} }
100ns min. RC7 = output RC7 input
Reset
Program/Verify Test Mode
FIGURE 5-3:
MCLR/VPP
INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY)
VIHH P6 1s min. Next Command 1 2
1 RC6 (CLOCK) RC7 (DATA)
2
3
4
5
6
0
1
1
0
0
0 P5
0
0
P3 P4
1s min.
Program/Verify Test Mode
Reset
} }
100ns min
DS30555A-page 12
(c) 1996 Microchip Technology Inc.
EPROM Memory Programming Specification
NOTES:
(c) 1996 Microchip Technology Inc.
DS30555A-page 13
WORLDWIDE SALES & SERVICE
AMERICAS
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AMERICAS (continued)
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EUROPE
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JAPAN
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All rights reserved. (c) 1996, Microchip Technology Incorporated, USA.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS30555A - page 14
(c) 1996 Microchip Technology Inc.

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