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LXT6234
E-Rate Multiplexer
Datasheet
The LXT6234 E-Rate Multiplexer is a single-chip solution for multiplexing four tributary channels into a single high speed data stream and for demultiplexing a high speed data stream back to four tributary channels. All of the necessary circuitry is integrated into the LXT6234 ERate Multiplexer; there is no need for an external framing device. The LXT6234 E-Rate Multiplexer conforms to both the (ITU) G.742 and (ITU) G.751 multiplexing formats defined by the International Telecommunications Union (ITU; formerly known as CCITT): G.742 recommendation for multiplexing four E1 channels into an E2 frame; and the G.751 recommendation for multiplexing four E2 channels into an E3 frame. The LXT6234 E-Rate Multiplexer also encodes and decodes HDB3 zero suppression line coding used on E1, E2, and E3 signals. The coder and decoder input/output pins are externally accessible, allowing either HDB3 or NRZ (non-return-to-zero) I/O to the multiplexer. The LXT6234 E-Rate Multiplexer can also serve as a five channel HDB3 coder and decoder.
Applications
n E1/E2 Multiplexer (2/8 Mbit/s) n E2/E3 Multiplexer (8/34 Mbit/s) n E1/E3 Multiplexer (2/34 Mbit/s) n Digital Loop Carrier (DLC) Terminal n Add / Drop Multiplexers (ADM) n 4 - to - 1 Non-Standard Multiplexer
Product Features
n Performs four-E1 to one-E2, or four-E2 to one-E3 multiplexing. Five ICs will implement a sixteen-E1 to one-E3 multiplexer. n Fully compliant with the G.742 and G.751 ITU recommendations. Fully compliant with G.703 when used with LXT305/332 Line Interface. n A robust frame-acquisition and frameholding algorithm minimizes frame slippage, acquires and holds frame below 10-2 bit error rate. n Four auxiliary low speed data or flag channels are available via the Stuffing Bits on each tributary channel. n Access to the Alarm bit and the National bit. These can be used as recommended by ITU or for proprietary use. n Five independent HDB3 CODECs allow multiplexer I/O in either HDB3 or NRZ formats. The LXT6234 can also function as a stand alone five-channel HDB3 transcoder.
As of January 15, 2001, this document replaces the Level One document LXT6234 E-Rate Multiplexer Datasheet.
Order Number: 249301-001 January 2001
Information in this document is provided in connection with Intel(R) products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The LXT6234 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) Intel Corporation, 2001 *Third-party brands and names are the property of their respective owners.
Datasheet
E-Rate Multiplexer -- LXT6234
Contents
1.0 2.0 3.0 Block Diagram ............................................................................................................. 5 Conscription.................................................................................................................6 Functional Description...........................................................................................11
3.1 3.2 3.3 3.4 Frame Format......................................................................................................11 HDB3 Codecs......................................................................................................11 HDB3 Decoder Alarms ........................................................................................12 Multiplexer ...........................................................................................................12 3.4.1 Flag Bits .................................................................................................13 3.4.2 Multiplexer Alarms ..................................................................................14 Demultiplexer ......................................................................................................14 3.5.1 Demultiplexer Alarms .............................................................................14
3.5
4.0 5.0
Glossary.......................................................................................................................16 Application Information.........................................................................................17
5.1 E1/E3 Multiplexer Block Diagram........................................................................17 5.1.1 E1 Line Interface ....................................................................................17 5.1.2 LXT6234, E1/E2 Stage...........................................................................17 5.1.3 LXT6234, E3 Stage ................................................................................18
6.0 7.0
Test Specifications ..................................................................................................19 AC Timing Specifications .....................................................................................20
Figures
1 2 3 4 5 6 7 8 9 10 11 12 13 Block Diagram ....................................................................................................... 5 LXT6234 Pin Assignment...................................................................................... 6 Multiplexer Side Block Diagram ..........................................................................12 E2 Frame.............................................................................................................13 E3 Frame.............................................................................................................13 Demultiplexer Side Block Diagram......................................................................15 E1/E3 Multiplexer Block Diagram........................................................................17 HDB3 Encoder and Decoder Timing (Refer to Table 5) ......................................20 Multiplexer Tributary Input Timing (Refer to Table 6) ..........................................20 High Speed Multiplexer Input & Output Timing (Refer to Table 7) ......................21 High Speed Demultiplexer Input & Output Timing (Refer to Table 8)..................22 Chip Enable Timing (Refer to Table 9) ................................................................22 Package Specifications .......................................................................................23
Datasheet
3
LXT6234 -- E-Rate Multiplexer
Tables
1 2 3 4 5 6 7 8 9 10 Input Signals ......................................................................................................... 7 Output Signals....................................................................................................... 9 Absolute Ratings ................................................................................................. 19 DC Characteristics (TA=-40 to +85xC, Vdd=+5V5%, GND=0 V)...................... 19 HDB3 Encoder and Decoder (Refer to Figure 8) ............................................... 20 Multiplexer Tributary Input (Refer to Figure 9) ................................................... 21 High Speed Multiplexer Input & Output (Refer to Figure 10) ............................. 21 High Speed Demultiplexer Input & Output (Refer to Figure 11) ......................... 22 Chip Enable (Refer to Figure 12) ........................................................................ 22 100-Pin Plastic Quad Flat Packs......................................................................... 23
4
Datasheet
E-Rate Multiplexer -- LXT6234
1.0
Block Diagram
Figure 1. Block Diagram
Demultiplexer High Speed NRZ Data Input Clock Mode Select HDB3 Data Input Clock 4 Tributary NRZ Data Inputs 4 Clocks 4 4 Demultiplexer And Timing Control HDB3 Decoder HDB3 Encoder #[1:4] Multiplexer 8 4 HDB3 Pos/Neg Data Input Pairs 4 4 Clocks 4 Force AIS 4 NRZ Data Inputs Service Channels / Ref Clock High Speed Multiplexer Clock NRZ Data Input Clock 4 4 4 HDB3 Decoder #[1:4] 4 4 4 Multiplexer And Timing Control 4 NRZ Data Outputs 4 Bipolar Violation Alarms 4 Elastic Store Alarm Indication High Speed NRZ Data Output Frame Sync Pulse 8 4 4 6 4 Tributary NRZ Data Outputs 4 Clocks Loss Of Signal (LOS) Service Channels / AIS NRZ Data Output Bipolar Violation Alarm 4 HDB3 Pos/Neg Data Output P
Elastic Store
HDB3 Encoder
2
Pos/Neg Data Output Pair
Datasheet
5
LXT6234-- E-Rate Multiplexer
2.0
Conscription
Figure 2. LXT6234 Pin Assignment
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
AUXO3 AUXO2 AUXO1 AUXI4 AUXI3 AUXI2 DLNRZO1 DLCO1 DLNRZO2 DLCO2 DLNRZO3 DLCO3 DLNRZO4 DLCO4 AUXI1 GND VCC RSTN DNAT DAIS CE FLOS DHAISD DHDMXC DHNRZI DSYNC MODE DHBPV DHNRZO n/c
AUXO4 DLNRZI1 DLCI1 DLDPO1 DLDNO1 DLNRZI2 DLCI2 DLDPO2 DLDNO2 GND VCC DLNRZI3 DLCI3 DLDPO3 DLDNO3 DLNRZI4 DLCI4 DLDPO4 DLDNO4 LREFCK
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Revision# Part# LOT# FPO# LXT6234QE XX XXXXXXXXXXXXXX XXXXXXXXX
DHHDB3C DHDNI DHDPI MHDNO MHDPO MHHDB3C MHNRZI n/c MHNRZO MHMUXC GND VCC MSYNC MAIS MNAT MESA4 MESA3 MESA2 MESA1 n/c
Package Topside Markings Marking Part # Rev # Lot # FPO # Definition LXT6234 is the unique identifier for this product family. QE indicates the family member. Identifies the particular silicon "stepping" -- refer to the specification update for additional stepping information. Identifies the batch. Identifies the Finish Process Order.
6
MLDPI1 MLDNI1 MLBPV1 MLNRZO1 MLNRZI1 MLFAIS1 MLCK1 MLDPI2 MLDNI2 MLBPV2 MLNRZO2 MLNRZI2 MLFAIS2 MLCK2 GND VCC MLDPI3 MLDNI3 MLBPV3 MLNRZO3 MLNRZI3 MLFAIS3 MLCK3 MLDPI4 MLDNI4 MLBPV4 MLNRZO4 MLNRZI4 MLFAIS4 MLCK4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Datasheet
E-Rate Multiplexer -- LXT6234
Table 1.
Pin # 1 2 8 9 17 18 24 25
Input Signals
Sym Description HDB3 Decoder #1 Positive Data Input. HDB3 Decoder #1 positive rail input clocked on the positive transitions of the clock signal MLCK1. HDB3 Decoder #1 Negative Data Input. HDB3 Decoder #1 negative rail input clocked on the positive transitions of the clock signal MLCK1. HDB3 Decoder #2 Positive Data Input. HDB3 Decoder #2 positive rail input clocked on the positive transitions of the clock signal MLCK2. HDB3 Decoder #2 Negative Data Input. HDB3 Decoder #2 negative rail input clocked on the positive transitions of the clock signal MLCK2. HDB3 Decoder #3 Positive Data Input. HDB3 Decoder #3 positive rail input clocked on the positive transitions of the clock signal MLCK3. HDB3 Decoder #3 Negative Data Input. HDB3 Decoder #3 negative rail input clocked on the positive transitions of the clock signal MLCK3. HDB3 Decoder #4 Positive Data Input. HDB3 Decoder #4 positive rail input clocked on the positive transitions of the clock signal MLCK4. HDB3 Decoder #4 Negative Data Input. HDB3 Decoder #4 negative rail input clocked on the positive transitions of the clock signal MLCK4. Multiplexer Tributary #1 Clock Input. Clock input for Multiplexer side tributary channel #1. This clock is used by both the associated HDB3 decoder and the Multiplexer. For standard rate applications, this clock must have a frequency of 50 ppm for 2048 kbit/s operation and 30 ppm for the 8448 kbit/s operation as per ITU G.703. Multiplexer Tributary #2 Clock Input. Idem as MLCK1 with tributary #2 in. Multiplexer Tributary #3 Clock Input. Idem as MLCK1 with tributary #3 in. Multiplexer Tributary #4 Clock Input. Idem as MLCK1 with tributary #4 in. Multiplexer Tributary #1 NRZ Data Input. Multiplexer tributary NRZ input clocked on the falling edge of the clock signal MLCK1. Multiplexer Tributary #4 NRZ Data Input. Multiplexer tributary NRZ input clocked on the falling edge of the clock signal MLCK2. Multiplexer Tributary #3 NRZ Data Input. Multiplexer tributary NRZ input clocked on the falling edge of the clock signal MLCK3. Multiplexer Tributary #4 NRZ Data Input. Multiplexer tributary NRZ input clocked on the falling edge of the clock signal MLCK4. Force AIS on Multiplexer Tributary #1. Active high signal to force AIS (all 1's) data and LREFCK clock on Multiplexer tributary #1. Force AIS on Multiplexer Tributary #2. Active high signal to force AIS (all 1's) data and LREFCK clock on Multiplexer tributary #2. Force AIS on Multiplexer Tributary #3. Active high signal to force AIS (all 1's) data and LREFCK clock on Multiplexer tributary #3. Force AIS on Multiplexer Tributary #4. Active high signal to force AIS (all 1's) data and LREFCK clock on Multiplexer tributary #4. Auxiliary Flag/Data #1 Input. The signal on this pin is clocked into the frame at the stuffing bit location (J1) when justification is such that tributary data is NOT placed at this location. A high on alarm signal MESA1 indicates this condition during the current frame. Auxiliary Flag/Data #2 Input. See AUXI1 Description. MESA2 is relevant indication signal. Auxiliary Flag/Data #3 Input. See AUXI1 Description. MESA3 is relevant indication signal. Auxiliary Flag/Data #4 Input. See AUXI1 Description. MESA4 is relevant indication signal.
MLDPI1 MLDNI1 MLDPI2 MLDNI2 MLDPI3 MLDNI3 MLDPI4 MLDNI4
7
MLCK1
14 23 30 5 12 21 28 6 13 22 29
MLCK2 MLCK3 MLCK4 MLNRZI1 MLNRZI2 MLNRZI3 MLNRZI4 MLFAIS1 MLFAIS2 MLFAIS3 MLFAIS4
66 75 76 77
AUXI1 AUXI2 AUXI3 AUXI4
Datasheet
7
LXT6234-- E-Rate Multiplexer
Table 1.
Pin # 36 37
Input Signals (Continued)
Sym Description National Bit Input. National Bit input that is placed in the 12th bit of the frame as per ITU G.742, G.751 specifications. AIS/Error Bit Input. AIS Bit input that is placed in the 11th bit of the frame, as per ITU G.742, G.751 specifications. High speed Multiplexer Clock Input. Clock input for Multiplexer functions and NRZ high speed data output. For standard rate applications, this clock must have a frequency of 30 ppm for the 8448 kbit/s operation and 20 ppm for the 34368 kbit/s operation as per ITU G.703. HDB3 Encoder #5 NRZ Input. HDB3 Encoder #5 (High speed) NRZ input clocked on the rising edge of MHHDB3C. HDB3 Encoder #5 Clock Input. When used in conjunction with the Multiplexer, this pin should be tied to the high speed Multiplexer Clock, MHMUXC, P41. HDB3 Decoder #5 Positive Data Input. HDB3 Decoder #5 (High Speed) positive rail input clocked on the rising edge of DHHDB3C. HDB3 Decoder #5 Negative Data Input. HDB3 Decoder #5 (High Speed) positive rail input clocked on the rising edge of DHHDB3C. HDB3 Decoder #5 Clock Input. When used in conjunction with the Demultiplexer, this pin should be tied to the high speed Demultiplexer Clock, DHMUXC, P57. Demultiplexer NRZ Data Input. Demultiplexer NRZ input clocked on rising edge of DHDMXC. High speed Demultiplexer Clock Input. Clock input for Demultiplexer functions and NRZ high speed data in. For standard rate applications, this clock must have a frequency of 30 ppm for the 8448 kbit/s operation and 20 ppm for the 34368 kbit/s operation as per ITU G.703. HDB3 Encoder #1 NRZ Data Input. HDB3 Encoder #1 NRZ input clocked on rising edge of DLCI1. HDB3 Encoder #2 NRZ Data Input. HDB3 Encoder #2 NRZ input clocked on rising edge of DLCI2. HDB3 Encoder #3 NRZ Data Input. HDB3 Encoder #3 NRZ input clocked on rising edge of DLCI3. HDB3 Encoder #4 NRZ Data Input. HDB3 Encoder #4 NRZ input clocked on rising edge of DLCI4. HDB3 Encoder #1 Clock Input. Clock input for HDB3 Encoder #1. HDB3 Encoder #2 Clock Input. Clock input for HDB3 Encoder #2. HDB3 Encoder #3 Clock Input. Clock input for HDB3 Encoder #3. HDB3 Encoder #4 Clock Input. Clock input for HDB3 Encoder #4. E12/E23 Mode Select. Mode selection for multiplexer/demultiplexer operation. A low signal selects 4E1/E2 multiplexing. A high signal selects 4E2/E3 multiplexing. Tributary Reference Clock. This clock is used as a reference for the Force AIS functions (See Pin 6 Description). For standard rate applications, this clock must have a frequency of 50 ppm for the 2048 kbit/s operation and 30 ppm for the 8448 kbit/s operation as per ITU G.703. Chip Enable. A high signal forces all outputs into tri-state; used for PCB Testing. This signal should be low for normal operation. Reset. An active low reset pin. Must be pulsed low on power up to initialize all internal circuits after VCC and clocks are stable. Ground. Ground Reference. Voltage. 5-volt supply voltage.
MNAT MAIS
41
MHMUXC
44 45 48 49 50 56 57 82 86 92 96 83 87 93 97 54
MHNRZI MHHDB3C DHDPI DHDNI DHHDB3C DHNRZI DHDMXC DLNRZI1 DLNRZI2 DLNRZI3 DLNRZI4 DLCI1 DLCI2 DLCI3 DLCI4 MODE
100
LREFCK
60 63 15, 40 65, 90 16, 39 64, 91
CE RSTN GND VCC
8
Datasheet
E-Rate Multiplexer -- LXT6234
Table 2.
Sym MLNRZO1 MLNRZO2 MLNRZO3 MLNRZO4 MLBPV1 MLBPV2 MLBPV3 MLBPV4
Output Signals
Pin # 4 11 20 27 3 10 19 26 Description HDB3 Decoder #1 NRZ Output. HDB3 Decoder #1 NRZ output clocked on the rising edge of MLCK1. HDB3 Decoder #2 NRZ Output. HDB3 Decoder #2 NRZ output clocked on the rising edge of MLCK2. HDB3 Decoder #3 NRZ Output. HDB3 Decoder #3 NRZ output clocked on the rising edge of MLCK3. HDB3 Decoder #4 NRZ Output. HDB3 Decoder #4 NRZ output clocked on the rising edge of MLCK4. HDB3 Decoder #1 Bipolar Violation Alarm. This open collector output pulses every time a bipolar violation occurs in the decoding process. HDB3 Decoder #2 Bipolar Violation Alarm. This open collector output pulses every time a bipolar violation occurs in the decoding process. HDB3 Decoder #3 Bipolar Violation Alarm. This open collector output pulses every time a bipolar violation occurs in the decoding process. HDB3 Decoder #4 Bipolar Violation Alarm. This open collector output pulses every time a bipolar violation occurs in the decoding process. Multiplexer Tributary #1 Elastic Store Alarm Indication. Multiplexer justification status for tributary #1. A high indicates bit stuffing on the current frame. A low indicates an information bit. When externally filtered, this signal can be used to indicate elastic store failure or incorrect tributary frequency. Multiplexer Tributary #2 Elastic Store Alarm Indication. Idem as MESA1 with tributary channel 2. Multiplexer Tributary #3 Elastic Store Alarm Indication. Idem as MESA1 with tributary channel 3. Multiplexer Tributary #4 Elastic Store Alarm Indication. Idem as MESA1 with tributary channel 4. High speed Multiplexer NRZ Output. Multiplexer NRZ data clocked out on the rising edge of MHMUXC. HDB3 Encoder #5 Positive Data Output. HDB3 Encoder #5 Positive rail clocked out on the rising edge of MHHDB3C. HDB3 Encoder #5 Negative Data Output. HDB3 Encoder #5 Negative rail clocked out on the rising edge of MHHDB3C. Demux Tributary #1 NRZ Output. This signal is clocked out on the rising edge of DHDMXC and transitions are coincident with the falling edge of DLCO1. Demux Tributary #2 NRZ Output. This signal is clocked out on the rising edge of DHDMXC and transitions are coincident with the falling edge of DLCO2. Demux Tributary #3 NRZ Output. This signal is clocked out on the rising edge of DHDMXC and transitions are coincident with the falling edge of DLCO3. Demux Tributary #4 NRZ Output. This signal is clocked out on the rising edge of DHDMXC and transitions are coincident with the falling edge of DLCO4. Demux Tributary #1 Clock Output. Demultiplexer side recovered clock of tributary #1. This clock has a duty cycle of 75% and is gapped at points in the frame where tributary data is not present (i.e., frame word). The maximum gap is 3 clocks at the frame word location. The frequency will match that of the far end multiplexer tributary input. This signal is clocked out on the rising edge of DHDMXC. Demux Tributary #2 Clock Output. Demultiplexer side recovered clock of tributary #2. See DLCO1 description. Demux Tributary #3 Clock Output. Demultiplexer side recovered clock of tributary #3. See DLCO1 description. Demux Tributary #4 Clock Output. Demultiplexer side recovered clock of tributary #4. See DLCO1 description. HDB3 Encoder #1 Output +. HDB3 Encoder #1 positive rail output clocked out on the rising edge of DLCI1.
MESA1
32
MESA2 MESA3 MESA4 MHNRZO MHDPO MHDNO DLNRZO1 DLNRZO2 DLNRZO3 DLNRZO4
33 34 35 42 46 47 74 72 70 68
DLCO1
73
DLCO2 DLCO3 DLCO4 DLDPO1
71 69 67 84
Datasheet
9
LXT6234-- E-Rate Multiplexer
Table 2.
Sym DLDNO1 DLDPO2 DLDNO2 DLDPO3 DLDNO3 DLDPO4 DLDNO4 DHNRZO DHBPV AUXO1 AUXO2 AUXO3 AUXO4 DNAT
Output Signals (Continued)
Pin # 85 88 89 94 95 98 99 52 53 78 79 80 81 62 Description HDB3 Encoder #1 Output -. HDB3 Encoder #1 negative rail output clocked out on the rising edge of DLCI1. HDB3 Encoder #2 Output +. HDB3 Encoder #2 positive rail output clocked out on the rising edge of DLCI2. HDB3 Encoder #2 Output -. HDB3 Encoder #2 negative rail output clocked out on the rising edge of DLCI2. HDB3 Encoder #3 Output +. HDB3 Encoder #3 positive rail output clocked out on the rising edge of DLCI3. HDB3 Encoder #3 Output -. HDB3 Encoder #3 negative rail output clocked out on the rising edge of DLCI3. HDB3 Encoder #4 Output +. HDB3 Encoder #4 positive rail output clocked out on the rising edge of DLCI4. HDB3 Encoder #4 Output -. HDB3 Encoder #4 negative rail output clocked out on the rising edge of DLCI4. HDB3 Decoder #5 NRZ Data Output. HDB3 Decoder #5 NRZ data clocked out on the rising edge of DHHDB3C. HDB3 Decoder #5 Bipolar Violation Alarm. This active high signal pulses every time a bipolar violation occurs in the decoding process. Auxiliary Flag/Data #1 Output. Auxiliary Data #1 output that contains data value input on AUXI1. See AUXI1 Description. Auxiliary Flag/Data #2 Output. Auxiliary Data #2 output that contains data value input on AUXI2. See AUXI1 Description. Auxiliary Flag/Data #3 Output. Auxiliary Data #3 output that contains data value input on AUXI3. See AUXI1 Description. Auxiliary Flag/Data #4 Output. Auxiliary Data #4 output that contains data value input on AUXI4. See AUXI1 Description. National Bit Output. Updated every frame based on the contents of the 12th bit in the frame as per ITU G.742, G.751 Demultiplexer Input AIS Detect. Active high alarm occurs when an all 1's condition (AIS) is detected at the DHNRZI input. This alarm will not occur if the input is a framed signal (i.e. all tributaries are AIS on multiplexer side). Demultiplexer Loss of Frame Alarm. Active high Frame Loss Alarm that occurs when the Demux has not detected the Frame word. Multiplexer Frame Sync Pulse. Pulse of one high speed clock cycle synchronous with the last bit of the frame (just before the frame word of the next frame). Dmx Frame Sync Pulse. Pulse of one high speed clock cycle synchronous with the first bit of the frame word of the high speed incoming signal. AIS Error Bit Output. Updated every frame based on the contents of the 11th bit in the frame as per ITU G.742 and G.751. Not Connected. These pins must be left unconnected.
DHAISD
58
FLOS MSYNC DSYNC DAIS NC
59 38 55 61 31, 43 51
10
Datasheet
E-Rate Multiplexer -- LXT6234
3.0
Functional Description
The LXT6234 E-Rate Multiplexer consists of a multiplexer block, a demultiplexer block, five HDB3 decoders, and five HDB3 encoders. If the HDB3 codecs are used, the signal flow would be as follows: Multiplexer: Four tributaries of data feed HDB3 decoders one through four. The NRZ outputs of the decoders are connected to the multiplexer tributary inputs. Within the multiplexer, the justification or stuffing for each tributary is determined; the frame word is added; and the high speed NRZ data sent out. The multiplexer output is connected to HDB3 encoder five where it is encoded and sent out as Positive Data Output (MHDPO) and Negative Data Output (MHDNO). Demultiplexer: High speed encoded data feeds the HDB3 decoder five and is output as NRZ data. The decoder output is connected to the demultiplexer input where it enters both the frame search circuitry and the demultiplexing circuitry. Once the frame is detected, the NRZ data is demultiplexed into the four tributaries and the justification is removed. Tributary data is then sent out in NRZ format. These tributary outputs, both Clock Output (DLCOx) and NRZ Output (DLNRZOx), are connected to HDB3 encoders one through four, encoded, and output as Positive Data (MHDPO) and Negative Data (MHDNO).
3.1
Frame Format
The multiplexer and demultiplexer share the Mode Select (MODE) control pin. When MODE is low, the multiplexer conforms to the ITU G.742 format for four-E1 to E2 (Figure 4). An E2 frame is 848 bits long, with 205 data bits and one justification bit for each E1 tributary. When MODE is high, the multiplexer conforms to the ITU G.751 format for four-E2 to E3 (Figure 5). This E3 frame is 1536 bits long, with 377 data bits and one justification bit for each E2 tributary. In both E2 and E3 formats, there are two flag bits per frame: the AIS bit and the National bit. The four justification bits may also be used as additional flag bits.
3.2
HDB3 Codecs
Five HDB3 codecs are included within the LXT6234 to allow easy integration with a wide range of line interface circuits. There are four low speed codecs for the tributary streams and one high speed codec to process the high speed output data. All five codecs are identical and all I/O pins are externally accessible for each device. All codecs can be operated at the maximum operating speed if the chip is used as a stand alone HDB3 transcoder. Note that the "low speed" decoders share a clock with the multiplexer tributary clocks. Each HDB3 decoder is provided with Positive Data, Negative Data, and clock; they decode the data into a single NRZ bit stream. The HDB3 encoders are provided with NRZ data and clock; they produce the Positive Data and Negative Data bit streams.
Datasheet
11
LXT6234-- E-Rate Multiplexer
3.3
HDB3 Decoder Alarms
A Bipolar Violation Alarm (MLBPVx, DHBPV) associated with each HDB3 decoder indicate detection of a coding violation error within the data. Coding violations include Bipolar Violations, a string of more than four zeros in a row, or encoding violations. The active high alarm is one clock cycle in duration.
3.4
Multiplexer
The multiplexer formats four low speed NRZ tributaries into a single high speed bit stream (Figure 3). Tributary data rates are synchronized via internal elastic store memories using a positive justification process as specified in the ITU recommendations.
Figure 3. Multiplexer Side Block Diagram
MLDPI[1:4] MLDNI[1:4] HDB3 Decoder #[1:4]
MLNRZ0[1:4] MLBPV[1:4] MESA[1:4]
MLCK[1:4] MLFAIS[1:4] MLNRZI[1:4]
Elastic Store
Multiplexer And Timing Control
MHNRZO
LREFCK MNAT MAIS AUXI[1:4] MHMUXC MHNRZI MHHDB3C HDB3 Encoder #5
MSYNC
MHDPO MHDNO
Data enters a first-in/first-out (FIFO) elastic store block. The FIFO receives the data along with the tributary clock and a pointer generated from the timing control. The output of the elastic store block is clocked by the tributary enable pulses from the timing control, and the data is finally processed by the multiplexer. Processing normally places the output data bit into the high speed bit stream during the tributary enable. An once-per-frame exception occurs during justification. During this event the location of the pointer in the FIFO is determined and a decision made for justification. If the elastic store is less than half full, a justification bit (used for the auxiliary flag channels) is placed in the bit stream and the MESAx pin is set high. When the elastic store becomes over half full, a tributary bit is clocked out from the FIFO, placed in the bit stream, and the MESAx pin set low. There are three justification indicators spread throughout the frame to show the status of the justification bit to the demultiplexer. Finally, the National and AIS bits are added at the beginning of each frame, and the bit stream is clocked out on MHNRZO. The multiplexer timing control receives a high speed clock and generates the frame structure and timing control according to the bit length of each frame. This is 848 bits for an E2 frame, and 1536 bits for an E3 frame. MODE provides for either E2 or E3 selection.
12
Datasheet
E-Rate Multiplexer -- LXT6234
In case of tributary transmission failure or the loss of a signal, tributary data can be forced to an all 1's state. For each tributary this function is controlled at the MLFAISx pin. Figure 4. E2 Frame
213 J1 425 J1 637 J1 J2 J3 J4 J2 J3 J4 641 S1 S2 S3 S4 645 204 E1 J2 J3 J4 429 208 E1 217 208 E1
4xE1 F1...F10 J1...J4 S1...S4 AIS NAT
Tributaries Data 205 Frame Bits 1 Justification Ind. 4 Justification Bits Auxiliary Bits 1 Alarm Bit 1 National Bit 1 Total
x 4 820 x 10 10 x 3 12 x4 x1 x1 4 1 1 848
Figure 5. E3 Frame
F1 385 J1 769 J1 1153 J1 J2 J3 J4 J2 J3 J4 1157 S1 S2 S3 S4 1161 376 E2 J2 J3 J4 773 380 E2 F2 F3 F4 F5 389 380 E2 F6 F7 F8 F9 F10 AIS NAT 372 E2
4xE2 F1...F10 J1...J4 S1...S4 AIS NAT
Tributaries Data 377 x 4 1508 10 Frame Bits 1 x 10 12 Justification Ind. 4x 3 Justification Bits 4 Auxiliary Bits 1x 4 1 Alarm Bit 1x 1 1 National Bit 1x 1 Total 1536
3.4.1
Flag Bits
Two flag bits, defined as the National Bit (MNAT) and AIS/Error Bit (MAIS) are transmitted with each frame. At the appropriate time the bit values of the MNAT and MAIS inputs are inserted into the frame. There are also four auxiliary flag channels available (AUXIx) that use the justification bit. These flags are placed in the frame approximately 40% of the time, depending on the ratio of the tributary clock to the multiplexer clock. A high on MESAx indicates that the AUXIx flag will be inserted into the current frame.
Datasheet
13
LXT6234-- E-Rate Multiplexer
3.4.2
Multiplexer Alarms
An indicator bit (MESAx) for each tributary monitors the status of the elastic store memory. This pin provides the justification status of the tributary. Under normal conditions this pin toggles at the frame rate with a 40% duty cycle. Large variation of the duty cycle indicates the tributary clock frequency is out of specification. Loss of clock would cause MESA to assume a rail value. For use as a frequency alarm this signal should be filtered by a single-pole RC filter far below the frame frequency, and connected to a pair of voltage comparators. The unfiltered alarm signal can be used to clock the auxiliary data channel inputs.
3.5
Demultiplexer
Data entering the demultiplexer is sent to both the demultiplexing block and the framer. The framer, using a Sieve algorithm, examines the incoming data to find the framing word. A frame is declared found when three passes show the frame word has been found at the same location within the frame. The timing module is then synchronized to the incoming data frame and the Frame Loss Alarm turns off. Valid tributary data can be extracted after the frame is found. For each tributary, three justification indicator bits are stored. A majority-rule determination decides whether the justification bit is sent as tributary data (with clock) or as an auxiliary bit (with no clock). The DNAT and DAIS flag bits are updated for each frame and sent to their dedicated pins. The auxiliary flag bits AUXOx are updated when they are available on the frame.
3.5.1
Demultiplexer Alarms
The demultiplexer has two active-high alarms: Frame Loss (FLOS), and Demultiplexer Input AIS Detect (DHAISD).
* FLOS is active at power-up and clears after three consecutive frames are detected. During
normal operation FLOS becomes active after missing four consecutive frames.
* DHAISD activates after 768 consecutive 1's pass through the high speed NRZ data stream.
DHAISD will occasionally glitch if four tributaries are all 1's and the justification of all four channels is identical. This glitch is filtered with a single-pole RC filter.
14
Datasheet
E-Rate Multiplexer -- LXT6234
.
Figure 6. Demultiplexer Side Block Diagram
4 4 DHNRZI Demultiplexer DHDMXC And Timing Control MODE 4
DLNRZO[1:4] DLCO[1:4]
DNAT DAIS AUXO[1:4] DSYNC FLOS DHAISD
DHDPI DHDNI DHHDB3C HDB3 Encoder #[1:4] HDB3 Decoder DHNRZO DHBPVO
DLNRZI[1:4] DLCI[1:4]
4 4
4 4
DLDPO[1:4] DLDNO[1:4]
Datasheet
15
LXT6234-- E-Rate Multiplexer
4.0
Glossary
AIS AMI Alarm Indication Signal. Alternate Mark Inversion.
CCITT Consultative Committee for International Telegraph and Telephone (now called the International Telecommunications Union - ITU). CODEC COder/DECoder; An assembly comprising an encoder and a decoder within the same unit. HDB3 High Density Bipolar code of order 3, extension of AMI. E1 E2 E3 FIFO ITU NRZ PCB RZ The primary European digital rate of 2.048 MHz, or thirty-two 64 KB channels. The secondary European rate, four E1 channels at 8.448 MHz. The tertiary European rate, four E2 channels at 34.368 MHz. First-in/First-Out Memory. International Telecommunications Union. Non-Return to Zero. Printed Circuit Board. Return to Zero.
16
Datasheet
E-Rate Multiplexer -- LXT6234
5.0
5.1
Application Information
E1/E3 Multiplexer Block Diagram
Figure 7 is a block diagram of the E1/E3 Multiplexer.
Figure 7. E1/E3 Multiplexer Block Diagram
tcy
MLCKx MHHDB3C DLCIx DHHB3C
tpw
tsu
MLDPIx MHNRZI DHDNI MLDNIx DHDPI DLNRZIx
th
tpd
MLNRZOx MHDPO DHNRZO DLDPOx MLBPVx MHDNO DHBPV DLDNOx
5.1.1
E1 Line Interface * Receive clocks from the pulse data. * Pass either HDB3 encoded signals to the E-Rate Multiplexer as clock and RZ data or as NRZ
data1. (Both positive and negative RZ data.)
5.1.2
LXT6234, E1/E2 Stage * The LXT6234 may interface with either HDB3 or non-HDB3 coded signals. Data from an LIU
that does not perform HDB3 decoding must be connected to the HDB3 inputs on the LXT6234. These are the clock (MLCKx) and decoder data input signals (both positive MLDPx and negative - MLDNx). When receiving data from an LIU which does perform HDB3 decoding, the NRZ data is connected to the MLNRZx input and the clock connects to the MLCKx in on the LXT6234
* The four tributaries are interleaved into a single, intermediary E2 rate data stream. An
on-board crystal oscillator drives the data output frequency from the mux at the E2 rate of 8.448 MHz. A bit stuffing algorithm implemented in the LXT6234 ensures tributary rate integrity at the output. The LXT6234 contains elastic store buffers to manage bit-stuffing process.
* The NRZ data is sent to a tributary of the E-Rate Multiplexer, stage E2/E3.
1. If the HDB3 decoder is on the line interface unit (LIU).
Datasheet
17
LXT6234-- E-Rate Multiplexer
5.1.3
LXT6234, E3 Stage * The multiplexer portion of the LXT6234 interleaves four asynchronous E2 rate NRZ data
streams into a single E3 data stream. Depending on the configuration, either an on-board crystal oscillator or an external reference clock drives the data output frequency from the mux at the rate of 34.368 Mbps. The bit stuffing algorithm implemented in the LXT6234 ensures tributary rate integrity at the output.
* If the LIU provides HDB3 encoding, then the NRZ data and clock are passed to the E3 line
interface.
* If the LIU does not provide HDB3 encoding, then encoding is done by the LXT6234 and data
is output as positive and negative data. An activity monitor provides tributary fail notification when necessary. See Application Note 9501 for additional information.
18
Datasheet
E-Rate Multiplexer -- LXT6234
6.0
Note:
Test Specifications
Minimum and maximum values in Tables 3 through 9 and Figure 8 through Figure 12 represent the performance specifications of the LXT6234 E-Rate Multiplexer and are guaranteed by test except, where noted, by design. Typical values are not subject to production testing. The LXT6234 E-Rate Multiplexer, fabricated with 0.8-micron CMOS technology, is currently available in a 100-pin plastic quad flat pack package (EIAJ standard 100PQFP). All device I/O comply with 5V CMOS standards. A list of input and output signals is provided with this data sheet. There are 46 input signals and 43 output signals. In addition, there are four VCC power pins and four Ground power pins. A Chip Enable is provided to facilitate board level, in-circuit testing during the PCB manufacturing process. The LXT6234 E-Rate Multiplexer is fully tested before shipment.
Table 3.
Absolute Ratings
Parameter Symbol VDD VIN
IIN
Min -0.3 0 -- -40 -55
Max 7.0 VDD+ 0.3 10 +85 +150
Units V V A
DC Supply Voltage Input Voltage Input Current Ambient Operating Temperature Storage Temperature
TAM TSTG
C C
CAUTION: Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 4.
DC Characteristics (TA=-40 to +85xC, Vdd=+5V5%, GND=0 V)
Symbol VIH VIL VOH VOL IIN IOZ PD IDD -- Min 0.7VDD -- 2.4 -- -10 -10 Typ -- -- 4.5 0.2 1 1 100 500 1 20 Max -- 0.3VDD -- 0.4 10 10 Units V V V V A A mW mW A Test Conditions VDD=5V5V CMOS IOH = Rated Current IOL = Rated Current VIN = VDD, VSS VOH = VDD or VSS VDD = 5.25 V1 VDD = 5.25 V VDD = 5.25 V
Parameter High level input voltage Low level input voltage High level output voltage Low level output voltage Input Current TriState leakage current Power dissipation 4E1/E2 mode 4E2/E3 mode Static current
Datasheet
19
LXT6234-- E-Rate Multiplexer
7.0
Note:
AC Timing Specifications
Unless otherwise specified, all timing specifications are referenced at ambient condition as TAmbient = -40 to 85C, VDD =+5V5%, GND = 0V.
Figure 8. HDB3 Encoder and Decoder Timing (Refer to Table 5)
tcy
MLCKx MHHDB3C DLCIx DHHB3C
tpw
tsu
MLDPIx MHNRZI DHDNI MLDNIx DHDPI DLNRZIx
th
tpd
MLNRZOx MHDPO DHNRZO DLDPOx MLBPVx MHDNO DHBPV DLDNOx
Table 5.
HDB3 Encoder and Decoder (Refer to Figure 8)
Parameter Symbol tPWH tSU tH tPD Min 40 5 6 -- Typ -- -- -- 15 Max 75 -- -- 25 Unit % ns ns ns
Clock duty cycle Data to clock setup time Data to clock hold time Clock to data propagation time (50pF capacitive load)
Figure 9. Multiplexer Tributary Input Timing (Refer to Table 6)
tcy tpw
MLCKx
tsu
MLNRZI
th
20
Datasheet
E-Rate Multiplexer -- LXT6234
Table 6.
Multiplexer Tributary Input (Refer to Figure 9)
Parameter Symbol tPWH tSU tH Min 40 5 5 Typ -- -- -- Max 60 -- -- Unit % ns ns
Clock duty cycle Data to clock setup time (falling edge) Data to clock hold time (falling edge)
Figure 10. High Speed Multiplexer Input & Output Timing (Refer to Table 7)
tCYC tPWH
MHMUXC
tSU
MAIS MNAT AUXI
tH
tPD
MHNRZO MESAx
Table 7.
High Speed Multiplexer Input & Output (Refer to Figure 10)
Symbol tPWH tSU tH tPD Min 40 5 6 -- Type -- -- -- 20 Max 60 -- -- 30 Unit % ns ns ns
Parameter Clock duty cycle Data to clock setup time Data to clock hold time Clock to data propagation time
Datasheet
21
LXT6234-- E-Rate Multiplexer
Figure 11. High Speed Demultiplexer Input & Output Timing (Refer to Table 8)
tCYC tPWH
DHDMXC
tSU
DHNRZI
tH
tPD
DLNRZOx DLCOx DNAT/DAIS AUXOx
Table 8.
High Speed Demultiplexer Input & Output (Refer to Figure 11)
Parameter Symbol tPWH tSU tH tPD 45 8 5 -- Min -- -- -- 20 Type 75 -- -- 30 Max % ns ns ns Unit
Clock duty cycle Data to clock setup time Data to clock hold time Clock to data propagation time
Figure 12. Chip Enable Timing (Refer to Table 9)
CE
ton
All Outputs
thz
Table 9.
Chip Enable (Refer to Figure 12)
Parameter Symbol tON tPWH Min 20 20 Type 30 30 Max ns ns Unit
CE to outputs enabled CE to outputs high impedance
22
Datasheet
E-Rate Multiplexer -- LXT6234
Figure 13. Package Specifications
100-Pin PQFP
* Part Number LXT6234QE * Extended Temperature Range
D D1 D3
Table 10. 100-Pin Plastic Quad Flat Packs
Inches Dim Min A A1 A2 - 0.010 0.100 0.009 0.931 0.783 Max 0.134 - 0.120 0.015 0.951 0.791 Min - 0.25 2.55 0.22 23.65 19.90 Max 3.40 - 3.05 0.38 24.15 20.10 Millimeters
E1 E3 E
B D D1 D3
0.742 REF 0.695 0.547 0.715 0.555
18.85 REF 17.65 13.90 18.15 14.10
1
D Side pin count = 30 pins E Side pin count = 20 pins for sides with even number of pins
E E1 E3
0.486 REF 0.026 BSC (nominal) 0.026 0.037
12.35 REF 0.65 BSC (nominal) 0.65 0.95
e/
e
2
L L1 q3
e
0.077 REF 5 0 16 7 5 0
1.95 REF 16 7
for sides with odd number of pins
q
BSC--Basic Spacing Between Centers
3
L1 A A1 L A2
3 B
Datasheet
23

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