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NLSF1174 Hex D Flip-Flop with Common Clock and Reset
This device consists of six D flip-flops with common Clock and Reset inputs. Each flip-flop is loaded with a low-to-high transition of the Clock input. Reset is asynchronous and active low. All inputs/outputs are standard CMOS compatible.
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* * * * * * *
Output Drive Compatibility: 10 LSTTL Loads Outputs Directly Interface to CMOS Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 mA MSL Level 1 Chip Complexity: 162 FET Pb-Free Package is Available*
1
QFN-16 MN SUFFIX CASE 485G
MARKING DIAGRAM
16
Q0 16
Reset 15
VCC 14
Q5 13
D0
1
12
D5
D1
2
11
D4
NLSF1174 A L Y W G
Q1
3
10
Q4
(Note: Microdot may be in either location)
D2
4
9
D3 Reset
5 Q2
6 GND
7 Clock
8 Q3
L H H H H
Center pad on bottom may be connected to VCC of device. This pad must be isolated or connected to VCC.
Figure 1. PIN ASSIGNMENT (Top View) ORDERING INFORMATION
Device NLSF1174MNR2 NLSF1174MNR2G Package QFN-16 Shipping 3000 / Tape & Reel
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Publication Order Number: NLSF1174/D
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May, 2006 - Rev. 5
CCC CCC
1 Inputs Clock X L
NLSF 1174 ALYW G G
= Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
FUNCTION TABLE
Output D X H L X X Q L H L No Change No Change
QFN-16 3000 / Tape & Reel (Pb-Free)
NLSF1174
D0 D1 DATA INPUTS D2 D3 D4 D5 CLOCK Q0 Q1 Q2 Q3 Q4 Q5 NONINVERTING OUTPUTS
RESET
Figure 2. LOGIC DIAGRAM DESIGN/VALUE TABLE
Design Criteria Internal Gate Count* Internal Gate Propagation Delay Internal Gate Power Dissipation Speed Power Product *Equivalent to a two-input NAND gate. Value 40.5 1.5 5.0 .0075 Unit ea ns mW pJ
MAXIMUM RATINGS
Parameter DC Supply Voltage DC Input Voltage DC Output Voltage DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Storage Temperature Range Lead Temperature, 1 mm from Case for 10 Seconds Junction Temperature Under Bias Thermal Resistance Power Dissipation in Still Air at 85C Moisture Sensitivity Flammability Rating ESD Withstand Voltage Oxygen Index: 30 to 35 Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) Above VCC and Below GND at 85C (Note 5) QFN QFN PDIP, SOIC, TSSOP (Referenced to GND) (Referenced to GND) (Referenced to GND) (Note 1) Symbol VCC VIN VOUT IIN IOUT ICC TSTG TL TJ qJA PD MSL FR VESD Value *0.5 to )7.0 *1.5 to VCC )1.5 *0.5 to VCC )0.5 $20 $25 $50 *65 to )150 260 )150 80 800 Level 1 UL 94 V-0 @ 0.125 in u2000 u100 u500 $300 V Unit V V V mA mA mA C C C C/W mW
Latchup Performance
ILATCHUP
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. IO absolute maximum rating must be observed. 2. Tested to EIA/JESD22-A114-A. 3. Tested to EIA/JESD22-A115-A. 4. Tested to JESD22-C101-A. 5. Tested to EIA/JESD78. 6. For high frequency or heavy load considerations, see the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
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NLSF1174
RECOMMENDED OPERATING CONDITIONS
Parameter DC Supply Voltage (Referenced to GND) Symbol VCC Min 2.0 0 Max 6.0 Unit V V
II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I
DC Input Voltage, Output Voltage (Referenced to GND) (Note 7) VIN, VOUT TA VCC Operating Temperature, All Package Types Input Rise and Fall Time (Figure 4) *55 0 0 0 )125 1000 500 400 C ns VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tr, tf 7. Unused inputs may not be left open. All inputs must be tied to a high- or low-logic input voltage level.
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Parameter Minimum High-Level Input Voltage Test Conditions VOUT = 0.1 V or VCC - 0.1 V |IOUT| v 20 mA VOUT = 0.1 V or VCC - 0.1 V |IOUT| v 20 mA VIN = VIH or VIL |IOUT| v 20 mA
VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0
Guaranteed Limit v855C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9
Symbol VIH
*555C to 255C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9
v1255C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4
Unit V
Maximum Low-Level Input Voltage
VIL
Minimum High-Level Output Voltage
VOH
VIN = VIH or VIL |IOUT| v 4.0 mA |IOUT| v 5.2 mA VIN = VIH or VIL |IOUT| v 20 mA
Maximum Low-Level Output Voltage
VOL
VIN = VIH or VIL |IOUT| v 4.0 mA |IOUT| v 5.2 mA
Maximum Input Leakage Current
VIN = VCC or GND
IIN ICC
Maximum Quiescent Supply Current (per Package)
VIN = VCC or GND IOUT = 0 mA
8. Information on typical parametric values, along with high frequency or heavy load considerations, can be found in the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Parameter Symbol fmax
Maximum Clock Frequency (50% Duty Cycle) (Figures 4 and 7) Maximum Propagation Delay, Clock to Q (Figures 5 and 7)
tPLH tPHL tPLH tPHL tTLH tTHL Cin
Maximum Propagation Delay, Reset to Q (Figures 2 and 7)
Maximum Output Transition Time, Any Output (Figures 4 and 7) Maximum Input Capacitance
62 pF Power Dissipation Capacitance, per Enabled Output (Note 10) CPD 9. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High-Speed CMOS Data Book (DL129/D). 10. Used to determine the no-load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
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II I I I IIIIIIIIIIIII I II II I II IIIIIIIIIIIII IIIIIIIIIIII I IIIIIIIIIIIII I II II I I II I I I IIIIIIIIIIIII IIIIIIIIIIII II I II IIIIIIIIIIIII I II IIIIIIIIIIIII I II II I I IIIIIIIIIIIII I II I IIIIIIIIIIIII IIIIIIIIIIII I II I IIIIIIIIIIIII I II I I II I I IIIIIIIIIIII IIIIIIIIIIIII I II II I I IIIIIIIIIIIII I II I IIIIIIIIIIIII I II IIIIIIIIIIIII I II I I IIIIIIIIIIIII I I IIIIIIIIIIIII I II I IIIIIIIIIIIII II I IIIIIIIIIIIII I II I IIIIIIIIIIIII IIIIIIIIIIII II I
V V 3.98 5.48 0.1 0.1 0.1 3.84 5.34 0.1 0.1 0.1 V 0.26 0.26 0.33 0.33 $0.1 4.0 $1.0 40 $1.0 160 mA mA VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Guaranteed Limit *555C to 255C 6.0 30 35 v855C 4.8 24 28 v1255C 4.0 20 24 Unit MHz 110 22 19 110 21 19 75 15 13 10 140 28 24 140 28 24 95 19 16 10 165 33 28 160 32 27 110 22 19 10 ns ns ns pF Typical @ 255C, VCC = 5.0 V
IIIIIIIIIIIIII I II I II I IIIIIIIIIIIIII I II II II II I I IIIIIIIIIIIIII I II I IIIIIIIIIIIII I IIIIIIIIIIIIII I II I IIIIIIIIIIIIII II II I II I IIIIIIIIIIIIII I II I IIIIIIIIIIIII I IIIIIIIIIIIIII I II I IIIIIIIIIIIIII I II I IIIIIIIIIIIIII I IIIIIIIIIIIIII I II II II II I I IIIIIIIIIIIIII I II I IIIIIIIIIIIIII IIIIIIIIIIII
IIIIIIII I I IIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIII IIIIIIIIII IIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIII I IIIIIIII I I IIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIII IIIIIIII I IIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIII IIIIIIIIIII IIIIIIII I IIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIII IIIIIIII I IIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIII IIIIIIIIIII IIIIIIIIIIIIIIIIII I IIIIIIII I IIIIIIIIIIIIIIIIII IIIIIIIIII IIIIIIIIIIIIIIIIII I IIIIIIII I IIIIIIIIIIIIIIIIII IIIIIIIIIII IIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII
II I I I I I I IIIIIII IIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIII IIIIIIII IIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIII I I IIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIII II IIIIIIIIIIIIIIII IIIIIIII IIIII IIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIII II IIIIIIIIIIIIIIII IIIIIIII IIIII IIII IIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIII II IIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIIII
VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 *555C to 255C Min 5.0 5.0 5.0 5.0 5.0 5.0 50 10 9.0 75 15 13 75 15 13 1000 500 400 Max Guaranteed Limit Min 5.0 5.0 5.0 5.0 5.0 5.0 95 19 16 95 19 16 65 13 11 v855C 1000 500 400 Max Min 110 22 19 110 22 19 5.0 5.0 5.0 5.0 5.0 5.0 75 15 13 v1255C 1000 500 400 Max Unit ns ns ns ns ns ns
IIIIIIIIIIIIIIII I IIIIIIIIIIIIIIII I IIIIIIIIIIIIIIII I IIIIIIIIIIIIIIII I I III I IIIIIIIIIIIIIIII IIIIIIIIIIIIII III I IIIIIIIIIIIIIIII I IIIIIIIIIIIIIIII IIIIIIIIIIIII III I IIIIIIIIIIIIIIII IIIIIIIIIIIIII IIIIIIIIIIIIIIII I IIIIIIIIIIIIIIII I III I IIIIIIIIIIIIIIII IIIIIIIIIIIIII IIIIIIIIIIIIIIII I III I IIIIIIIIIIIIIIII IIIIIIIIIIIIII
TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)
Maximum Input Rise and Fall Times Minimum Pulse Width, Reset Minimum Pulse Width, Clock Minimum Recovery Time, Reset Inactive to Clock Minimum Hold Time, Clock to Data Minimum Setup Time, Data to Clock Parameter Figure 4 5 4 5 6 6
CLOCK
RESET
D5
D4
D3
D2
D1
D0
Figure 3. Expanded Logic Diagram
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NLSF1174
Symbol
tr, tf
trec
tsu
tw
tw
th
4 D D D D D D C C C C C C R R R R R Q Q Q Q Q R Q Q5 Q4 Q3 Q2 Q1 Q0
NLSF1174
tr CLOCK 90% 50% 10% tw 1/fmax tPLH Q 90% 50% 10% tTLH tTHL tPHL Q trec 50% CLOCK GND VCC tf VCC GND tw 50% GND tPHL
RESET
VCC
Figure 4. Switching Waveform
Figure 5. Switching Waveform
VALID VCC DATA 50% GND tsu CLOCK th VCC 50% GND DEVICE UNDER TEST
TEST POINT OUTPUT
CL *
*Includes all probe and jig capacitance
Figure 6. Switching Waveform
Figure 7. Test Circuit
PIN1/PRODUCT ORIENTATION CARRIER TAPE
USER DIRECTION OF FEED
Figure 8.
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NLSF1174
PACKAGE DIMENSIONS
16 PIN QFN CASE 485G-01 ISSUE C
D
A B
PIN 1 LOCATION
E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.18 TYP 0.30 0.50
0.15 C 0.15 C 0.10 C TOP VIEW
16 X
0.08 C SIDE VIEW A1 C
16X
L
5
NOTE 5 4
16X
K
1 12
16X
b BOTTOM VIEW
0.10 C A B 0.05 C
NOTE 3
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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CC CC CC
(A3) D2 e
8 9 16 13
A
SEATING PLANE
DIM A A1 A3 b D D2 E E2 e K L
EXPOSED PAD
E2 e
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NLSF1174/D

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